JP3078811B1 - Method of forming wiring structure - Google Patents

Abstract

An interlayer insulating film having a low relative dielectric constant can be formed by employing a normal resist process. A first organic film is formed on a semiconductor substrate.
03, a silicon oxide film 604 and a second organic film 605 are sequentially deposited, and then a mask pattern 608 is formed on the second organic film 605. The organic insulating film 605 is etched using the second resist pattern 609 and the mask pattern 608 as a mask, and the second organic film 605 is etched.
And a second resist pattern 609
Is removed. Etching is performed on the silicon oxide film 604 using the patterned second organic film 605A as a mask to pattern the silicon oxide film 604.
The second organic film 605A is etched using the mask pattern 608 as a mask, and the first organic film 603 is etched using a silicon oxide film as a mask to form a wiring groove in the second organic film 605A. At the same time, a contact hole is formed in the first organic film 603.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a wiring structure in a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art With the advance of high integration of semiconductor integrated circuits, an increase in wiring delay time due to an increase in capacitance between wirings, which is a parasitic capacitance between metal wirings, hinders high performance of semiconductor integrated circuits. It has become. The wiring delay time is a so-called RC delay that is proportional to the product of the resistance of the metal wiring and the capacitance between the wirings.

Therefore, in order to reduce the wiring delay time, it is necessary to reduce the resistance of the metal wiring or reduce the capacitance between the wirings.

Accordingly, IBM and Motorola have reported semiconductor integrated circuit devices that use copper instead of an aluminum alloy as a wiring material in order to reduce wiring resistance.
Copper material has a specific resistance of about two-thirds that of aluminum-based alloy material. Therefore, when copper material is used as the wiring material, the wiring delay time is calculated more simply than when aluminum-based alloy material is used. Is reduced to two-thirds, so that a speedup of 1.5 times can be realized.

However, as the degree of integration of the semiconductor integrated circuit further increases, there is a concern that even if metal wiring made of copper is used, the speeding up will reach its limit due to an increase in wiring delay time. Copper as a wiring material is
Since the specific resistance is smaller than that of gold or silver, even if a metal wiring made of gold or silver is used instead of a metal wiring made of copper, the wiring resistance is slightly reduced.

For this reason, it is important to reduce the wiring resistance and the capacitance between the wirings in order to increase the integration of the semiconductor integrated circuit. It is necessary to reduce the dielectric constant. Conventionally, a silicon oxide film has been used as an interlayer insulating film. The relative dielectric constant of the silicon oxide film is about 4 to 4.5, and the silicon oxide film is used as an interlayer insulating film in a highly integrated semiconductor integrated circuit. Is difficult to adopt.

Therefore, as an interlayer insulating film having a relative dielectric constant smaller than that of a silicon oxide film, a fluorine-added silicon oxide film,
Low dielectric constant SOG films and organic polymer films have been proposed.

[0008]

Incidentally, the relative dielectric constant of the fluorine-doped silicon oxide film is 3.3 to 3.7,
Although about 20% smaller than the conventional silicon oxide film, the fluorine-added silicon oxide film has high hygroscopicity, and thus easily absorbs moisture in the atmosphere. For this reason, since the fluorine-added silicon oxide film absorbs moisture and SiOH having a high relative dielectric constant is taken into the film, the relative dielectric constant of the fluorine-added silicon oxide film increases, or SiOH reacts in the heat treatment step. And release of H ₂ O gas during the heat treatment process, the fluorine liberated in the fluorine-added silicon oxide film segregates on the surface during the heat treatment process, and the segregated fluorine reacts with Ti or the like of the TiN film as the adhesion layer. There is a problem of forming a TiF film which is easily peeled off, and the fluorine-added silicon oxide film has many practical problems.

As a low dielectric constant SOG film, HSQ (Hydr
ogen silsesquioxane: a structure composed of Si atoms, O atoms, and two-thirds of H atoms) H) films are being studied, but HSQ films are compared with conventional silicon oxide films. Therefore, there is a problem that workability is poor due to a large amount of released water. It is difficult to form a buried wiring in the HSQ film because the HSQ film has poor workability. Therefore, when forming a metal wiring in the HSQ film, it is necessary to use a metal wiring in which the metal film is patterned.

Further, since the HSQ film has low adhesion to the metal wiring, it is necessary to form a CVD oxide film as an adhesion layer between the HSQ film and the metal wiring in order to secure the adhesion to the metal wiring. However, when a CVD oxide film is formed on a metal wiring, a substantial inter-wiring capacitance is formed between the HSQ film and the CVD oxide film because a CVD oxide film having a large relative dielectric constant exists between the metal wirings. Since the capacitance becomes the capacitance, there is a problem that the capacitance between the wirings is increased as compared with the case where the HSQ film is used alone.

Since the organic polymer film has low adhesion to the metal wiring like the low dielectric constant SOG film, it is necessary to form a CVD oxide film as an adhesion layer between the organic polymer film and the metal wiring.

Further, since the etching rate of the organic polymer film is substantially equal to the ashing rate when the resist pattern is ashed by oxygen plasma, the organic polymer film is damaged when the resist pattern is removed by ashing. The problem is that the resist process cannot be used. Therefore, a method is proposed in which a CVD oxide film is formed on an organic polymer film, a resist film is formed on the CVD oxide film, and the resist film is etched using the CVD oxide film as an etching stopper (protective film). Have been.

However, when a CVD oxide film is formed on an organic polymer film, the surface of the organic polymer film is exposed to a reactive gas containing oxygen, so that the organic polymer film reacts with oxygen to form an organic film. Since a polar group such as a carbonyl group or a ketone group is introduced into the polymer film, there is a problem that the relative dielectric constant of the organic polymer film increases.

Further, when copper embedded wiring is formed in the organic polymer film, since the organic polymer film has low adhesion to metal wiring, the organic polymer film has, for example, a peripheral surface of a wiring recess formed in the organic polymer film. It is necessary to form an adhesion layer made of TiN or the like. However, since the TiN film has a high resistance, the effective cross-sectional area of the metal wiring is reduced. Therefore, there is an advantage that the resistance is reduced by using a metal wiring made of copper. There is a problem of being damaged.

In view of the foregoing, it is an object of the present invention to form an interlayer insulating film having a low relative dielectric constant by employing a normal resist process.

[0016]

A method of forming a wiring structure according to the present invention comprises the steps of forming a first insulating film on a lower metal wiring, and forming the first insulating film on the first insulating film. Forming a second insulating film having a different composition from the second insulating film; forming a third insulating film having a different composition from the second insulating film on the second insulating film; Forming a thin film on the insulating film, forming a first resist pattern having a wiring forming opening on the thin film, and etching the thin film using the first resist pattern as a mask Forming a mask pattern made of a thin film and having an opening for forming a wiring, and after removing the first resist pattern, forming an opening for forming a contact hole on the third insulating film and the mask pattern. Step of forming a second resist pattern By performing dry etching on the third insulating film using the second resist pattern and the mask pattern as a mask, an opening for forming a contact hole is formed in the third insulating film in the third insulating film. The second insulating film into contact holes by performing dry etching using the third insulating film patterned on the second insulating film as a mask. Performing a patterning process so that a formation opening is formed, performing dry etching on the patterned third insulating film using a mask pattern as a mask, and performing patterning on the first insulating film. By performing dry etching using the formed second insulating film as a mask, a wiring groove is formed in the patterned third insulating film, and the first insulating film is formed. An eleventh step of forming a contact connecting the upper metal wiring and the lower metal wiring with the upper metal wiring by filling the wiring groove and the contact hole with a metal film. It has.

According to the method of forming a wiring structure according to the present invention, when dry etching is performed on the third insulating film, the second insulating film is present on the first insulating film. Therefore, the first insulating film is not damaged.
Therefore, as the first insulating film, an insulating film which is damaged by dry etching but has a low relative dielectric constant can be used. Therefore, an interlayer insulating film having a low relative dielectric constant can be formed while adopting a normal resist process. Can be formed.

In addition, dry etching is performed on the patterned third insulating film using the mask pattern as a mask, and dry etching is performed on the first insulating film using the patterned second insulating film as a mask. Is performed to form a wiring groove in the patterned third insulating film and to form a contact hole in the first insulating film, that is, to form the wiring groove and the contact hole by the same etching process. Therefore, a dual damascene structure can be formed while suppressing an increase in the number of steps.

In the method for forming a wiring structure according to the present invention, the first insulating film preferably contains an organic component as a main component.

By doing so, the relative dielectric constant of the interlayer insulating film can be further reduced.

In the method for forming a wiring structure according to the present invention, the dimension of the contact hole forming opening of the second resist pattern is set in the direction in which the metal wiring of the upper layer extends with respect to the designed opening dimension of the contact hole. Preferably, it is enlarged in a vertical direction.

Thus, even if the contact hole forming opening of the second resist pattern is misaligned with respect to the wiring forming opening of the mask pattern, the contact hole is formed in the patterned third insulating film. Since the contact hole forming opening to be formed is formed in an overlapping area of the contact hole forming opening of the second resist pattern and the wiring forming opening of the mask pattern, the patterned third insulating film is formed. The contact hole forming opening is formed in the region of the wiring forming opening of the mask pattern in a self-aligned manner. Therefore, the connection between the contact and the upper metal wiring can be reliably ensured.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described. In each embodiment, the organic film includes both a film composed of only organic components and a film composed mainly of organic components. Concept. In each embodiment,
The film containing an organic component as a main component may be changed to a film containing only an organic component, or the film containing only an organic component may be changed to a film containing an organic component as a main component.

(First Embodiment) Hereinafter, a method for forming a wiring structure according to a first embodiment of the present invention will be described with reference to FIG.
(A)-(c), FIGS. 2 (a)-(c) and FIGS. 3 (a)-
This will be described with reference to FIG.

First, as shown in FIG. 1A, a first metal wiring 101 formed on a semiconductor substrate 100 is
After a silicon nitride film 102 having a thickness of, for example, 50 nm for protecting the first metal wiring 101 is formed in an etching process performed later, the silicon nitride film 102 is formed.
A first organic film 103 (first insulating film) having a thickness of, for example, 1 μm and containing an organic component as a main component is deposited thereon. Next, on the first organic film 103, for example, 50
After depositing an organic-containing silicon oxide film 104 (second insulating film) having a thickness of nm and containing an organic component in the silicon oxide, a film of, for example, 400 nm is formed on the organic-containing silicon oxide film 104. A second organic film 105 (third insulating film) having a thickness and containing an organic component as a main component is deposited, and then, for example, 5
A titanium nitride film 106 having a thickness of 0 nm is deposited.

The method for depositing the first and second organic films 103 and 105 is not particularly limited, but for example, a plasma CVD method using a reactive gas containing perfluorodecalin as a main material is exemplified. In addition, as the first and second organic films 103 and 105, a hydrocarbon film or a fluorine-containing hydrocarbon film formed by a plasma CVD method, a coating method, or a thermal CVD method can be used.

As a method for depositing the first organic film 103, for example, a reactive gas mainly containing perfluorodecalin and an organic silane such as hexamethyldisiloxane, allylalkoxysilane or alkylalkoxysilane is used. The plasma CVD method may be used. By doing so, an organic-inorganic hybrid film is obtained.

The method of depositing the organic-containing silicon oxide film 104 is not particularly limited, but includes, for example, a CVD method using a reactive gas containing phenyltrimethoxysilane as a main material. Thus, an organic-containing silicon oxide film 104 having a structure in which a phenyl group bonded to a silicon atom is incorporated in silicon oxide is obtained.

It should be noted that, instead of the titanium nitride film 106, it has a high etching selectivity with respect to the first and second organic films 103 and 105 and the organic-containing silicon oxide film 104.
That is, a thin film having a sufficiently low etching rate, for example, a silicon nitride film can be used.

Next, as shown in FIG. 1B, a first resist pattern 107 having an opening for forming a wiring groove is formed on the titanium nitride film 106 by a lithography process. Dry etching is performed on the titanium nitride film 106 using the resist pattern 107 as a mask to form a mask pattern 108 made of the titanium nitride film 106 as shown in FIG.

Next, without removing the first resist pattern 107, a second resist pattern 109 having an opening for forming a contact hole is formed on the second organic film 105 by a lithography process. By performing dry etching on the second organic film 105, FIG.
As shown in (a), a patterned second organic film 105A having an opening for forming a contact hole is formed. In this case, since the second organic film 105 and the first resist pattern 107 and the second resist pattern 109 both contain an organic component as a main component, the second organic film 1
Since the etching rate for the second organic film 105 and the etching rate for the first and second resist patterns 107 and 109 are substantially equal to each other, the first resist pattern 10
7 and the second resist pattern 109 are removed.

Incidentally, in the dry etching step for the second organic film 105, the second resist pattern 109 is formed.
May remain. The reason is that the second
This is because the resist pattern 109 is removed in a later step of forming the wiring groove 111 in the patterned second organic film 105A (see FIG. 2C).

Next, the patterned second organic film 10
Dry etching is performed on the organic-containing silicon oxide film 104 using 5A as a mask to form a patterned organic-containing silicon oxide film 104A having an opening for forming a contact hole as shown in FIG. 2B. .
This dry etching step is performed by selecting etching conditions such that the etching rate for the organic-containing silicon oxide film 104 is higher than the etching rate for the patterned second organic film 105A.
This prevents a situation in which the patterned second organic film 105A is etched.

Next, the second organic film 105A patterned using the mask pattern 108 as a mask and the first organic film 103 dried using the patterned organic-containing silicon oxide film 104A as a mask. By performing etching, as shown in FIG. 2C, a wiring groove 111 is formed in the patterned second organic film 105A, and the patterned first organic film 103A having the contact hole 110 is formed. Form.

Next, the silicon nitride film 102 is dry-etched using the patterned organic-containing silicon oxide film 104A as a mask, and as shown in FIG. Is formed, and the first metal wiring 101 is exposed to the contact hole 110.

Next, as shown in FIG. 3B, for example, 50 nm is formed on the wall surfaces of the contact hole 110 and the wiring groove 111.
After depositing an adhesion layer 112 made of titanium nitride having a thickness of m, a metal film 113 is deposited over the entire surface so as to fill the contact holes 110 and the wiring grooves 111. The composition of the metal film 113 is not particularly limited, and copper, aluminum, gold, silver, nickel, cobalt, tungsten, an alloy thereof, or the like can be used.
The deposition method of No. 3 is not particularly limited, and a plating method, a CVD method, a sputtering method, or the like can be used.

Next, as shown in FIG. 3C, the second organic film 105A is deposited on the patterned second organic film 105A.
Adhesion layer 112, metal film 113 and mask pattern 108
Is removed by, for example, a CMP method to form a second metal wiring 114 made of a metal film 113 and a contact 115 made of a metal film 113 connecting the first metal wiring 101 and the second metal wiring 114.

By performing the same steps as those described above on the second metal wiring 114, a multilayer wiring structure can be formed.

According to the first embodiment, since the organic-containing silicon oxide film 104 is a film formed by a CVD method using a reactive gas containing phenyltrimethoxysilane as a main material, silicon-containing silicon oxide film It has a structure in which a phenyl group (organic group) bonded to an atom is incorporated. Therefore, it has the same good workability as the conventional CVD oxide film, the relative dielectric constant as low as the HSQ film, and the high adhesion to the organic film, the oxide film and the metal film. .

After the mask pattern 108 made of the titanium nitride film 106 is formed, the second resist pattern 10 is removed without removing the first resist pattern 107.
9 and the first resist pattern 10 is formed by a dry etching process for the second organic film 105.
7 and the second resist pattern 109 are removed.
Since the step of removing the first resist pattern 107 and the second resist pattern 109 by ashing using oxygen plasma is not required, the situation in which the second organic film 105 is damaged when the resist pattern is removed by ashing is eliminated. Can be avoided. Therefore, it is possible to adopt a normal resist process although the second organic film 105 having a low relative dielectric constant is used as the interlayer insulating film.

Further, the wiring groove 111 is formed by performing dry etching on the patterned second organic film 105A by using the patterned organic-containing silicon oxide film 104A as an etching stopper using the mask pattern 108 as a mask. Therefore, since the depth of the wiring groove 111 matches the thickness of the second organic film 105, the depth of the wiring groove 111 can be defined in a self-aligned manner.

Hereinafter, problems in the case where the second resist pattern 109 is displaced from the first resist pattern 107 and a solution in that case will be described.

First, the problem when the second resist pattern 109 is displaced will be described with reference to FIGS.
This will be described with reference to (c), FIGS. 5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c).

As in the first embodiment, as shown in FIG. 4A, a silicon nitride film 102 having a thickness of, for example, 50 nm is formed on a first metal wiring 101 formed on a semiconductor substrate 100. After the formation, a first organic film 103 having a thickness of, for example, 1 μm and containing an organic component as a main component is deposited on the silicon nitride film 102.

Next, an organic-containing silicon oxide film 104 having a thickness of, for example, 50 nm and containing an organic component in silicon oxide is deposited on the first organic film 103, and then the organic-containing silicon oxide film 104 is deposited. A second organic film 105 having a thickness of, for example, 400 nm and containing an organic component as a main component is deposited on the film 104, and then, a nitride film having a thickness of, for example, 50 nm is formed on the second organic film 105. A titanium film 106 is deposited.

Next, as shown in FIG. 4B, after forming a first resist pattern 107 having an opening for forming a wiring groove on the titanium nitride film 106, the first resist pattern 107 is formed. 4C, dry etching is performed on the titanium nitride film 106 to form a mask pattern 1 made of the titanium nitride film 106, as shown in FIG.
08 is formed.

Next, as shown in FIG. 5A, a second resist having an opening for forming a contact hole is formed on the second organic film 105 without removing the first resist pattern 107. A pattern 109 is formed. In this case, as can be seen from a comparison between FIG. 5A and FIG. 1C, the second resist pattern 109 is misaligned with respect to the first resist pattern 107.

Next, dry etching is performed on the second organic film 105 to form a patterned second organic film 105A having an opening for forming a contact hole as shown in FIG. 5B. Form. As in the first embodiment, the second organic film 105 and the first resist pattern 1
Since both 07 and the second resist pattern 109 contain an organic component as a main component, the first resist pattern 107 and the second resist pattern 109 are removed by a dry etching process on the second organic film 105. In this case, since the second resist pattern 109 is displaced from the first resist pattern 107, the diameter of the contact hole forming opening formed in the second organic film 105A is small.

Next, the patterned second organic film 10
Using the 5A as a mask, the organic-containing silicon oxide film 104 is dry-etched to form a patterned organic-containing silicon oxide film 104A having a contact hole forming opening as shown in FIG. 5C. .

Next, dry etching is performed on the second organic film 105A patterned using the mask pattern 108 as a mask and on the first organic film 103 using the patterned organic-containing silicon oxide film 104A as a mask. 6A, a wiring groove 111 is formed in the patterned second organic film 105A, and a patterned first organic film 103A having a contact hole 110 is formed as shown in FIG. I do. Thereafter, the silicon nitride film 102 is dry-etched using the patterned organic-containing silicon oxide film 104A as a mask to form a patterned silicon nitride film 102A as shown in FIG. Then, the first metal wiring 101 is exposed in the contact hole 110.

Next, an adhesion layer 112 made of a titanium nitride layer having a thickness of, for example, 50 nm is deposited on the wall surfaces of the contact hole 110 and the wiring groove 111, and then a metal film is deposited over the entire surface. The adhesion layer 112, the metal film, and the mask pattern 108, which are deposited on the second organic film 105A, are removed by, for example, a CMP method. In this case, as shown in FIG.
Although the second metal wiring 114 made of a metal film is formed,
Since the diameter of the contact hole 110 is small, the contact hole 110 is not completely filled with the metal film.
The first metal wiring 101 and the second metal wiring 112 are not connected, and a defect occurs.

Hereinafter, a solution to the case where the second resist pattern 109 is displaced will be described with reference to FIGS.
This will be described with reference to (c) and FIGS. 8 (a) to (c).

First, FIG. 4A to FIG. 4C and FIG.
By the same process as the above-described process described based on
A second resist pattern 109 having an opening for forming a contact hole is formed. In this case as well, the second resist pattern 109 is replaced with the first resist pattern 107.
(See FIG. 5A).

Then, as shown in FIG. 7A, the first resist pattern 107 and the mask pattern 108 are dry-etched using the second resist pattern 109 as a mask to form the first resist pattern 10.
7, the region not overlapping with the second resist pattern 109 is removed, and the opening of the mask pattern 108 is enlarged to a size including the opening for forming the wiring groove and the opening for forming the contact hole. As a result, the contact hole forming opening of the second resist pattern 109 is transferred to the first resist pattern 107 and the mask pattern.

Next, dry etching is performed on the second organic film 105 to form a patterned second organic film 105A having an opening for forming a contact hole, as shown in FIG. 7B. Form. Also in this case, since the second organic film 105 and the first resist pattern 107 and the second resist pattern 109 both have an organic component as a main component, a dry etching process for the second organic film 105 is performed. The first resist pattern 107 and the second resist pattern 109 are removed.

Next, the organic-containing silicon oxide film 104 is dry-etched using the patterned organic film 105A as a mask, as shown in FIG.
A patterned organic-containing silicon oxide film 104A having a contact hole forming opening is formed.

As described above, the second resist pattern 1
09 is misaligned with respect to the first resist pattern 107, but since the contact hole forming opening of the second resist pattern 109 is transferred to the first resist pattern 107 and the mask pattern 108,
The diameter of the contact hole forming opening formed in the patterned second organic film 105A and the patterned organic-containing silicon oxide film 104A has a predetermined size.

Next, dry etching is performed on the patterned second organic film 105A and the first organic film 103 using the mask pattern 108 and the patterned organic silicon oxide film 104A as a mask. 8
As shown in (a), the patterned second organic film 1
A first organic film 10 having a contact groove 110 and a wiring groove 111 formed in the first organic film 10
Form 3A. Thereafter, the silicon nitride film 1 is formed using the patterned organic-containing silicon oxide film 104A as a mask.
02 is subjected to dry etching, and FIG.
As shown in FIG.
A is formed, and the first metal wiring 101 is exposed to the contact hole 110.

Next, an adhesion layer 112 made of a titanium nitride layer having a thickness of, for example, 50 nm is deposited on the wall surfaces of the contact hole 110 and the wiring groove 111, and then a metal film is deposited over the entire surface. The adhesion layer 112, the metal film, and the mask pattern 108, which are deposited on the second organic film 105A, are removed by, for example, a CMP method. In this case, as shown in FIG.
A second metal wiring 114 and a contact 115 made of a titanium nitride film 112 and a metal film are formed.

(Second Embodiment) Hereinafter, a method for forming a wiring structure according to a second embodiment of the present invention will be described with reference to FIG.
(A)-(c), FIGS. 10 (a)-(c) and FIG.
This will be described with reference to (a) to (c).

First, as shown in FIG. 9A, a silicon nitride film 202 having a thickness of, for example, 50 nm is formed on a first metal wiring 201 formed on a semiconductor substrate 200, and then the silicon nitride film 202 is formed. On the nitride film 202, for example, 1 μm
A first organic film 203 (first insulating film) having a thickness of m and containing an organic component as a main component is deposited. Next, the first
After depositing an organic-containing silicon oxide film 204 (second insulating film) having a thickness of, for example, 50 nm and containing an organic component in silicon oxide, on the organic film 203 of FIG.
On the organic-containing silicon oxide film 204, for example, 400
a second layer having a thickness of 10 nm and containing an organic component as a main component.
An organic film 205 (third insulating film) is deposited, and then a titanium nitride film 206 having a thickness of, for example, 50 nm is deposited on the second organic film.

The method for depositing the first and second organic films 203 and 205 is not particularly limited, and examples thereof include a plasma CVD method using a reactive gas containing perfluorodecalin as a main material. In addition, as the first and second organic films 203 and 205, a hydrocarbon film or a fluorine-containing hydrocarbon film formed by a plasma CVD method, a coating method, or a thermal CVD method can be used.

The method of depositing the organic-containing silicon oxide film 204 is not particularly limited, but includes, for example, a CVD method using a reactive gas mainly containing phenyltrimethoxysilane.

It should be noted that, instead of the titanium nitride film 206, it has a high etching selectivity with respect to the first and second organic films 203 and 205 and the organic-containing silicon oxide film 204.
That is, a thin film having a sufficiently low etching rate, for example, a silicon nitride film can be used.

Next, as shown in FIG. 9B, a first resist pattern 207 having an opening for forming a wiring groove is formed on the titanium nitride film 206 by a lithography process. Dry etching is performed on the titanium nitride film 206 using the resist pattern 207 as a mask to form a mask pattern 208 made of the titanium nitride film 206 as shown in FIG.

Next, a second resist pattern 209 having an opening for forming a contact hole is formed on the second organic film 205 by a lithography process without removing the first resist pattern 207. By performing dry etching on the second organic film 205, FIG.
As shown in FIG. 0A, a patterned second organic film 205A having an opening for forming a contact hole is formed. In this case, since the second organic film 205, the first resist pattern 207, and the second resist pattern 209 both have an organic component as a main component, the etching rate for the second organic film 205, Since the etching rates for the second resist patterns 207 and 209 are substantially equal to each other, the first resist pattern 2
07 and the second resist pattern 209 are removed.

Incidentally, the second resist pattern 209 is the first resist pattern.
When there is a possibility that the resist pattern 207 is misaligned with respect to the first resist pattern 207 and the mask pattern 208 using the second resist pattern 209 as a mask as described in the first embodiment.
Of the first resist pattern 207 is subjected to dry etching.
In addition to removing the region not overlapping with the above, the opening of the mask pattern 208 is enlarged to include the opening for forming the wiring groove and the opening for forming the contact hole.

Next, the patterned second organic film 20
Dry etching is performed on the organic-containing silicon oxide film 204 using 5A as a mask to form a patterned organic-containing silicon oxide film 204A having an opening for forming a contact hole, as shown in FIG. 10B. . Thereafter, dry etching is performed on the second organic film 205A patterned using the mask pattern 208 as a mask and on the first organic film 203 using the patterned organic-containing silicon oxide film 204A as a mask. As shown in FIG. 10C, a wiring groove 211 is formed in the patterned second organic film 205A, and a patterned first organic film 203A having a contact hole 210 is formed.

Next, the silicon nitride film 202 is dry-etched using the patterned organic-containing silicon oxide film 204A as a mask to form the patterned silicon nitride film 202A as shown in FIG. Is formed, and the first metal wiring 201 is exposed to the contact hole 210.

Next, the patterned first organic film 20
Plasma treatment using ammonia gas is performed on 3A and the patterned second organic film 205A. By doing so, as shown in FIG. 11B, the wall portion exposed in the contact hole 210 in the patterned first organic film 203A and the wiring groove 211 in the patterned second organic film 205A are formed. Adhesion layers 212 each having an amino group and an amide group are formed on the exposed wall. Thereafter, a metal film 213 is deposited over the entire surface so as to fill the contact hole 210 and the wiring groove 211. The composition of the metal film 213 is not particularly limited, and copper, aluminum, gold, silver, nickel, cobalt, tungsten, an alloy thereof, or the like can be used. The deposition method of the metal film 213 is not particularly limited, and the plating method is not limited. , CV
D method or a sputtering method can be used.

Next, as shown in FIG. 11 (c), the metal film 213 and the mask pattern 208 deposited on the patterned second organic
After removal by the MP method, a second metal wiring 214 and a contact 215 made of the metal film 213 are formed.

By performing the same steps as those described above on the second metal wiring 214, a multilayer wiring structure can be formed.

(Third Embodiment) Hereinafter, a method of forming a wiring structure according to a third embodiment of the present invention will be described with reference to FIG.
(A)-(c), FIGS. 13 (a)-(c) and FIG.
This will be described with reference to (a) to (c).

First, as shown in FIG. 12A, on the first metal wiring 301 formed on the semiconductor substrate 300, for example, 50 nm for protecting the first metal wiring 301 in an etching process performed later. After forming a silicon nitride film 302 having a thickness of
A first organic-containing silicon oxide film 303 (first insulating film) having a film thickness of, for example, 1 μm and containing an organic component in a silicon oxide is deposited on the silicon oxide film 02. Next, on the first organic-containing silicon oxide film 303, for example, 40
After depositing a low dielectric constant SOG film 304 (second insulating film) having a thickness of 0 nm and having a siloxane skeleton,
A second organic-containing silicon oxide film 305 (third insulating film) having a thickness of, for example, 50 nm and containing an organic component in silicon oxide is deposited on the low dielectric constant SOG film 304, and thereafter Then, a titanium nitride film 306 having a thickness of, for example, 50 nm is formed on the second organic-containing silicon oxide film 305.

The method of depositing the first organic-containing silicon oxide film 303 and the second organic-containing silicon oxide film 305 is not particularly limited. For example, a CVD method using a reactive gas containing phenyltrimethoxysilane as a main material is used. Is mentioned. Also, a low dielectric constant SO having a siloxane skeleton
As the G film 304, an HSQ film can be used.

It should be noted that instead of the titanium nitride film 306, the first and second organic-containing silicon oxide films 303 and 305 and the low dielectric constant SOG film 304 have high etching selectivity, that is, the etching rate is sufficiently high. A slow thin film, for example, a silicon nitride film can be used.

Next, as shown in FIG. 12B, a first resist pattern 307 having an opening for forming a wiring groove is formed on the titanium nitride film 306 by a lithography process. Dry etching is performed on the titanium nitride film 306 using the resist pattern 307 as a mask, and as shown in FIG.
6 are formed.

Next, as shown in FIG. 13A, after the first resist pattern 307 is removed, a second hole having a contact hole forming opening is formed on the second organic-containing silicon oxide film 305. The resist pattern 309 is formed. Then, using the second resist pattern 309 as a mask, the second organic-containing silicon oxide film 305, the low-permittivity SOG film 304, and the first organic-containing silicon oxide film 30
13 is sequentially subjected to dry etching to obtain FIG.
As shown in (b), a patterned second organic-containing silicon oxide film 305A, a patterned low dielectric constant S
Patterned first organic-containing silicon oxide film 303A having OG film 304A and contact hole 310
Are formed respectively.

Next, as shown in FIG. 13C, after removing the second resist pattern 309, the second organic-containing silicon oxide film 305A patterned using the mask pattern 308 as a mask is dried. An etching is performed to form an opening for forming a wiring groove in the patterned second organic-containing silicon oxide film 305A, and thereafter, a patterned second pattern having a mask pattern 308 and an opening for forming a wiring groove is formed. Organic-containing silicon oxide film 305A
Dielectric constant SOG film 30 patterned by using
4A is subjected to dry etching to form wiring trenches 311.
To form In the step of forming the wiring groove 311,
By setting the etching conditions such that the etching rate for the first organic-containing silicon oxide film 303A is sufficiently slower than the etching rate for the low-dielectric-constant SOG film 304A, the patterned first organic-containing silicon oxide film Since a sufficient selection ratio with respect to the film 303A can be secured, the depth of the wiring groove 311 can be uniquely determined by the total thickness of the second organic silicon oxide film 305 and the low dielectric constant SOG film 304.

Note that the second resist pattern 309 is
If there is a possibility of misalignment with respect to the second resist pattern 307, the second organic-containing silicon oxide film 305 is subjected to the second etching before dry-etching using the second resist pattern 309 as a mask. It is preferable to perform dry etching on the mask pattern 308 using the resist pattern 309 as a mask. That is, when the mask pattern 308 is exposed to the contact hole forming opening of the second resist pattern 309 because the second resist pattern 309 is misaligned with respect to the first resist pattern 307. Is to dry-etch the mask pattern 308 using the second resist pattern 309 as a mask to enlarge the opening of the mask pattern 308 to a size including the opening for forming the wiring groove and the opening for forming the contact hole. I do.

Next, the silicon nitride film 3 is formed using the patterned first organic-containing silicon oxide film 303A as a mask.
02 is dry-etched to obtain FIG.
As shown in FIG. 2A, a patterned silicon nitride film 302A is formed, and the first metal wiring 301 is exposed to a contact hole 310.

Next, as shown in FIG. 14B, for example, 50 mm is formed on the wall surfaces of the contact hole 310 and the wiring groove 311.
adhesion layer 312 made of a titanium nitride layer having a thickness of 10 nm
Is deposited, the contact hole 310 and the wiring groove 31 are formed.
A metal film 313 is deposited over the entire surface so as to fill 1. The composition of the metal film 313 is not particularly limited, and copper, aluminum, gold, silver, nickel, cobalt, tungsten, an alloy thereof, or the like can be used. The deposition method of the metal film 313 is not particularly limited. A CVD method, a sputtering method, or the like can be used.

Next, as shown in FIG. 14C, the adhesion layer 312, the metal film 313, and the mask pattern 308 deposited on the patterned second organic-containing silicon oxide film 305A are removed, for example. Removed by CMP method,
A second metal wiring 314 made of a metal film 313;
A contact 315 made of a metal film 313 for connecting the metal wiring 301 and the second metal wiring 314 is formed.

By performing the same steps as those described above on the second metal wiring 314, a multilayer wiring structure can be formed.

According to the third embodiment, when the first resist pattern 307 is removed by ashing using oxygen plasma, the second resist pattern 307 is formed on the low dielectric constant SOG film 304.
Of the organic-containing silicon oxide film 305 of
The low dielectric constant SOG film 304 is not exposed to oxygen plasma.

Using the second resist pattern 309 as a mask, the second organic-containing silicon oxide film 305, the low dielectric constant SOG film 304, and the first organic-containing silicon oxide film 303 were sequentially subjected to dry etching. rear,
Since the second resist pattern 309 is removed by ashing using oxygen plasma, a region of the patterned low dielectric constant SOG film 304A exposed to the contact hole forming opening is exposed to oxygen plasma and is damaged. However, the damage layer in the patterned low dielectric constant SOG film 304A is removed when the wiring groove 311 is formed in the patterned low dielectric constant SOG film 304A, so that it has no adverse effect in a subsequent process.

Therefore, as the low dielectric constant SOG film 304, a material that is deteriorated by oxygen plasma can be used. For example, when the HSQ film is exposed to oxygen plasma, the Si—H bond is oxidized, which causes an increase in the water content and an increase in the relative dielectric constant, thereby deteriorating the reliability and performance of the device. However, according to the third embodiment, since the patterned low dielectric constant SOG film 304A after the formation of the wiring groove 311 is not affected by oxygen plasma, the HSQ film is used as the interlayer insulating film. Also, it is possible to avoid deterioration of the reliability and performance of the device.

(Modification of Third Embodiment) Hereinafter, a method for forming a wiring structure according to a modification of the third embodiment of the present invention will be described with reference to FIGS. 15 (a) to 15 (c) and 16 (a). ) ~
This will be described with reference to (d) and FIGS. 17 (a) to (c).

First, as shown in FIG. 15A, on a first metal wiring 351 formed on a semiconductor substrate 350, for example, 50 nm for protecting the first metal wiring 351 in an etching step performed later. After forming a silicon nitride film 352 having a thickness of
A first silicon oxide film 353 (first insulating film) having a film thickness of, for example, 1 μm is deposited on the metal film 52. Next, after depositing an organic film 354 (a second insulating film) having a thickness of, for example, 400 nm on the first silicon oxide film 353, a film thickness of, for example, 50 nm is deposited on the organic film 354. A second silicon oxide film 355 (third insulating film) is deposited, and then a titanium nitride film 356 having a thickness of, for example, 50 nm is formed on the second silicon oxide film 355.

The method of depositing the first silicon oxide film 353 and the second silicon oxide film 355 is not particularly limited, but includes, for example, a CVD method using a reactive gas mainly containing phenyltrimethoxysilane.

The first and second silicon oxide films 353 and 355 and the organic film 3 are replaced with the titanium nitride film 356.
It is possible to use a thin film having a high etching selectivity to 54, that is, a silicon nitride film having a sufficiently low etching rate, for example, a silicon nitride film.

Next, as shown in FIG. 15B, a first resist pattern 357 having an opening for forming a wiring groove is formed on the titanium nitride film 356 by a lithography process. Dry etching is performed on the titanium nitride film 356 using the resist pattern 357 as a mask, and as shown in FIG.
6 is formed.

Next, as shown in FIG. 16A, after removing the first resist pattern 357, a second resist having an opening for forming a contact hole is formed on the second silicon oxide film 355. A pattern 359 is formed. Thereafter, using the second resist pattern 359 as a mask, the second silicon oxide film 355 and the organic film 354 are sequentially dry-etched, and as shown in FIG. Having,
A patterned second silicon oxide film 355A and a patterned organic film 354A are formed. In this case, the second resist pattern 359 is removed in the etching step for the organic film 354.

Next, as shown in FIG. 16C, dry etching is performed on the first silicon oxide film 353 using the patterned second silicon oxide film 355A and the patterned organic film 354A as masks. To form a patterned first silicon oxide film 353A having a contact hole 361. In this etching step, the patterned second silicon oxide film 3
Since the mask pattern 358 is transferred to 55A, an opening for forming a wiring groove is formed in the patterned second silicon oxide film 355A.

Next, as shown in FIG. 16 (d), a mask pattern 358 and an organic film 354A patterned using the patterned second silicon oxide film 355A having an opening for forming a wiring groove as a mask are formed. On the other hand, the wiring groove 362 is formed by performing dry etching. Wiring groove 36
In the step of forming the first silicon oxide film 3,
By setting the etching conditions such that the etching rate for 53A is sufficiently lower than the etching rate for organic film 354A, a sufficient selectivity with respect to patterned first silicon oxide film 353A can be ensured. The depth of the groove 362 can be uniquely determined by the total thickness of the second silicon oxide film 355 and the organic film 354.

Note that the second resist pattern 359 corresponds to the first resist pattern 359.
If there is a possibility that the second resist pattern 357 is misaligned, the second resist pattern 359 is used as a mask before the second silicon oxide film 355 is dry-etched. 35
It is preferable to perform dry etching on the mask pattern 358 using the mask 9 as a mask. That is, the second resist pattern 359 corresponds to the first resist pattern 35.
7, the mask pattern 3
In the case where 58 is exposed in the contact hole forming opening of second resist pattern 359, mask pattern 358 is formed using second resist pattern 359 as a mask.
By performing dry etching, the opening of the mask pattern 358 is enlarged to include the opening for forming the wiring groove and the opening for forming the contact hole.

Next, the silicon nitride film 352 is dry-etched using the patterned first silicon oxide film 353A as a mask, and as shown in FIG. 352A is formed, and the first metal wiring 351 is exposed to the contact hole 361.

Next, as shown in FIG. 17B, for example, 50 mm is formed on the wall surfaces of the contact hole 361 and the wiring groove 362.
adhesion layer 363 made of a titanium nitride layer having a thickness of 10 nm
Is deposited, the contact hole 361 and the wiring groove 36 are formed.
A metal film 364 is deposited over the entire surface so as to fill 2. The composition of the metal film 364 is not particularly limited, and copper, aluminum, gold, silver, nickel, cobalt, tungsten, an alloy thereof, or the like can be used. The deposition method of the metal film 364 is not particularly limited, and the plating method is not limited. , CVD
Method or sputtering method can be used.

Next, as shown in FIG. 17C, the adhesion layer 363, the metal film 364, and the mask pattern 358 deposited on the patterned second silicon oxide film 355A are formed by, for example, a CMP method. Metal film 3
64, and a metal film 3 connecting the first metal wiring 351 and the second metal wiring 365.
A contact 366 of 64 is formed.

It is to be noted that a multilayer interconnection structure can be formed on second metal interconnection 365 by performing the same steps as those described above.

According to the modification of the third embodiment, when the first resist pattern 357 is removed by ashing using oxygen plasma, the second silicon oxide film 355 exists on the organic film 354. The organic film 35
4 is not exposed to oxygen plasma.

The second silicon oxide film 355 and the organic film 3 are formed by using the second resist pattern 359 as a mask.
Since the second resist pattern 359 is removed when the dry etching is performed on the layer 54, it is not necessary to remove the second resist pattern 359 by ashing using oxygen plasma. No exposure.

(Fourth Embodiment) Hereinafter, a method for forming a wiring structure according to a fourth embodiment of the present invention will be described with reference to FIG.
(A)-(c), FIGS. 19 (a)-(c) and FIG.
This will be described with reference to (a) to (c).

First, as shown in FIG. 18A, on the first metal wiring 401 formed on the semiconductor substrate 400, for example, 50 nm for protecting the first metal wiring 401 in an etching process performed later. After forming a silicon nitride film 402 having a thickness of
For example, a first low dielectric constant SOG film 403 having a thickness of 1 μm and having a siloxane skeleton (first
Is deposited. Next, an organic silicon oxide film 404 (second insulating film) having a thickness of, for example, 50 nm and containing an organic component in silicon oxide is deposited on the first low dielectric constant SOG film 403. Thereafter, a second low dielectric constant SOG film 405 (third insulating film) having a thickness of, for example, 400 nm and having a siloxane skeleton is deposited on the organic-containing silicon oxide film 404.
On the second low dielectric constant SOG film 405, for example, 50 nm
A titanium nitride film 406 having a film thickness of is deposited.

The first and second low dielectric constant SOG films 403,
As the 405, for example, an HSQ film can be used.
The method for depositing the organic-containing silicon oxide film 404 is not particularly limited, and for example, a CVD method using a reactive gas containing phenyltrimethoxysilane as a main material can be used. Thus, an organic-containing silicon oxide film 404 having a structure in which a phenyl group bonded to a silicon atom is incorporated in silicon oxide is obtained.

It should be noted that, instead of the titanium nitride film 406, the first and second low dielectric constant SOG films 403 and 405 and the organic-containing silicon oxide film 404 have high etching selectivity, that is, the etching rate is sufficiently high. A slow thin film, for example, a silicon nitride film can be used.

Next, as shown in FIG. 18B, a first resist pattern 407 having an opening for forming a wiring groove is formed on the titanium nitride film 406 by a lithography process. Dry etching is performed on the titanium nitride film 406 using the resist pattern 407 as a mask, and as shown in FIG.
6 is formed.

Next, a second resist pattern 409 having a contact hole forming opening is formed on the second low dielectric constant SOG film 405 by a lithography process without removing the first resist pattern 407. After that, using the second resist pattern 409 as a mask,
Dry etching is sequentially performed on the second low dielectric constant SOG film 405 and the organic-containing silicon oxide film 404,
As shown in FIG. 19A, a patterned second low dielectric constant SOG film 405A and a patterned organic-containing silicon oxide film 404A are formed.

Next, the first and second resist patterns 4
When the layers 07 and 409 are removed by ashing using oxygen plasma, contact holes are formed in the patterned second low dielectric constant SOG film 405A and the first low dielectric constant SOG film 403 as shown in FIG. The damage layer 410 is formed in a region exposed to the opening for use.

Next, the second low dielectric constant SOG film 405A patterned by using the mask pattern 408 as a mask and the first low dielectric constant SOG film by using the patterned organic-containing silicon oxide film 404A as a mask. Membrane 403
19 is subjected to dry etching, and FIG.
As shown in (c), a wiring groove 412 is formed in the patterned second low dielectric constant SOG film 405A, and a patterned first low dielectric constant SOG film 403A having a contact hole 411 is formed. I do. By this dry etching step, the patterned second low dielectric constant S
The damaged layer 410 of the OG film 405A and the first low dielectric constant SOG film 403 is removed.

Next, the silicon nitride film 402 is dry-etched using the patterned organic-containing silicon oxide film 404A as a mask, and as shown in FIG. Is formed, and the first metal wiring 401 is exposed in the contact hole 411.

Next, as shown in FIG. 20B, for example, 50 μm are formed on the wall surfaces of the contact hole 411 and the wiring groove 412.
adhesion layer 413 made of a titanium nitride layer having a thickness of 10 nm
Is deposited, the contact hole 411 and the wiring groove 41 are formed.
A metal film 414 is deposited over the entire surface so as to fill 2. The composition of the metal film 414 is not particularly limited, and copper, aluminum, gold, silver, nickel, cobalt, tungsten, an alloy thereof, or the like can be used. , CVD
Method or sputtering method can be used.

Next, as shown in FIG. 20C, the adhesion layer 413, the metal film 414, and the mask pattern 408 deposited on the patterned second low dielectric constant SOG film 405A are formed, for example. After removal by the CMP method, a second metal wiring 415 made of the metal film 414 and a contact 416 made of the metal film 414 connecting the first metal wiring 401 and the second metal wiring 415 are formed.

Note that a multilayer wiring structure can be formed on the second metal wiring 114 by performing the same steps as those described above.

According to the fourth embodiment, when the first and second resist patterns 407 and 409 are removed by ashing using oxygen plasma, the patterned second low dielectric constant SOG film 405A and the first Low dielectric constant SO
Although a damaged layer 410 is formed on the G film 403,
The damaged layer 410 is removed when forming the contact hole 411 and the wiring groove 412.

Therefore, as the first and second low dielectric constant SOG films 403 and 405, it is possible to use a material which is deteriorated by oxygen plasma. For example, when an HSQ film is exposed to oxygen plasma, Si—H bonds are oxidized, so that an increase in water content and an increase in relative dielectric constant occur, thereby deteriorating the reliability and performance of the device. However, according to the fourth embodiment, the contact hole 4
The patterned first low-permittivity SOG film 403A after the formation of the wiring 11 and the patterned second low-permittivity SOG film 405A after the formation of the wiring groove 412 are affected by the oxygen plasma. Since no HSQ film is used as the interlayer insulating film, deterioration of the reliability and performance of the device can be avoided.

(Fifth Embodiment) Hereinafter, a method for forming a wiring structure according to a fifth embodiment of the present invention will be described with reference to FIGS.
(A)-(c), FIGS. 22 (a)-(c), FIG. 23 (a)
This will be described with reference to FIGS.

First, as shown in FIG. 21A, a first metal wiring 501 formed on a semiconductor substrate 500 is formed on a first metal wiring 501 in a later-described etching step to protect the first metal wiring 501 by, for example, 50 nm. After forming a silicon nitride film 502 having a thickness of
A first organic film 503 (first insulating film) having a thickness of, for example, 400 nm and containing an organic component as a main component is deposited on the substrate 02. Next, a first silicon oxide film 50 having a thickness of, for example, 100 nm is formed on the first organic film 503.
After depositing the second organic film 505 (third insulating film), the second silicon film 505 (third organic film) having a thickness of, for example, 300 nm and having an organic component as a main component is formed on the first silicon oxide film 504.
Is deposited. Next, a second silicon oxide film 506 (fourth insulating film) having a thickness of, for example, 200 nm is deposited on the second organic film 505, and then, for example, on the second silicon oxide film 506, A titanium nitride film 507 (thin film) having a thickness of 50 nm is deposited.

The method for depositing the first and second organic films 503 and 505 is not particularly limited, but for example, a plasma CVD method using a reactive gas containing perfluorodecalin as a main material is exemplified. As the first and second organic films 503 and 505, a hydrocarbon film or a fluorine-containing hydrocarbon film formed by a plasma CVD method, a coating method, or a thermal CVD method can be used. , Polytetrafluoroethylene, oxygen-containing polytetrafluoroethylene, fluorinated polyimide, polyallyl ether, or the like can be used.

First and second silicon oxide films 504, 5
No particular limitation is imposed on the method of depositing 06, for example, a plasma CVD method.

It should be noted that instead of the titanium nitride film 507, the first and second organic films 503 and 505 and the first and second silicon oxide films 504 and 506 have a high etching selectivity, that is, an etching rate However, a sufficiently thin film, for example, a silicon nitride film can be used.

Next, as shown in FIG. 21B, a first resist pattern 508 having an opening for forming a wiring groove is formed on the titanium nitride film 507 by a lithography process. Using the resist pattern 508 as a mask, dry etching is performed on the titanium nitride film 507 to form a mask pattern 509 made of the titanium nitride film 507 having an opening for forming a wiring groove, as shown in FIG.

Next, as shown in FIG. 22A, the first resist pattern 508 is removed by, for example, oxygen plasma. In this case, since the second silicon oxide film 506 exists on the second organic film 505 containing an organic component as a main component, the first resist pattern 508 is removed by ashing using oxygen plasma. However, deterioration of the film quality of the second organic film 505 is not caused.

Next, as shown in FIG. 22B, a second resist pattern 510 having an opening for forming a contact hole is formed on the mask pattern 509 by a lithography process. Pattern 51
Then, dry etching is performed on the second silicon oxide film 506 using the mask pattern 509 and the mask pattern 509 as a mask to form a patterned second silicon oxide film having an opening for forming a contact hole as shown in FIG. An oxide film 506A is formed.

Next, the second organic film 505 is dry-etched using the patterned second silicon oxide film 506A as a mask, and as shown in FIG. A patterned second organic film 505A having a portion is formed. in this case,
Since both the second organic film 505 and the second resist pattern 510 contain an organic component as a main component, the etching rate for the second organic film 505 is substantially equal to the etching rate for the second resist pattern 510. In a dry etching process for the second organic film 505, the second resist pattern 510 is removed. Patterned second silicon oxide film 506A
Functions as an etching stopper in the dry etching process for the second resist pattern 510.

In the dry etching step for the second organic film 505, the second resist pattern 510 is formed.
May remain. The reason is that the second
The resist pattern 510 is formed in a dry etching step (FIG. 23) for the first organic film 503 to be performed later.
(See (c)).

Next, dry etching is performed on the patterned second silicon oxide film 506A using the mask pattern 509 as a mask, and the first silicon oxide film 506A is patterned using the patterned second organic film 505A as a mask. The film 504 is dry-etched to form a patterned second silicon oxide film 506B having an opening for forming a wiring groove, as shown in FIG. A patterned first silicon oxide film 504A having a portion is formed.

Next, the second organic film 505A patterned by using the mask pattern 509 as a mask is dry-etched, and the first organic film 504A is patterned by using the first silicon oxide film 504A as a mask. 5
03 is dry-etched to obtain FIG.
As shown in (c), a patterned second organic film 505B having a wiring groove 511 and a patterned first organic film 503A having a contact hole 512 are formed.

Next, using the patterned first silicon oxide film 504A as a mask, dry etching is performed on the silicon nitride film 502 to form a patterned silicon nitride film 502A (see FIG. 23D). Is formed, and the first metal wiring 501 is formed in the contact hole 5.
Exposure to 12 Next, although not shown, the first
Similarly to the embodiment, after an adhesion layer made of titanium nitride having a thickness of, for example, 50 nm is deposited on the wall surfaces of the contact hole 512 and the wiring groove 511, the contact hole 51 is formed.
A metal film is deposited over the entire surface so as to fill the wiring groove 511 and the wiring groove 511. The composition of the metal film is not particularly limited, and copper, aluminum, gold, silver, nickel, cobalt, tungsten, an alloy thereof, or the like can be used. The deposition method of the metal film is not particularly limited, and a plating method, a CVD method, or the like. Method or sputtering method can be used. Next, the adhesion layer, the metal film, and the mask pattern 509 deposited on the patterned second silicon oxide film 506B are removed by, for example, a CMP method, and as shown in FIG. Second metal wiring 513 and first metal wiring 501
514 connecting the second metal wiring 513 to the second metal wiring 513
To form

Note that a multilayer wiring structure can be formed on the second metal wiring 513 by performing the same steps as those described above.

According to the fifth embodiment, when the first resist pattern 508 is removed by, for example, oxygen plasma, a second silicon oxide film is formed on the second organic film 505 which is easily damaged by oxygen plasma. Since the film 506 exists, the film quality of the second organic film 505 does not deteriorate.

In the dry etching step for the second organic film 505, the first silicon oxide film 50
Since 4 functions as an etching stopper, it is possible to prevent the first organic film 503 from deteriorating in film quality.

(Modification of Fifth Embodiment) Hereinafter, a method of forming a wiring structure according to a modification of the fifth embodiment of the present invention will be described with reference to FIGS. 24 (a) to 24 (c) and 25 (a). ) ~
(C), FIGS. 26 (a) to (d), FIG. 27 (a),
(B), FIG. 28 (a), (b) and FIG. 29 (a),
This will be described with reference to FIG.

First, as shown in FIG. 24A, a first metal wiring 551 formed on a semiconductor substrate 550 is formed on a first metal wiring 551 by, for example, 50 nm for protecting the first metal wiring 551 in an etching step performed later. After forming a silicon nitride film 552 having a thickness of
A first organic film 553 (first insulating film) having a film thickness of, for example, 400 nm and containing an organic component as a main component is deposited on the second insulating film 52. Next, a first silicon oxide film 55 having a thickness of, for example, 100 nm is formed on the first organic film 553.
After depositing the second organic film 555 (third insulating film), a second organic film 555 (third organic film) having a thickness of, for example, 300 nm and containing an organic component as a main component is formed on the first silicon oxide film
Is deposited. Next, a second silicon oxide film 556 (fourth insulating film) having a thickness of, for example, 200 nm is deposited on the second organic film 555, and then, for example, on the second silicon oxide film 556, A titanium nitride film 557 having a thickness of 50 nm is deposited.

The method for depositing the first and second organic films 553 and 555 and the first and second silicon oxide films 554 and 556 is the same as in the fifth embodiment.
First and second organic films 5 instead of titanium nitride film 557
53, 555 and first and second silicon oxide films 55
A thin film having high etching selectivity to 4,556 can be used.

Next, as shown in FIG. 24B, a first layer having an opening for forming a wiring groove is formed on the titanium nitride film 557.
After the resist pattern 558 is formed, the titanium nitride film 557 is formed using the first resist pattern 558 as a mask.
24C, a mask pattern 559 made of a titanium nitride film 557 having an opening for forming a wiring groove is formed as shown in FIG.

Next, as shown in FIGS. 25A and 27A, after removing the first resist pattern 558, as shown in FIG. 25B, a mask pattern 559 is formed.
A second resist pattern 560 having a contact hole forming opening is formed thereon. In this case, as a feature of the modification of the fifth embodiment, the size of the contact hole forming opening of the second resist pattern 560 is perpendicular to the wiring groove for forming the second metal wiring. In a suitable direction and in a parallel direction, the contact hole is larger than the design dimension of the contact hole. The reason for this will be described later.

Next, the second silicon oxide film 556 is dry-etched using the second resist pattern 560 and the mask pattern 559 as a mask.
As shown in FIG. 5C and FIG. 27B, a patterned second silicon oxide film 556A having an opening for forming a contact hole is formed.

As described above, the size of the contact hole forming opening of the second resist pattern 560 is larger than the design dimension in the direction perpendicular and parallel to the wiring groove for forming the second metal wiring. Has also been expanded,
Even if the contact hole forming opening of the resist pattern 560 is displaced from the wiring forming opening of the mask pattern 559, the contact hole forming opening formed in the patterned second silicon oxide film 556A is formed. The opening is formed in an overlapping region of the contact hole forming opening of the second resist pattern 560 and the wiring forming opening of the mask pattern 559, so that the contact of the patterned second silicon oxide film 556A is formed. The hole forming opening is formed in a region of the wiring forming opening of the mask pattern 559 in a self-aligned manner.

Since the size of the contact hole forming opening of the second resist pattern 560 is enlarged in the direction parallel to the wiring groove for forming the second metal wiring, the size is to be formed later. The contact area between the contact 564 to be formed and the second metal wiring 563 (see FIG. 26D) is enlarged, so that the contact 564 becomes
The first and second metal wires 563 can be reliably connected.

Next, dry etching is performed on the second organic film 555 using the patterned second silicon oxide film 556A as a mask, and FIG. 26 (a) and FIG.
As shown in FIG. 8A, a patterned second organic film 555A having an opening for forming a contact hole is formed. In this case, since both the second organic film 555 and the second resist pattern 560 contain an organic component as a main component, the etching rate for the second organic film 555 and
Since the etching rate for the second resist pattern 560 is substantially the same, the second resist pattern 5
60 is removed. Incidentally, in the etching step for the second organic film 555, the second resist pattern 560 is formed.
May remain. The reason is that the second
This is because the resist pattern 560 is removed in a later-described etching step for the first organic film 553 (see FIG. 26C).

Next, the second silicon oxide film 556A patterned by using the mask pattern 559 as a mask is dry-etched, and the first silicon oxide film 555A is masked by using the second organic film 555A as a mask. The film 554 is subjected to dry etching to form a patterned second silicon oxide film 556B having a wiring groove and a contact hole as shown in FIGS. 26 (b) and 28 (b). A patterned first silicon oxide film 554A having an opening for use is formed.

Next, dry etching is performed on the patterned second organic film 555A using the mask pattern 559 and the patterned second silicon oxide film 556B as a mask, and the patterned first organic film 555A is formed. First organic film 55 using silicon oxide film 554A as a mask
3 is subjected to dry etching, and FIG.
As shown in FIG. 29A, a patterned second organic film 555B having a wiring groove 561 is formed, and a patterned first organic film 553A having a contact hole 562 is formed.

Next, using the patterned first silicon oxide film 554A as a mask, the silicon nitride film 552 is dry-etched to form a patterned silicon nitride film 552A having a contact hole (FIG. 2).
6 (d)) and the first metal wiring 5
51 is exposed to the contact hole 562. Next, although not shown, for example, 50 n is formed on the wall surface of the contact hole 562 and the wiring groove 561 as in the first embodiment.
After depositing an adhesion layer made of titanium nitride having a thickness of m, a metal film is deposited over the entire surface so as to fill the contact hole 562 and the wiring groove 561, and then a patterned second silicon oxide film is formed. The adhesion layer, the metal film, and the mask pattern 559 deposited on 556B are removed by, for example, the CMP method, and FIG. 26 (d) and FIG.
As shown in (b), the second metal wiring 563 and the first
A contact 564 that connects the metal wiring 551 of the second metal wiring 563 to the second metal wiring 563 is formed.

Note that a multilayer wiring structure can be formed on the second metal wiring 563 by performing the same steps as those described above.

According to the modification of the fifth embodiment, the size of the contact hole forming opening of the second resist pattern 560 is perpendicular and parallel to the wiring groove for forming the second metal wiring. In this case, even if the contact hole forming opening of the second resist pattern 560 is displaced from the wiring forming opening of the mask pattern 559, the patterning is performed. An opening for forming a contact hole formed in second silicon oxide film 556A is formed with second resist pattern 56.
0 contact hole forming opening and mask pattern 5
Since the contact hole forming opening of the patterned second silicon oxide film 556A is formed in a region overlapping with the wiring forming opening 59, the wiring forming opening of the mask pattern 559 is self-aligned. Area. Therefore, the contact 564 and the second metal wiring 563
Can be reliably ensured.

Since the size of the contact hole forming opening of second resist pattern 560 is enlarged in the direction parallel to the wiring groove for forming the second metal wiring, contact 564 is formed. And the second metal wiring 563
Since the contact area with the contact 564 is increased, the contact 564 becomes the first contact.
Metal wiring 551 and the second metal wiring 563 can be reliably connected.

FIG. 36 shows the relationship between the wiring forming opening of the mask pattern 559 and the contact hole forming opening of the second resist pattern 560 according to a modification of the fifth embodiment. As can be seen from the figure, the contact hole forming opening of the second resist pattern 560 is larger than the design dimension.

FIG. 37A shows a positional relationship between a mask pattern and a second resist pattern and a positional relationship between a first metal wiring and a contact in a modification of the fifth embodiment. The positional relationship between the wiring forming opening of the mask pattern 559 and the contact hole forming opening of the second resist pattern 560 is shown. 1 shows a positional relationship between one metal wiring 551 and a contact 564. FIG. 37B shows the positional relationship between the mask pattern and the second resist pattern and the first and second resist patterns according to the fifth embodiment.
The upper part of the drawing shows the positional relationship between the wiring forming opening of the mask pattern 509 and the contact hole forming opening of the second resist pattern 510. Shows a cross-sectional state along the line BB, and the lower part of the drawing shows the positional relationship between the first metal wiring 501 and the contact 514.

When the size of the contact hole forming opening of the second resist pattern 510 is set to the designed size as in the fifth embodiment, as can be seen from FIG. When the contact hole forming opening of the pattern 510 is displaced from the wiring forming opening of the mask pattern 509, the contact 5
The area of the connection (region shown by oblique lines) between the first metal wiring 501 and the first metal wiring 501 is greatly reduced. On the other hand, when the size of the contact hole forming opening of the second resist pattern 560 is made larger than the design size as in the modification of the fifth embodiment, FIG. As can be seen, even if the contact hole forming opening of the second resist pattern 560 is misaligned with respect to the wiring forming opening of the mask pattern 559, the connection portion (the contact portion between the contact 564 and the first metal wiring 551 ( The area of the hatched area) does not decrease much.

(Sixth Embodiment) Hereinafter, a method of forming a wiring structure according to a sixth embodiment of the present invention will be described with reference to FIG.
(A)-(c), FIG. 31 (a)-(c), FIG. 32 (a)
This will be described with reference to FIGS.

First, as shown in FIG. 30A, a first metal wiring 601 formed on a semiconductor substrate 600 is formed on a first metal wiring 601 in a later-described etching step to protect the first metal wiring 601 by, for example, 50 nm. After forming a silicon nitride film 602 having a thickness of
A first organic film 603 (first insulating film) having a thickness of, for example, 400 nm and containing an organic component as a main component is deposited on the substrate 02. Next, after depositing a silicon oxide film 604 (second insulating film) having a thickness of, for example, 100 nm on the first organic film 603, a film thickness of, for example, 300 nm is deposited on the silicon oxide film 604. A second organic film 605 (third insulating film) having an organic component as a main component is deposited. Next, on the second organic film 605, for example, 50
A titanium nitride film 606 (thin film) having a thickness of nm is deposited.

The method for depositing the first and second organic films 603 and 605 is not particularly limited, but for example, a plasma CVD method using a reactive gas containing perfluorodecalin as a main raw material can be mentioned. As the first and second organic films 603 and 605, a hydrocarbon film or a fluorine-containing hydrocarbon film formed by a plasma CVD method, a coating method, or a thermal CVD method can be used. , Polytetrafluoroethylene, oxygen-containing polytetrafluoroethylene, fluorinated polyimide, polyallyl ether, or the like can be used.

The method for depositing the silicon oxide film 604 is not particularly limited, either. For example, a plasma CVD method can be used.

The first and second organic films 603 and 605 and the silicon oxide film 6 are replaced with the titanium nitride film 606.
It is possible to use a thin film having a high etching selectivity with respect to 04, that is, a thin film having a sufficiently low etching rate, for example, a silicon nitride film.

Next, as shown in FIG. 30B, a first resist pattern 607 having an opening for forming a wiring groove is formed on the titanium nitride film 606 by a lithography process. Dry etching is performed on the titanium nitride film 606 using the resist pattern 607 as a mask to form a mask pattern 608 made of the titanium nitride film 606 having an opening for forming a wiring groove, as shown in FIG.

Next, as shown in FIG. 31A, the first resist pattern 607 is removed using, for example, an organic stripper. In this case, the second organic film 605 is not exposed to oxygen plasma, so that the quality of the second organic film 605 does not deteriorate.

Next, as shown in FIG. 31B, a second resist pattern 609 having an opening for forming a contact hole is formed on the mask pattern 608 by a lithography process. Pattern 60
The second organic film 605 is dry-etched using the mask 9 and the mask pattern 608 as a mask.
As shown in (c), a patterned second organic film 605A having an opening for forming a contact hole is formed. In this case, since both the second organic film 605 and the second resist pattern 609 have an organic component as a main component, an etching rate for the second organic film 605 and
Since the etching rate of the second resist pattern 609 is substantially equal to that of the second resist pattern 609, the second resist pattern 6
09 is removed.

In the dry etching step for the second organic film 605, the second resist pattern 609 is formed.
May remain. The reason is that the second
The resist pattern 609 is formed by a dry etching step (FIG. 32) for the first organic film 603 to be performed later.
(See (b)).

Next, the patterned second organic film 60
Dry etching is performed on the silicon oxide film 604 using the mask 5A as a mask, as shown in FIG.
A patterned silicon oxide film 604A having an opening for forming a contact hole is formed.

Next, the second organic film 605A patterned by using the mask pattern 608 as a mask is dry-etched, and the first organic film 603 is etched by using the patterned silicon oxide film 604A as a mask. As shown in FIG. 32 (b), dry etching is performed to form a patterned second layer having a wiring groove 610.
And a patterned first organic film 603A having a contact hole 611.
To form

Next, dry etching is performed on the patterned silicon oxide film 604A using the mask pattern 608 as a mask, and the first patterned silicon oxide film 604A is formed.
Silicon film 602 using organic film 603A as a mask.
Is etched to form a patterned silicon oxide film 604B having a wiring groove and a patterned silicon nitride film 60 having a contact hole.
2A (see FIG. 32C) is formed, and the first metal wiring 601 is exposed to the contact hole 611. Next, although not shown, as in the first embodiment, an adhesion layer made of titanium nitride having a thickness of, for example, 50 nm is deposited on the wall surfaces of the contact hole 611 and the wiring groove 610, and then the contact hole 611 And wiring groove 6
A metal film is deposited over the entire surface so as to fill 10. The composition of the metal film is not particularly limited, and copper, aluminum, gold,
Silver, nickel, cobalt, tungsten, an alloy thereof, or the like can be used, and a method for depositing a metal film is not particularly limited, and a plating method, a CVD method, a sputtering method, or the like can be used. Next, the adhesion layer, the metal film, and the mask pattern 608 deposited on the patterned second organic film 605B are removed by, for example, a CMP method, and as shown in FIG. 2 metal wiring 61
2, the first metal wiring 601 and the second metal wiring 612
Contact 613 is formed to connect to the contact.

By performing the same steps as those described above on the second metal wiring 612, a multilayer wiring structure can be formed.

According to the sixth embodiment, dry etching is performed using the mask pattern 608 having an opening for forming a wiring groove as a mask to form a patterned second organic film 605B having a wiring groove 610, and Then, dry etching is performed using the patterned silicon oxide film 604A as a mask to form a contact hole 611.
In order to form the patterned first organic film 603A having the above, that is, the wiring groove 610 and the contact hole 611 can be formed by the same etching step, the dual damascene structure can be realized while suppressing an increase in the number of steps. Can be formed.

According to the sixth embodiment, since the first resist pattern 607 is removed using, for example, an organic stripper, the second organic film 605 does not deteriorate in film quality.

In the dry etching step for the second organic film 605, since the silicon oxide film 604 functions as an etching stopper, it is possible to prevent the first organic film 603 from being deteriorated in film quality.

(Modification of Sixth Embodiment) Hereinafter, a method of forming a wiring structure according to a modification of the sixth embodiment of the present invention will be described with reference to FIGS. 33 (a) to 33 (c) and 34 (a). ) ~
This will be described with reference to FIG. 35 (c) and FIGS.

First, as shown in FIG. 33A, a first metal wiring 651 formed on a semiconductor substrate 650 is formed on a first metal wiring 651 in a later-described etching step to protect the first metal wiring 651 by, for example, 50 nm. After forming a silicon nitride film 652 having a thickness of
A first organic film 653 (first insulating film) having a thickness of, for example, 400 nm and containing an organic component as a main component is deposited on the top surface 52. Next, after depositing a silicon oxide film 654 (second insulating film) having a thickness of, for example, 100 nm on the first organic film 653, a film thickness of, for example, 300 nm is deposited on the silicon oxide film 654. A second organic film 655 (third insulating film) having an organic component as a main component is deposited. Next, on the second organic film 655, for example, 50
A titanium nitride film 656 (thin film) having a thickness of nm is deposited.

The method for depositing the first and second organic films 653 and 655 is not particularly limited, but for example, a plasma CVD method using a reactive gas containing perfluorodecalin as a main raw material can be mentioned. In addition, as the first and second organic films 653 and 655, a hydrocarbon film or a fluorine-containing hydrocarbon film formed by a plasma CVD method, a coating method, or a thermal CVD method can be used. , Polytetrafluoroethylene, oxygen-containing polytetrafluoroethylene, fluorinated polyimide, polyallyl ether, or the like can be used.

The method of depositing the silicon oxide film 654 is not particularly limited, but includes, for example, a plasma CVD method.

The first and second organic films 653 and 655 and the silicon oxide film 6 are replaced with the titanium nitride film 656.
It is possible to use a thin film having a high etching selectivity to 54, that is, a silicon nitride film having a sufficiently low etching rate, for example, a silicon nitride film.

Next, as shown in FIG. 33B, a first resist pattern 657 having an opening for forming a wiring groove is formed on the titanium nitride film 656 by a lithography process. Dry etching is performed on the titanium nitride film 656 using the resist pattern 657 as a mask to form a mask pattern 658 made of the titanium nitride film 656 having an opening for forming a wiring groove, as shown in FIG.

Next, as shown in FIG. 34A, the first resist pattern 657 is removed using, for example, an organic stripper. In this case, since the second organic film 655 is not exposed to oxygen plasma, the quality of the second organic film 655 does not deteriorate.

Next, as shown in FIG. 34B, a second resist pattern 659 having an opening for forming a contact hole is formed on the mask pattern 658 by a lithography process. In this case, as a feature of the modification of the sixth embodiment, the size of the contact hole forming opening of the second resist pattern 659 is perpendicular to the wiring groove for forming the second metal wiring. In a suitable direction and in a parallel direction, the contact hole is larger than the design dimension of the contact hole. The reason for this will be described later.

Next, the second organic film 65 is formed using the second resist pattern 659 and the mask pattern 658 as a mask.
5 is dry-etched to obtain FIG.
As shown in FIG. 7, a patterned second organic film 655A having a contact hole forming opening is formed. In this case, since both the second organic film 655 and the second resist pattern 659 mainly contain an organic component,
Since the etching rate for the organic film 655 is substantially equal to the etching rate for the second resist pattern 659, the second resist pattern 659 is removed in the dry etching step for the second organic film 655. In the dry etching step for the second organic film 655, the second resist pattern 659 may remain. The reason is that the remaining second resist pattern 659 is subjected to a dry etching step for the first organic film 653 to be performed later (FIG. 35B).
).

Next, the patterned second organic film 65
Dry etching is performed on the silicon oxide film 654 using the mask 5A as a mask, as shown in FIG.
A patterned silicon oxide film 654A having an opening for forming a contact hole is formed.

Next, the second organic film 655A patterned using the mask pattern 658 as a mask is dry-etched, and the first organic film 653 is patterned using the patterned silicon oxide film 654A as a mask. Dry etching is performed, and as shown in FIG. 35 (b), a patterned second layer having a wiring groove 660 is formed.
Organic film 655B and patterned first organic film 653A having contact hole 661
To form

Next, the patterned silicon oxide film 654A is dry-etched using the mask pattern 658 as a mask, and the patterned first silicon oxide film 654A is etched.
Silicon nitride film 652 using organic film 653A as a mask.
Is subjected to dry etching to form a patterned silicon oxide film 654B having wiring grooves (FIG. 35).
(FIG. 35C) and a patterned silicon nitride film 652A having a contact hole (see FIG. 35C) is formed, and the first metal wiring 651 is exposed to the contact hole 661. Next, although not shown, as in the first embodiment, contact holes 66 are formed.
After an adhesion layer made of titanium nitride having a thickness of, for example, 50 nm is deposited on the wall surfaces of the first and wiring grooves 660, a metal film is deposited over the entire surface so as to fill the contact holes 661 and the wiring grooves 660. The composition of the metal film is not particularly limited, and copper, aluminum, gold, silver, nickel, cobalt,
Tungsten or an alloy thereof can be used, and a method for depositing a metal film is not particularly limited, and a plating method, a CVD method, a sputtering method, or the like can be used.
Next, an adhesion layer, a metal film, and a mask pattern 65 deposited on the patterned second organic film 655B.
8 is removed by, for example, a CMP method to form a second metal wiring 662 and a contact 663 for connecting the first metal wiring 651 and the second metal wiring 662 as shown in FIG. .

Note that a multilayer wiring structure can be formed on the second metal wiring 662 by performing the same steps as those described above.

According to the modification of the sixth embodiment, the size of the contact hole forming opening of the second resist pattern 659 is perpendicular and parallel to the wiring groove for forming the second metal wiring. In this case, even if the contact hole forming opening of the second resist pattern 659 is displaced from the wiring forming opening of the mask pattern 658, the patterning is performed. The contact hole forming opening formed in the second organic film 655A is formed in an overlapping region of the contact hole forming opening of the second resist pattern 659 and the wiring forming opening of the mask pattern 658. The opening for forming a contact hole of the patterned second organic film 655A is formed in a self-aligned manner with the opening for forming a wiring of the mask pattern 658. It is formed in the region. Therefore, the connection between the contact 663 and the second metal wiring 662 can be reliably ensured.

Since the size of the contact hole forming opening of the second resist pattern 659 is enlarged in the direction parallel to the wiring groove for forming the second metal wiring, the contact 663 is formed. And the second metal wiring 662
The contact 663 is connected to the first
Metal wiring 651 and second metal wiring 662 can be reliably connected.

[0182]

According to the method for forming a wiring structure according to the present invention, when dry etching is performed on the third insulating film, the first insulating film is not damaged. Since an insulating film which is damaged by dry etching but has a low relative dielectric constant can be used as the insulating film, an interlayer insulating film having a low relative dielectric constant can be formed while employing a normal resist process.

Further, since the wiring groove and the contact hole can be formed by the same etching step, a dual damascene structure can be formed while suppressing an increase in the number of steps.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating a method for forming a wiring structure according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating a method for forming a wiring structure according to the first embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views illustrating a method for forming a wiring structure according to the first embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views illustrating a problem when a second resist pattern is displaced in the method for forming a wiring structure according to the first embodiment of the present invention; It is.

FIGS. 5A to 5C are cross-sectional views illustrating a problem when the second resist pattern is displaced in the method for forming a wiring structure according to the first embodiment of the present invention; It is.

FIGS. 6A to 6C are cross-sectional views illustrating a problem when the second resist pattern is displaced in the method for forming a wiring structure according to the first embodiment of the present invention; It is.

FIGS. 7A to 7C are cross-sectional views illustrating a solution when a second resist pattern is displaced in the method for forming a wiring structure according to the first embodiment of the present invention; It is.

FIGS. 8A to 8C are cross-sectional views illustrating a solution in a case where a second resist pattern is displaced in the method for forming a wiring structure according to the first embodiment of the present invention; It is.

FIGS. 9A to 9C are cross-sectional views illustrating a method for forming a wiring structure according to a second embodiment of the present invention.

FIGS. 10A to 10C are cross-sectional views illustrating a method for forming a wiring structure according to a second embodiment of the present invention.

FIGS. 11A to 11C are cross-sectional views illustrating a method for forming a wiring structure according to a second embodiment of the present invention.

FIGS. 12A to 12C are cross-sectional views illustrating a method for forming a wiring structure according to a third embodiment of the present invention.

FIGS. 13A to 13C are cross-sectional views illustrating a method for forming a wiring structure according to a third embodiment of the present invention.

14A to 14C are cross-sectional views illustrating a method for forming a wiring structure according to a third embodiment of the present invention.

FIGS. 15A to 15C are cross-sectional views illustrating a method for forming a wiring structure according to a modification of the third embodiment of the present invention.

FIGS. 16A to 16D are cross-sectional views illustrating a method for forming a wiring structure according to a modification of the third embodiment of the present invention.

17A to 17C are cross-sectional views illustrating a method for forming a wiring structure according to a modification of the third embodiment of the present invention.

FIGS. 18A to 18C are cross-sectional views illustrating a method for forming a wiring structure according to a fourth embodiment of the present invention.

FIGS. 19A to 19C are cross-sectional views illustrating a method for forming a wiring structure according to a fourth embodiment of the present invention.

FIGS. 20A to 20C are cross-sectional views illustrating a method for forming a wiring structure according to a fourth embodiment of the present invention.

FIGS. 21A to 21C are cross-sectional views illustrating a method for forming a wiring structure according to a fifth embodiment of the present invention.

FIGS. 22A to 22C are cross-sectional views illustrating a method for forming a wiring structure according to a fifth embodiment of the present invention.

FIGS. 23A to 23D are cross-sectional views illustrating a method for forming a wiring structure according to a fifth embodiment of the present invention.

FIGS. 24A to 24C are cross-sectional views illustrating a method for forming a wiring structure according to a modification of the fifth embodiment of the present invention.

FIGS. 25A to 25C are cross-sectional views illustrating a method for forming a wiring structure according to a modification of the fifth embodiment of the present invention.

FIGS. 26A to 26D are cross-sectional views illustrating a method of forming a wiring structure according to a modification of the fifth embodiment of the present invention.

FIGS. 27A and 27B are perspective views showing a method of forming a wiring structure according to a modification of the fifth embodiment of the present invention.

FIGS. 28A and 28B are perspective views showing a method for forming a wiring structure according to a modification of the fifth embodiment of the present invention.

FIGS. 29A and 29B are perspective views showing a method for forming a wiring structure according to a modification of the fifth embodiment of the present invention.

FIGS. 30A to 30C are cross-sectional views illustrating a method for forming a wiring structure according to a sixth embodiment of the present invention.

FIGS. 31A to 31C are cross-sectional views illustrating a method for forming a wiring structure according to a sixth embodiment of the present invention.

FIGS. 32A to 32C are cross-sectional views illustrating a method for forming a wiring structure according to a sixth embodiment of the present invention.

FIGS. 33A to 33C are cross-sectional views illustrating a method for forming a wiring structure according to a modification of the sixth embodiment of the present invention.

FIGS. 34A to 34C are cross-sectional views illustrating a method for forming a wiring structure according to a modification of the sixth embodiment of the present invention.

FIGS. 35A to 35C are cross-sectional views illustrating a method for forming a wiring structure according to a modification of the sixth embodiment of the present invention.

FIG. 36 is a plan view showing a relationship between a wiring formation opening of a mask pattern and a contact hole formation opening of a second resist pattern according to a modification of the fifth embodiment.

FIG. 37A shows a modification of the fifth embodiment.
It is a figure which shows the positional relationship between a mask pattern and a 2nd resist pattern, and the positional relationship between a 1st metal wiring and a contact, and (b) is a figure which shows the mask pattern and the 2nd resist pattern in 5th Embodiment. FIG. 5 is a diagram showing a positional relationship between the first metal wiring and a contact.

[Explanation of symbols]

Reference Signs List 100 semiconductor substrate 101 first metal wiring 102 silicon nitride film 102A patterned silicon nitride film 103 first organic film (first insulating film) 103A patterned first organic film 104 organic-containing silicon oxide film (Second insulating film) 104A Patterned organic-containing silicon oxide film 105 Second organic film (third insulating film) 105A Patterned second organic film 106 Titanium nitride film (thin film) 107 First Resist pattern 108 mask pattern 109 second resist pattern 110 contact hole 111 wiring groove 112 adhesion layer 113 metal film 114 second metal wiring 115 contact 200 semiconductor substrate 201 first metal wiring 202 silicon nitride film 202A patterned Silicon nitride film 203 First organic film ( (First insulating film) 203A Patterned first organic film 204 Organic-containing silicon oxide film (second insulating film) 204A Patterned organic-containing silicon oxide film 205 Second organic film (third insulating film) Film) 205A patterned second organic film 206 titanium nitride film 207 first resist pattern 208 mask pattern 209 second resist pattern 210 contact hole 211 wiring groove 212 adhesion layer 213 metal film 214 second metal wiring 215 Contact 300 Semiconductor substrate 301 First metal wiring 302 Silicon nitride film 302A Patterned silicon nitride film 303 First organic-containing silicon oxide film (first insulating film) 303A Patterned first organic-containing silicon oxide Film 304 Low dielectric constant SOG film (second insulating film) 30 A Patterned low dielectric constant SOG film 305 Second organic-containing silicon oxide film (third insulating film) 305A Patterned second organic-containing silicon oxide film 306 Titanium nitride film 307 First resist pattern 308 Mask pattern 309 Second resist pattern 310 Contact hole 311 Wiring groove 312 Adhesive layer 313 Metal film 314 Second metal wiring 315 Contact 350 Semiconductor substrate 351 First metal film 352 Silicon nitride film 352A Patterned silicon nitride film 353 First silicon oxide film (first insulating film) 353A Patterned first silicon oxide film 354 Organic film (second insulating film) 354A Patterned organic film 355 Second silicon oxide film (second 355A Patterned second film Con oxide film 356 Titanium nitride film 357 First resist pattern 358 Mask pattern 359 Second resist pattern 360 Contact hole forming opening 361 Contact hole 362 Wiring groove 363 Adhesion layer 364 Metal film 365 Second metal wiring 366 Contact 400 Semiconductor substrate 401 First metal wiring 402 Silicon nitride film 402A Patterned silicon nitride film 403 First low dielectric constant SOG film (first insulating film) 403A Patterned first low dielectric constant SOG film 404 Organic containing silicon oxide film (second insulating film) 404A Patterned organic containing silicon oxide film 405 Second low dielectric constant SOG film (third insulating film) 405A Patterned second low dielectric constant SOG Film 406 titanium nitride film 407 first resist Turn 408 Mask pattern 409 Second resist pattern 410 Damage layer 411 Contact hole 412 Wiring groove 413 Adhesion layer 414 Metal film 415 Second metal film 416 Contact 500 Semiconductor substrate 501 First metal wiring 502 Silicon nitride film 502A Patterned Silicon nitride film 503 first organic film (first insulating film) 503A patterned first organic film 504 first silicon oxide film (second insulating film) 504A patterned first silicon Oxide film 505 Second organic film (third insulating film) 505A Patterned second organic film 505B Patterned second organic film 506 Second silicon oxide film (fourth insulating film) 506A Patterned second silicon oxide film 506B Patterned second silicon oxide film 506B Recon oxide film 507 Titanium nitride film (thin film) 508 First resist pattern 509 Mask pattern 510 Second resist pattern 511 Wiring groove 512 Contact hole 513 Second metal wiring 514 Contact 550 Semiconductor substrate 551 First metal wiring 552 Silicon Nitride film 552A patterned silicon nitride film 553 first organic film (first insulating film) 553A patterned first organic film 554 first silicon oxide film (second insulating film) 554A patterned First silicon oxide film 555 formed Second organic film (third insulating film) 555A Second organic film patterned 555B Second organic film patterned 556 Second silicon oxide film (second 556A Patterned second silicon oxide film 556B Second silicon oxide film 557 titanium nitride film (thin film) 558 first resist pattern 559 mask pattern 560 second resist pattern 561 wiring groove 562 contact hole 563 second metal wiring 564 contact 600 semiconductor substrate 601 First metal wiring 602 Silicon nitride film 602A Patterned silicon nitride film 603 First organic film (first insulating film) 603A Patterned first organic film 604 Silicon oxide film (second insulating film) Film) 604A Patterned silicon oxide film 605 Second organic film (third insulating film) 605A Patterned second organic film 606 Titanium nitride film (thin film) 607 First resist pattern 608 Mask pattern 609 Second resist pattern 610 Wiring groove 611 Contact hole 612 Second metal wiring 613 Contact 650 Semiconductor substrate 651 First metal wiring 652 Silicon nitride film 652A Patterned silicon nitride film 653 First organic film (first insulating film) 653A Patterned first 1st organic film 654 silicon oxide film (second insulating film) 654A patterned silicon oxide film 655 second organic film (third insulating film) 655A patterned second organic film 656 titanium nitride film (Thin film) 657 First resist pattern 658 Mask pattern 659 Second resist pattern 660 Wiring groove 661 Contact hole 662 Second metal wiring 663 Contact

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (3)

(57) [Claims] 1. A first step of forming a first insulating film on a lower metal wiring, and a second insulating film having a composition different from that of the first insulating film on the first insulating film. Forming a third insulating film composed of an organic film and having a different composition from the second insulating film on the second insulating film; and forming a third insulating film on the third insulating film. Forming a thin film, forming a first resist pattern having an opening for forming a wiring on the thin film, etching the thin film using the first resist pattern as a mask, Forming a mask pattern made of the thin film and having an opening for forming a wiring; and, after removing the first resist pattern, an opening for forming a contact hole on the third insulating film and the mask pattern. Resist pattern having Forming a third hole in the third insulating film by performing dry etching on the third insulating film using the second resist pattern and the mask pattern as a mask. Patterning such that an opening for formation is formed and removing the second resist pattern; and dry-etching using the third insulating film patterned with respect to the second insulating film as a mask The step of patterning the second insulating film so that a contact hole forming opening is formed in the second insulating film; Dry etching is performed using the mask pattern as a mask, and the second insulating film patterned with respect to the first insulating film is used as a mask. Forming a wiring groove in the patterned third insulating film by performing etching, and forming a contact hole in the first insulating film; and forming a metal film in the wiring groove and the contact hole. Forming a contact for connecting an upper metal wiring and the lower metal wiring to the upper metal wiring by filling the wiring structure. 2. The method according to claim 1, wherein the first insulating film contains an organic component as a main component. 3. The dimension of the contact hole forming opening of the second resist pattern is enlarged in a direction perpendicular to the direction in which the metal wiring of the upper layer extends with respect to the design opening dimension of the contact hole. The method for forming a wiring structure according to claim 1, wherein