JP3068814B2 - Method of manufacturing high voltage power device - Google Patents
Method of manufacturing high voltage power deviceInfo
- Publication number
- JP3068814B2 JP3068814B2 JP10291039A JP29103998A JP3068814B2 JP 3068814 B2 JP3068814 B2 JP 3068814B2 JP 10291039 A JP10291039 A JP 10291039A JP 29103998 A JP29103998 A JP 29103998A JP 3068814 B2 JP3068814 B2 JP 3068814B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- forming
- well
- conductivity type
- power device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 17
- 238000010438 heat treatment Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229920001917 Ficoll Polymers 0.000 claims 1
- 239000012895 dilution Substances 0.000 claims 1
- 238000010790 dilution Methods 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 239000000243 solution Substances 0.000 claims 1
- 239000012535 impurity Substances 0.000 description 15
- 239000010410 layer Substances 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus (Phosphorus) ions Chemical class 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体技術に関
し、特にＭＯＳ型高電圧電力素子の製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly to a method for manufacturing a MOS type high voltage power device.
【０００２】[0002]
【従来の技術】一般に、１００〜５００Ｖ用Ｐ型高電圧
電力素子は、水平二重拡散型のＭＯＳ技術を利用して製
造し、ステップモーター（step motor）、ＦＥＤ（fiel
d emission display）、及びＰＤＰ（plasma display p
anel）の駆動ＩＣ（integratedcircuit）等に利用され
る。2. Description of the Related Art In general, a P-type high-voltage power device for 100 to 500 V is manufactured by using a horizontal double diffusion type MOS technology, and a step motor, a FED (fiel) is used.
d emission display) and PDP (plasma display p)
Anel) is used for a drive IC (integrated circuit) or the like.
【０００３】高い降伏電圧を持つ水平型電力素子を具現
するために、従来では、Ｐ型（あるいはＮ型）半導体基
板上に比抵抗の高いＮ型エピタキシャル層で形成された
Ｎ−ドリフト（drift）領域を利用して電力素子の降伏
電圧及びＯＮ−抵抗値を改善するために素子の構造的な
変化を図り工程を改善する技術が多く開発されてきた。In order to implement a horizontal power device having a high breakdown voltage, conventionally, an N-drift formed of an N-type epitaxial layer having a high specific resistance on a P-type (or N-type) semiconductor substrate is used. In order to improve the breakdown voltage and the ON-resistance value of the power device by using the region, many techniques for improving the process by changing the structure of the device have been developed.
【０００４】このような従来の方法は、エピタキシャル
層の厚さ及び不純物濃度、ドリフト領域の厚さ及び不純
物の濃度によって垂直及び水平方向の降伏電圧値を決定
して、金属電界版（field plate）またはドレーン領域
に金属電極（metal electrode）を長く形成して電場の
強さを緩和させることで降伏電圧を改善している。In such a conventional method, the breakdown voltage in the vertical and horizontal directions is determined according to the thickness and the impurity concentration of the epitaxial layer, the thickness of the drift region and the impurity concentration, and a metal field plate is used. Alternatively, the breakdown voltage is improved by forming a long metal electrode in the drain region to relax the strength of the electric field.
【０００５】これまでＰ−型電力素子の降伏電圧及びＯ
Ｎ−抵抗値において多くの改善がなされたが、さらに改
善されなければならなく、降伏電圧を低めればそれに従
ってＯＮ−抵抗値が増加するようになるのでこの２種類
の要素らの最適化のための技術の開発が要求されてい
る。Heretofore, the breakdown voltage and O
Many improvements in N-resistance have been made, but they must be further improved, and lowering the breakdown voltage will increase the ON-resistance accordingly, thus optimizing the two elements. There is a demand for technology development.
【０００６】図１０は従来技術によって形成された水平
型Ｐ−チャンネル高電圧電力素子の断面構造を図示した
もので、以下、これを参照してその製造工程を概略的に
考察してみれば次の通りである。まず、半導体基板２０
上に埋込酸化物層１、Ｐ型エピタキシャル層２、深いＮ
−ウェル３を順に形成して、深いＮ−ウェル３上にＰ型
ドリフト領域４とＮ−ウェル５とを形成する。その次
に、ＬＯＣＯＳ（local oxidation of silicon）技術を
利用して素子の活性領域と非活性領域を定義するフィー
ルド酸化膜６を形成して、Ｐ型ドリフト領域４とＮ−ウ
ェル５とが接する領域の基板上にゲート酸化膜７及び多
結晶シリコンゲート８を形成する。FIG. 10 shows a cross-sectional structure of a horizontal P-channel high-voltage power element formed by the prior art. Referring to FIG. It is as follows. First, the semiconductor substrate 20
Buried oxide layer 1, P-type epitaxial layer 2, deep N
Forming a well 3 in order, and forming a P-type drift region 4 and an N-well 5 on the deep N-well 3; Next, a field oxide film 6 defining an active region and a non-active region of the device is formed using LOCOS (local oxidation of silicon) technology, and a region where the P-type drift region 4 and the N-well 5 are in contact with each other is formed. A gate oxide film 7 and a polycrystalline silicon gate 8 are formed on the substrate.
【０００７】続けて、Ｐ型ドリフト領域４とＮ−ウェル
５との所定領域にＰ型不純物イオン注入を実施してソー
ス領域１０とドレーン領域９とを形成する。次いで、Ｎ
型不純物イオン注入を実施してソース領域１０に接する
Ｎ＋型ソースコンタクト１３を形成した後、ソース領域
１０及びドレーン領域９とＮ＋型ソースコンタクト１３
及びゲート電極８との一部を露出させる層間絶縁膜１１
を形成して、全面に金属を塗布して、これをフォトリソ
グラフィー法でパターニングして金属電極１２を形成す
ることによって素子の製造を完了する。Subsequently, P-type impurity ions are implanted into predetermined regions of P-type drift region 4 and N-well 5 to form source region 10 and drain region 9. Then N
After forming an N + type source contact 13 in contact with the source region 10 by performing impurity ion implantation, the source region 10 and the drain region 9 are connected to the N + type source contact 13.
And interlayer insulating film 11 exposing a part of gate electrode 8
Is formed, a metal is applied to the entire surface, and is patterned by photolithography to form a metal electrode 12, thereby completing the manufacture of the element.
【０００８】[0008]
【発明が解決しようとする課題】ところが、上記の工程
中でフィールド酸化膜６を形成するためには１０００℃
の高温で進行される長時間の熱酸化工程を必要とする。
これに伴いフィールド酸化膜６形成工程が進行される間
にドリフト領域４に注入された不純物の外部拡散が発生
することと同時に、フィールド酸化膜の側面部でのバー
ズビーク（bird'sbeak）効果による側面及び垂直方向へ
の酸化膜成長が発生して、フィールド酸化膜６を形成す
るためのマスクパターンの長さ（設計値）よりフィール
ド酸化膜６の形成領域の長さがＡで示されるように設計
値より拡大されるのでＯＮ−抵抗値が増加するようにな
る問題点が誘発される。However, in order to form the field oxide film 6 during the above steps, it is necessary to use a temperature of 1000.degree.
Requires a prolonged thermal oxidation step which is carried out at a high temperature.
As a result, the external diffusion of the impurities implanted into the drift region 4 occurs while the field oxide film 6 forming process proceeds, and at the same time, the side surface due to the bird's beak effect at the side surface portion of the field oxide film. The length of the region where the field oxide film 6 is formed is indicated by A from the length (design value) of the mask pattern for forming the field oxide film 6 due to the growth of the oxide film in the vertical direction. Since the ON-resistance value is increased, the ON-resistance value increases.
【０００９】本発明は上述した従来例に係る問題点を解
消するためになされたもので、ドリフト領域の不純物外
部拡散を最小化してドリフト領域の長さを低減させてＯ
Ｎ−抵抗を改善できる高電圧電力素子の製造方法を提供
しようとする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the prior art, and minimizes the out-diffusion of impurities in the drift region to reduce the length of the drift region.
It is an object of the present invention to provide a method for manufacturing a high-voltage power device capable of improving N-resistance.
【００１０】[0010]
【課題を解決するための手段】本発明に係る高電圧電力
素子の製造方法は、半導体基板上部のエピタキシャル層
に第１導電型の第１ウェルを形成する第１段階と、上記
第１ウェル内に第２導電型のドリフト領域及び第１導電
型の第２ウェルを形成する第２段階と、上記第２導電型
のドリフト領域及び第１導電型の第２ウェル上に所定厚
さのパッド酸化膜を形成する第３段階と、上記第３段階
遂行後、全体構造上部に所定厚さの第１ＴＥＯＳ酸化膜
を形成する第４段階と、上記第１ＴＥＯＳ酸化膜を熱処
理する第５段階と、上記第１ＴＥＯＳ酸化膜の熱処理
後、第１ＴＥＯＳ酸化膜上に所定厚さの第２ＴＥＯＳ酸
化膜を形成する第６段階と、上記第１ＴＥＯＳ酸化膜と
上記第２ＴＥＯＳ酸化膜を傾斜蝕刻して活性領域に予定
される領域を露出させるフィールド酸化膜を形成する第
７段階と、上記第７段階遂行後、基板全面を酸化して酸
化膜を成長させる第８段階と、上記第８段階で成長され
た酸化膜上部に多結晶シリコン膜を形成する第９段階
と、上記第８及び第９段階で形成された多結晶シリコン
膜及び上記酸化膜を順に選択蝕刻してゲート酸化膜及び
ゲート電極を形成する第１０段階と、上記第１導電型の
第２ウェル及び第２導電型のドリフト領域に第２導電型
のソース／ドレーン領域を形成する第１１段階とを含む
ものである。According to the present invention, there is provided a method of manufacturing a high-voltage power device, comprising: a first step of forming a first well of a first conductivity type in an epitaxial layer above a semiconductor substrate; Forming a drift region of the second conductivity type and a second well of the first conductivity type on the second conductive type;
A predetermined thickness on the drift region and the second well of the first conductivity type.
A third step of forming a pad oxide film having a predetermined thickness, a fourth step of forming a first TEOS oxide film having a predetermined thickness on the entire structure after performing the third step, and a heat treatment of the first TEOS oxide film.
And heat treatment of the first TEOS oxide film
Thereafter, a second TEOS acid having a predetermined thickness is formed on the first TEOS oxide film.
A sixth step of forming an oxide film, and the first TEOS oxide film
The second TEOS oxide film is inclined etched and is scheduled for the active region
The forming field oxide to expose the area to be
After performing the seventh step and the seventh step, the entire surface of the substrate is oxidized and acidified.
An eighth step of growing the oxide film; and
Ninth step of forming a polycrystalline silicon film on top of the damaged oxide film
And the polycrystalline silicon formed in the eighth and ninth steps.
Selectively etching the film and the oxide film sequentially to form a gate oxide film and
A tenth step of forming a gate electrode;
An eleventh step of forming a source / drain region of the second conductivity type in the second well and the drift region of the second conductivity type.
【００１１】また、上記第７段階における傾斜蝕刻は、
稀釈されたＨＦ溶液を使用した蝕刻法を利用することを
特徴とするものである。 The tilt etching in the seventh step is as follows.
An etching method using a diluted HF solution is used .
【００１２】また、上記第１ＴＥＯＳ酸化膜の厚さは、
５０００ないし８０００Åであり、上記第２ＴＥＯＳ酸
化膜の厚さは、２０００ないし３０００Åであることを
特徴とするものである。Further, the thickness of the first TEOS oxide film is as follows:
5000 to 8000 °, the second TEOS acid
The thickness of the passivation film is 2000 to 3000 ° .
【００１３】また、上記第５段階における上記第１ＴＥ
ＯＳ酸化膜の熱処理は、８５０℃に熱処理することを特
徴とするものである。Further, the first TE in the fifth stage
The heat treatment of the OS oxide film is characterized in that the heat treatment is performed at 850 ° C.
【００１４】さらに、上記第３段階における上記パッド
酸化膜の厚さは２００ないし５００Åであることを特徴
とするものである。Further, the pad in the third stage
The oxide film has a thickness of 200 to 500 ° .
【００１５】[0015]
【発明の実施の形態】本発明に係る高電圧電力素子の製
造方法は、半導体基板上部のエピタキシャル層に第１導
電型の第１ウェルを形成する第１段階と、上記第１ウェ
ル内に第２導電型のドリフト領域及び第１導電型の第２
ウェルを形成する第２段階と、上記第２導電型のドリフ
ト領域及び第１導電型の第２ウェル上に所定厚さのパッ
ド酸化膜を形成する第３段階と、上記第３段階遂行後、
全体構造上部に所定厚さの第１ＴＥＯＳ酸化膜を形成す
る第４段階と、上記第１ＴＥＯＳ酸化膜を熱処理する第
５段階と、上記第１ＴＥＯＳ酸化膜の熱処理後、第１Ｔ
ＥＯＳ酸化膜上に所定厚さの第２ＴＥＯＳ酸化膜を形成
する第６段階と、上記第１ＴＥＯＳ酸化膜と上記第２Ｔ
ＥＯＳ酸化膜を傾斜蝕刻して活性領域に予定される領域
を露出させるフィールド酸化膜を形成する第７段階と、
上記第７段階遂行後、基板全面を酸化して酸化膜を成長
させる第８段階と、上記第８段階で成長された酸化膜上
部に多結晶シリコン膜を形成する第９段階と、上記第８
及び第９段階で形成された多結晶シリコン膜及び上記酸
化膜を順に選択蝕刻してゲート酸化膜及びゲート電極を
形成する第１０段階と、上記第１導電型の第２ウェル及
び第２導電型のドリフト領域に第２導電型のソース／ド
レーン領域を形成する第１１段階とを含む。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a high voltage power device according to the present invention includes a first step of forming a first well of a first conductivity type in an epitaxial layer on a semiconductor substrate, and a step of forming a first well in the first well. Drift region of two conductivity type and second region of first conductivity type
A second step of forming a well, and the second conductivity type drift
A predetermined thickness on the first region and the second well of the first conductivity type.
A third step of forming an oxide film, and after performing the third step,
A fourth step of forming a first TEOS oxide film having a predetermined thickness on the entire structure, and a fourth step of heat-treating the first TEOS oxide film .
After the heat treatment of the first TEOS oxide film, the first T
Form a second TEOS oxide film of a predetermined thickness on the EOS oxide film
The first TEOS oxide film and the second T
EOS oxide film is obliquely etched and is expected to be an active region
A seventh step of forming a field oxide film exposing
After performing the seventh step, the entire surface of the substrate is oxidized to grow an oxide film
An eighth step of forming, and on the oxide film grown in the eighth step
A ninth step of forming a polycrystalline silicon film in the portion;
And the polycrystalline silicon film formed in the ninth step and the acid
Gate oxide film and gate electrode by selective etching of
A tenth step of forming, a second well of the first conductivity type and
Each time drift region of a second conductivity type and a second 11 forming a source / drain region of the second conductivity type.
【００１６】また、本発明は、高電圧電力素子の製造工
程中でフィールド酸化膜を形成する時に、ドリフト領域
上に既存のＬＯＣＯＳ技術を利用してフィールド酸化膜
を形成する代わりにＴＥＯＳ酸化膜を蒸着して、これを
パターニングしてフィールド酸化膜を形成する。したが
って、ドリフト領域の長さが短縮されて、また低温でフ
ィールド酸化膜が形成されることによってドリフト領域
の不純物が外部拡散されないことによりＯＮ−抵抗が改
善される。Further, according to the present invention, when a field oxide film is formed in a manufacturing process of a high voltage power element, a TEOS oxide film is formed on a drift region instead of forming a field oxide film using an existing LOCOS technique. It is deposited and patterned to form a field oxide film. Therefore, the length of the drift region is reduced, and the ON-resistance is improved by forming the field oxide film at a low temperature so that impurities in the drift region are not diffused out.
【００１７】以下、本発明が属する技術分野で通常の知
識を持った者が本発明をより容易に実施できるように本
発明の望ましい実施の形態を説明する。Hereinafter, preferred embodiments of the present invention will be described so that those skilled in the art to which the present invention pertains can more easily implement the present invention.
【００１８】図１ないし図７は本発明の一実施の形態に
係るＰ−チャンネルの高電圧電力素子製造工程を図示し
たことで、以下、これを参照してその製造工程を説明す
る。FIGS. 1 to 7 illustrate a process of manufacturing a P-channel high-voltage power device according to an embodiment of the present invention, and the manufacturing process will be described below with reference to FIG.
【００１９】まず、図１に図示した通り、Ｎ型半導体基
板２０上に埋込酸化物層２１及びＰ−エピタキシャル層
２２が形成された基板を利用する。First, as shown in FIG. 1, a substrate having a buried oxide layer 21 and a P-epitaxial layer 22 formed on an N-type semiconductor substrate 20 is used.
【００２０】次いで、図２に図示した通り、Ｐ−エピタ
キシャル層にリン（Phosphorus）イオンを注入した後、
１２００℃で２５時間熱処理を遂行して深いＮ−ウェル
２３を形成して、深いＮ−ウェル２３上に漂流領域を定
義するイオン注入マスク（図示せず）を形成した後、Ｐ
型不純物として硼素（Ｂ）をイオン注入して、イオン注
入マスクを除去した後、深いＮ−ウェル２３上にＮ−ウ
ェルを定義するイオン注入マスク（図示せず）を形成し
て、Ｎ型不純物としてリン（Ｐ）を注入した後、１２０
０℃で１５時間の間熱処理を遂行してＰ型ドリフト領域
２４及びそれに接するＮ−ウェル２５を形成する。Next, as shown in FIG. 2, after implanting phosphorus (Phosphorus) ions into the P-epitaxial layer,
After performing a heat treatment at 1200 ° C. for 25 hours, a deep N-well 23 is formed, and an ion implantation mask (not shown) defining a drift region is formed on the deep N-well 23.
After boron (B) is ion-implanted as a type impurity and the ion implantation mask is removed, an ion implantation mask (not shown) for defining an N-well is formed on the deep N-well 23 to form an N-type impurity. After injecting phosphorus (P) as
A heat treatment is performed at 0 ° C. for 15 hours to form a P-type drift region 24 and an N-well 25 in contact therewith.
【００２１】次に、図３に図示した通り、基板の全面に
２００〜５００Å厚さの酸化膜（図示せず）を成長させ
て、１次で５０００〜８０００Å厚さのＴＥＯＳ酸化膜
を蒸着させた後８５０℃で熱処理を遂行して、２次で２
０００〜３０００Å厚さのＴＥＯＳ酸化膜を蒸着した後
希釈された佛酸（ＨＦ）を利用してＴＥＯＳ酸化膜を蝕
刻して電力素子の活性領域（ソース／ドレーン領域及び
ゲート領域）に予定された領域を露出させるフィールド
酸化膜２６を形成する。この時、フィールド酸化膜２６
の形成のために傾斜蝕刻工程を進行してフィールド酸化
膜２６の側壁が傾斜するようにする。Next, as shown in FIG. 3, an oxide film (not shown) having a thickness of 200 to 500.degree. Is grown on the entire surface of the substrate, and a TEOS oxide film having a thickness of 5000 to 8000.degree. After that, heat treatment is performed at 850 ° C.
After depositing a TEOS oxide film having a thickness of 2,000 to 3,000 mm, the TEOS oxide film is etched using diluted HF to form active regions (source / drain regions and gate regions) of the power device. A field oxide film 26 exposing the region is formed. At this time, the field oxide film 26
An oblique etching process is performed to form a sidewall of the field oxide film 26.
【００２２】次いで、図４に図示した通り、基板の全面
を酸化して酸化膜を成長させて、その上部に多結晶シリ
コン膜を形成した後、ゲート電極形成用マスクを利用し
て多結晶シリコン膜と酸化膜とを順に選択蝕刻してゲー
ト酸化膜２７及びゲート電極２８とを形成する。Next, as shown in FIG. 4, the entire surface of the substrate is oxidized to grow an oxide film, a polycrystalline silicon film is formed thereon, and then the polycrystalline silicon film is formed using a gate electrode forming mask. The gate oxide film 27 and the gate electrode 28 are formed by selectively etching the film and the oxide film in this order.
【００２３】続けて、図５に図示した通り、露出された
基板の全面にＰ＋型不純物として硼素（Ｂ）をイオン注
入して各々Ｎ−ウェル２５とＰ型ドリフト領域２４とに
ソース領域３０及びドレーン領域２９を形成して、ソー
ス領域３０が一部露出されるようにマスキングした後Ｎ
＋型不純物としてＡｓを注入してＮ＋型ソースコンタク
ト３３を形成する。ソース領域３０に隣接したＮ＋型ソ
ースコンタクト３３はドレーン領域２９に高い電界がか
かる場合、衝突イオン化現象によって発生した電子-正
孔対の中で電子を効果的に除去するために形成される。Subsequently, as shown in FIG. 5, boron (B) is ion-implanted into the entire surface of the exposed substrate as a P + -type impurity, so that the source region 30 and the source region 30 are formed in the N-well 25 and the P-type drift region 24, respectively. After forming the drain region 29 and masking so that the source region 30 is partially exposed, N
As is implanted as a + type impurity to form an N + type source contact 33. The N + type source contact 33 adjacent to the source region 30 is formed to effectively remove electrons from the electron-hole pairs generated by the impact ionization phenomenon when a high electric field is applied to the drain region 29.
【００２４】次いで、図６に図示した通り、基板の全面
に層間絶縁膜を形成した後、これをフォトリソグラフィ
ー法でパターニングして上記ゲート電極２８、ソース領
域３０、ドレーン領域２９及びＮ＋型ソースコンタクト
の一部を露出させる。Next, as shown in FIG. 6, after forming an interlayer insulating film on the entire surface of the substrate, this is patterned by photolithography to form the gate electrode 28, the source region 30, the drain region 29 and the N + type source contact. Expose part of
【００２５】次に、図７に図示した通り、基板の全面に
アルミニウムを蒸着した後、これをパターニングしてソ
ース／ドレーン及びゲートの金属電極３２を形成する。
上記の工程を通じて製造された電力素子はフィールド酸
化膜２６をＴＥＯＳ膜で形成することによりドリフト領
域２４の表面が酸化されなくて平坦な表面を維持するよ
うにして、ＬＯＣＯＳ工程時必然的に現れるバーズビー
ク効果を根本的に防止することによってフィールド酸化
膜２６の長さＢがＬＯＣＯＳ工程を通した従来のフィー
ルド酸化膜の長さＡに比べて短くなるようになる。この
ようなフィールド酸化膜２６の長さの減少は結局ドリフ
ト領域の減少になって素子のＯＮ−抵抗値を改善するこ
とになる。Next, as shown in FIG. 7, aluminum is deposited on the entire surface of the substrate and then patterned to form metal electrodes 32 for source / drain and gate.
In the power device manufactured through the above process, the field oxide film 26 is formed of a TEOS film so that the surface of the drift region 24 is not oxidized and is maintained flat, so that a bird's beak which appears in the LOCOS process is inevitable. By fundamentally preventing the effect, the length B of the field oxide film 26 becomes shorter than the length A of the conventional field oxide film through the LOCOS process. Such a decrease in the length of the field oxide film 26 eventually leads to a decrease in the drift region, thereby improving the ON-resistance value of the device.
【００２６】図８は従来のＬＯＣＯＳ技術を利用してフ
ィールド酸化膜を形成した電力素子と本発明によってＴ
ＥＯＳ酸化膜を利用してフィールド酸化膜を形成した電
力素子とのそれぞれの不純物の濃度分布を表したもの
で、図面を通じてＬＯＣＯＳ技術を利用してフィールド
酸化膜を形成した電力素子に比べて本発明に係る電力素
子のドリフト領域の不純物の濃度が非常に増加すること
が分かる。FIG. 8 shows a power device in which a field oxide film is formed by using the conventional LOCOS technique and a T element according to the present invention.
FIG. 3 shows the impurity concentration distribution of each of a power element having a field oxide film formed using an EOS oxide film, and the present invention is compared with a power element having a field oxide film formed using a LOCOS technique throughout the drawings. It can be seen that the concentration of impurities in the drift region of the power element according to (1) greatly increases.
【００２７】図９は従来のＬＯＣＯＳ技術を利用してフ
ィールド酸化膜を形成した電力素子と本発明によってＴ
ＥＯＳ酸化膜を利用してフィールド酸化膜を形成した電
力素子とのそれぞれの電流−電圧特性を表したものであ
る。FIG. 9 shows a power device in which a field oxide film is formed using a conventional LOCOS technique and a T element according to the present invention.
FIG. 4 shows current-voltage characteristics of a power device having a field oxide film formed by using an EOS oxide film.
【００２８】図面から本発明によって製作された素子の
ドレーン電流値が２倍程度高いことを確認することがで
き、その結果素子のＯＮ−抵抗値も３５〜４０％程度改
善された。反面、本発明に係る電力素子の降伏電圧を測
定した結果従来の電力素子に比べて降伏電圧値の減少が
但し５％程度であることを確認した。From the drawings, it can be confirmed that the drain current value of the device manufactured according to the present invention is about twice as high, and as a result, the ON-resistance value of the device is improved by about 35 to 40%. On the other hand, as a result of measuring the breakdown voltage of the power device according to the present invention, it was confirmed that the breakdown voltage value was reduced by about 5% as compared with the conventional power device.
【００２９】また、本発明は上記実施の形態になんら限
定されるものではなく、本発明の要旨を逸脱しない範囲
で種種の形態で実施することができる。Further, the present invention is not limited to the above embodiment, and can be implemented in various forms without departing from the gist of the present invention.
【００３０】[0030]
【発明の効果】上述したように、本発明によれば、ＭＯ
Ｓ型高電圧電力素子の製造工程中でフィールド酸化膜形
成時に低温工程が可能なＴＥＯＳ酸化膜を利用すること
によって、ドリフト領域で発生する不純物外部拡散を最
小化して、フィールド酸化膜の形成領域が拡大されるこ
とを防止できるので電力素子のＯＮ−抵抗値を改善する
効果があり、また、電力素子の降伏電圧をほとんど減少
させない長所がある。As described above, according to the present invention, the MO
By using the TEOS oxide film, which can be formed at a low temperature during the formation of the field oxide film during the manufacturing process of the S-type high voltage power device, the external diffusion of impurities generated in the drift region is minimized, and the field oxide film formation region is reduced. Since the expansion can be prevented, the ON-resistance value of the power element is improved, and the breakdown voltage of the power element is hardly reduced.
【図１】 本発明の一実施の形態に係るＰ−チャンネル
高電圧電力素子の製造工程の説明図である。FIG. 1 is an explanatory diagram of a manufacturing process of a P-channel high-voltage power device according to one embodiment of the present invention.
【図２】 図１に続く製造工程の説明図である。FIG. 2 is an explanatory view of a manufacturing process following FIG. 1;
【図３】 図２に続く製造工程の説明図である。FIG. 3 is an explanatory view of a manufacturing process following FIG. 2;
【図４】 図３に続く製造工程の説明図である。FIG. 4 is an explanatory view of the manufacturing process following FIG. 3;
【図５】 図４に続く製造工程の説明図である。FIG. 5 is an explanatory view of the manufacturing process following FIG. 4;
【図６】 図５に続く製造工程の説明図である。FIG. 6 is an explanatory view of the manufacturing process following FIG. 5;
【図７】 図６に続く製造工程の説明図である。FIG. 7 is an explanatory view of the manufacturing process following FIG. 6;
【図８】 ＬＯＣＯＳ技術を利用した従来の電力素子及
び本発明によってＴＥＯＳ酸化膜を利用した電力素子そ
れぞれの不純物分布特性図である。FIG. 8 is an impurity distribution characteristic diagram of a conventional power device using the LOCOS technology and a power device using a TEOS oxide film according to the present invention.
【図９】 ＬＯＣＯＳ技術を利用した従来の電力素子及
び本発明によってＴＥＯＳ酸化膜を利用した電力素子そ
れぞれの電流-電圧特性図である。FIG. 9 is a current-voltage characteristic diagram of a conventional power device using a LOCOS technology and a power device using a TEOS oxide film according to the present invention.
【図１０】 従来技術によって形成されたＰ−チャンネ
ル高電圧電力素子の断面図である。FIG. 10 is a cross-sectional view of a P-channel high voltage power device formed according to the prior art.
２０ 基板、２１ 埋込酸化物層、２２ Ｐ−エピタキ
シャル層、２３ 深いＮ−ウェル、２４ Ｐ型ドリフト
領域、２５ Ｎ−ウェル、２６ フィールド酸化膜、２
７ ゲート酸化膜、２８ 多結晶シリコン膜、２９ ド
レーン領域、３０ ソース領域、３１ 層間絶縁膜、３
２ 金属電極、３３ Ｎ＋型ソースコンタクト。Reference Signs List 20 substrate, 21 buried oxide layer, 22 P-epitaxial layer, 23 deep N-well, 24 P-type drift region, 25 N-well, 26 field oxide film, 2
7 gate oxide film, 28 polycrystalline silicon film, 29 drain region, 30 source region, 31 interlayer insulating film, 3
2 Metal electrode, 33 N + type source contact.
フロントページの続き (72)発明者 具 珍 根 大韓民国大田市儒城區柯亭洞161 韓國 電子通信研究院内 (56)参考文献 特開 平８−316469（ＪＰ，Ａ) 特開 平２−291166（ＪＰ，Ａ) 特開 平８−236757（ＪＰ，Ａ) 特開 昭63−173340（ＪＰ，Ａ) 特開 平６−53502（ＪＰ，Ａ) 特開 平９−223798（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 21/336 H01L 29/786 Continuation of the front page (72) Inventor Jin Jin, 161 Kejeong-dong, Yuseong-gu, Daejeon-si, Republic of Korea (56) References JP-A-8-316469 (JP, A) JP-A-2-291166 ( JP, A) JP-A-8-237557 (JP, A) JP-A-63-173340 (JP, A) JP-A-6-53502 (JP, A) JP-A-9-223798 (JP, A) (58) ) Surveyed field (Int.Cl. 7 , DB name) H01L 29/78 H01L 21/336 H01L 29/786
Claims (5)
１導電型の第１ウェルを形成する第１段階と、 上記第１ウェル内に第２導電型のドリフト領域及び第１
導電型の第２ウェルを形成する第２段階と、上記第２導電型のドリフト領域及び第１導電型の第２ウ
ェル上に所定厚さのパッド酸化膜を形成する第３段階
と、 上記第３段階遂行後、全体構造上部に所定厚さの第１Ｔ
ＥＯＳ酸化膜を形成する第４段階と、上記第１ＴＥＯＳ酸化膜を熱処理する第５段階と、 上記第１ＴＥＯＳ酸化膜の熱処理後、第１ＴＥＯＳ酸化
膜上に所定厚さの第２ＴＥＯＳ酸化膜を形成する第６段
階と、 上記第１ＴＥＯＳ酸化膜と上記第２ＴＥＯＳ酸化膜を 傾
斜蝕刻して活性領域に予定される領域を露出させるフィ
ールド酸化膜を形成する第７段階と、 上記第７段階遂行後、基板全面を酸化して酸化膜を成長
させる第８段階と、 上記第８段階で成長された酸化膜上部に多結晶シリコン
膜を形成する第９段階と、 上記第８及び第９段階で形成された多結晶シリコン膜及
び上記酸化膜を順に選択蝕刻してゲート酸化膜及びゲー
ト電極を形成する第１０段階と、 上記第１導電型の第２ウェル及び第２導電型のドリフト
領域に 第２導電型のソース／ドレーン領域を形成する第
１１段階とを含む高電圧電力素子の製造方法。A first step of forming a first well of a first conductivity type in an epitaxial layer above a semiconductor substrate; and a drift region of a second conductivity type and a first well in the first well.
A second step of forming a second well of the conductivity type, the drift region of the second conductivity type and the second well of the first conductivity type;
Third step of forming pad oxide film of predetermined thickness on well
If, after the third step performed, the 1 T of predetermined thickness on the entire structure
A fourth step of forming an EOS oxide film, a fifth step of heat-treating the first TEOS oxide film, and a first TEOS oxidation after the heat treatment of the first TEOS oxide film.
Sixth step of forming a second TEOS oxide film having a predetermined thickness on the film
A floor, and a seventh step of forming Ficoll <br/> Rudo oxide film to expose the area to be expected the first 1TEOS oxide film and the first 2TEOS oxide film on the inclined etching to the active region, the seventh step performed Later, the entire surface of the substrate is oxidized to grow an oxide film
An eighth step of forming a polysilicon layer on the oxide film grown in the eighth step.
A ninth step of forming a film, the polycrystalline silicon film formed in the eighth and ninth steps, and
Gate oxide film and gate
10th step of forming a gate electrode, and the second well of the first conductivity type and the drift of the second conductivity type.
The forming the source / drain regions of a second conductivity type in the region
11. A method for manufacturing a high-voltage power device, comprising:
されたＨＦ溶液を使用した蝕刻法を利用することを特徴
とする請求項１に記載の高電圧電力素子の製造方法。 2. The inclined etching in the seventh step is a dilution.
Characterized by using an etching method using a HF solution
The method for manufacturing a high-voltage power device according to claim 1.
００ないし８０００Åであり、上記第２ＴＥＯＳ酸化膜
の厚さは、２０００ないし３０００Åであることを特徴
とする請求項１に記載の高電圧電力素子の製造方法。 3. The thickness of the first TEOS oxide film is 50.
The second TEOS oxide film,
Characterized by a thickness of 2000 to 3000 mm
The method for manufacturing a high-voltage power device according to claim 1.
酸化膜の熱処理は、 ８５０℃に熱処理することを特徴と
する請求項１に記載の高電圧電力素子の製造方法。 4. The first TEOS in the fifth step.
The heat treatment of the oxide film is performed at a temperature of 850 ° C.
The method for manufacturing a high-voltage power device according to claim 1.
の厚さは２００ないし５００Åであることを特徴とする
請求項１に記載の高電圧電力素子の製造方法。 5. The pad oxide film in the third step
Characterized by a thickness of 200 to 500 mm
A method for manufacturing the high-voltage power device according to claim 1.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1997-61585 | 1997-11-20 | ||
| KR1019970061585A KR100289055B1 (en) | 1997-11-20 | 1997-11-20 | Method for fabricating p-channel double diffusion power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11191624A JPH11191624A (en) | 1999-07-13 |
| JP3068814B2 true JP3068814B2 (en) | 2000-07-24 |
Family
ID=19525196
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10291039A Expired - Fee Related JP3068814B2 (en) | 1997-11-20 | 1998-10-13 | Method of manufacturing high voltage power device |
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| Country | Link |
|---|---|
| JP (1) | JP3068814B2 (en) |
| KR (1) | KR100289055B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3831602B2 (en) * | 2000-12-07 | 2006-10-11 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| KR100788376B1 (en) * | 2006-09-13 | 2008-01-02 | 동부일렉트로닉스 주식회사 | Method for forming semiconductor device |
| KR100760924B1 (en) * | 2006-09-13 | 2007-09-21 | 동부일렉트로닉스 주식회사 | Method for forming semiconductor device |
| CN110491941B (en) * | 2018-05-15 | 2023-03-24 | 立锜科技股份有限公司 | High voltage device and method for manufacturing the same |
-
1997
- 1997-11-20 KR KR1019970061585A patent/KR100289055B1/en not_active IP Right Cessation
-
1998
- 1998-10-13 JP JP10291039A patent/JP3068814B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11191624A (en) | 1999-07-13 |
| KR100289055B1 (en) | 2001-08-07 |
| KR19990041054A (en) | 1999-06-15 |
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