JP3058151B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3058151B2
JP3058151B2 JP25310698A JP25310698A JP3058151B2 JP 3058151 B2 JP3058151 B2 JP 3058151B2 JP 25310698 A JP25310698 A JP 25310698A JP 25310698 A JP25310698 A JP 25310698A JP 3058151 B2 JP3058151 B2 JP 3058151B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor element
wiring pattern
semiconductor
pitch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP25310698A
Other languages
Japanese (ja)
Other versions
JPH11163497A (en
Inventor
伸晃 橋元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25310698A priority Critical patent/JP3058151B2/en
Publication of JPH11163497A publication Critical patent/JPH11163497A/en
Application granted granted Critical
Publication of JP3058151B2 publication Critical patent/JP3058151B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の構造
に関する。
The present invention relates to a structure of a semiconductor device.

【0002】[0002]

【従来の技術】従来、半導体装置の構造としては、特願
平01−015511号に示され、図2に示されるような構造が
知られていた。図2は従来の半導体装置の構造を基板側
から見た図であり、1は少なくとも表面が絶縁されてい
る基板でその絶縁表面上に2の装置外部との配線パター
ン及び3の装置内部の配線パターンが、5の半導体素子の
電極上に形成されている金属突起4に相対するように形
成されている。8は絶縁樹脂であり、半導体素子5と、基
板1はこの絶縁樹脂によって、配線パターンと、金属突
起の電気的接続を保ったまま、接着している。一般に半
導体素子の電極ピッチは50〜200μmであり、外部装置と
の結線を行う際は、さらにそのピッチを拡大し、図2の2
に示されるような配線パターンを形成することが多かっ
た。6は基板の端面を示し、7は基板端面と半導体素子の
距離を示す。従来の半導体装置の構造を液晶パネルに応
用した例を図3に示す。11は基板ガラスであり、16の対
向ガラスとの間に液晶が封入されている。11の基板ガラ
ス上には、図2で説明したような方式に従って、駆動用
半導体素子15が実装されている。12は駆動用半導体素子
へ入力信号を送出するための入力配線パターンであり、
17のフレキシブルコネクターと異方性導電膜、ハンダ付
け等で接続され、外部回路と接続されていた。また駆動
用半導体素子15からの出力は出力配線パターン13を通し
て液晶封入部へ導かれ、液晶駆動のための信号を液晶に
印加していた。
2. Description of the Related Art Conventionally, as a structure of a semiconductor device, a structure shown in Japanese Patent Application No. 01-015511 and shown in FIG. 2 has been known. FIG. 2 is a view of the structure of a conventional semiconductor device as viewed from the substrate side. Reference numeral 1 denotes a substrate having at least an insulated surface. The pattern is formed so as to face the metal protrusion 4 formed on the electrode of the semiconductor element 5. Reference numeral 8 denotes an insulating resin, and the semiconductor element 5 and the substrate 1 are adhered to each other by the insulating resin while maintaining the electrical connection between the wiring pattern and the metal protrusion. In general, the electrode pitch of a semiconductor element is 50 to 200 μm, and when connecting to an external device, the pitch is further expanded to 2 in FIG.
In many cases, a wiring pattern as shown in FIG. 6 indicates an end face of the substrate, and 7 indicates a distance between the end face of the substrate and the semiconductor element. FIG. 3 shows an example in which the structure of a conventional semiconductor device is applied to a liquid crystal panel. 11 is a substrate glass, and liquid crystal is sealed between the substrate glass and 16. The driving semiconductor element 15 is mounted on the substrate glass 11 according to the method described with reference to FIG. 12 is an input wiring pattern for transmitting an input signal to the driving semiconductor element,
The 17 flexible connectors were connected by anisotropic conductive films, soldering, etc., and were connected to external circuits. The output from the driving semiconductor element 15 was guided to the liquid crystal enclosure through the output wiring pattern 13, and a signal for driving the liquid crystal was applied to the liquid crystal.

【0003】[0003]

【発明が解決しようとする課題】しかし、従来の半導体
装置の構造では、図3で示されるように、半導体素子の
出力配線パターンすなわち装置内部の配線パターンと半
導体素子をはさんで基板端面側に入力配線パターンすな
わち装置外部との配線パターンを有するような構造にな
っているために、基板端面と半導体素子の距離7が必然
的に長くなってしまうという問題点を有していた。一般
に基板は、例えば液晶表示装置であれば液晶表示部、イ
メージセンサーであれば、フォトダイオード及び駆動回
路等、その装置にとって必要不可決な部分をできる限り
大きくし、実装部等はできる限り小さくし、基板からの
装置の取り効率を上げようとするため、できるだけ基板
端面と半導体素子の距離7のようなスペースは削除する
設計が行われる。そのため、従来の半導体装置の構造で
は基板からの装置の取り効率が悪いという問題点を有し
ていたのである。
However, in the structure of the conventional semiconductor device, as shown in FIG. 3, the output wiring pattern of the semiconductor element, that is, the wiring pattern inside the device and the semiconductor element are sandwiched between the semiconductor element and the end face of the substrate. Since the structure has an input wiring pattern, that is, a wiring pattern to the outside of the device, there is a problem that the distance 7 between the substrate end face and the semiconductor element is necessarily long. In general, the substrate should be as large as possible, such as a liquid crystal display part for a liquid crystal display device, and a photodiode and a drive circuit for an image sensor, and the mounting parts and the like should be as small as possible. In order to increase the efficiency of removing the device from the substrate, a design is made to eliminate as much as possible a space such as the distance 7 between the substrate end face and the semiconductor element. Therefore, the conventional semiconductor device has a problem that the efficiency of removing the device from the substrate is low.

【0004】そこで、本発明では前述のような問題点を
解決するために、基板端面と半導体素子の距離7をでき
る限り小さくし、基板からの装置の取り効率をできるだ
け高めるような半導体装置の構造を提供することを目的
としている。
Therefore, in order to solve the above-mentioned problems, the present invention reduces the distance 7 between the end face of the substrate and the semiconductor element as much as possible, and increases the efficiency of removing the device from the substrate as much as possible. It is intended to provide.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
複数の半導体素子が基板上に形成されてなり、前記各半
導体素子に形成されてなる電極と電気的に接続してなる
入力配線パターンと、前記各半導体素子に形成されてな
る電極と電気的に接続してなる出力配線パターンとが前
記基板上に形成されてなる半導体装置において、前記入
力配線パターンは線幅が徐々に広くなるピッチ変換部を
有し、前記半導体素子の間に前記ピッチ変換部が配置さ
れるように形成されてなり、 前記複数の半導体素子の
うち第1の半導体素子と第2の半導体素子の間の領域
に、前記第1の半導体素子に接続してなる前記入力配線
パターンと前記第2の半導体素子に接続してなる前記出
力配線パターンが隣接して形成されてなることを特徴と
する。また、前記入力配線パターンのピッチよりも前記
出力配線パターンのピッチが狭いことを特徴とする。
According to the present invention, there is provided a semiconductor device comprising:
A plurality of semiconductor elements are formed on a substrate, and an input wiring pattern electrically connected to an electrode formed on each of the semiconductor elements; and an input wiring pattern electrically formed on each of the semiconductor elements. In a semiconductor device in which a connected output wiring pattern is formed on the substrate, the input wiring pattern has a pitch conversion section whose line width gradually increases, and the pitch conversion section is provided between the semiconductor elements. The input wiring pattern connected to the first semiconductor element is provided in a region between a first semiconductor element and a second semiconductor element among the plurality of semiconductor elements. And the output wiring pattern connected to the second semiconductor element is formed adjacently. Further, the pitch of the output wiring pattern is narrower than the pitch of the input wiring pattern.

【0006】[0006]

【作用】本発明では、フェースダウン実装されている半
導体素子から外部へ引き出される配線パターンを半導体
素子の側面から多く引き出す構造としたので、半導体素
子の電極ピッチを、外部との接続が容易に得られるよう
に配線パターンのピッチを拡大する部分が半導体素子と
基板端ぶの間ではなく、半導体素子の側方を用いること
ができるため、半導体素子と基板端部の距離が短くなる
という作用を有する。
According to the present invention, the wiring pattern extending from the face-down mounted semiconductor element to the outside is drawn out from the side of the semiconductor element, so that the electrode pitch of the semiconductor element can be easily obtained. Since the portion where the pitch of the wiring pattern is enlarged can be used not between the semiconductor element and the edge of the substrate but on the side of the semiconductor element, the distance between the semiconductor element and the edge of the substrate is shortened. .

【0007】[0007]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

【0008】[0008]

【実施例】以下に、本発明を実施例に基づき、詳細に説
明する。図1は、本発明による半導体装置の構造を基板
側から見た図である。1は基板であり、少なくとも表面
が絶縁された、金属、ガラス、セラミックス等が用いら
れることが多い。図1では、ガラス等の透明基板を用い
た例で説明する。基板上には、半導体素子5を基板外部
と接続するための装置外部との配線パターン2と、基板
上に形成された回路との接続を行うための装置内部の配
線パターン3とが形成されている。これらの配線パター
ンは、通常、Cr,Ni,Ta等の金属やITO等の金属
酸化物をフォトパターニングして形成するか、導電イン
クを印刷して形成することが多い。装置内部の配線パタ
ーン3のピッチは、基板1上に形成される回路のピッチ
が、半導体素子5上に形成されている金属突起4のピッチ
と同程度か、それ以下であるため、パターン設計上素直
に引きまわせば良いため問題無いが、装置外部との接続
は、通常、金属突起4のピッチより広くなければ、接続
しにくく、かつ半導体素子に供給する電源等は低インピ
ーダンスを求められることが多いため、装置外部との配
線パターン2はできる限り幅広く設計することが多い。
装置外部との配線パターン4は半導体素子5の側面方向へ
引き出されており、こうすることで、配線パターンのピ
ッチの拡大および低インピーダンス化すなわちパターン
の幅広化を行っているのである。当然、半導体素子5の
外部接続用金属突起も装置外部との配線パターン2に相
対する位観に形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments. FIG. 1 is a view of a structure of a semiconductor device according to the present invention as viewed from a substrate side. Reference numeral 1 denotes a substrate, which is often made of metal, glass, ceramic, or the like, at least having an insulated surface. FIG. 1 illustrates an example using a transparent substrate such as glass. On the substrate, a wiring pattern 2 for connecting the semiconductor element 5 to the outside of the substrate and a wiring pattern 3 for connecting the circuit formed on the substrate to the outside of the device are formed. I have. These wiring patterns are usually formed by photo-patterning a metal such as Cr, Ni, or Ta, or a metal oxide such as ITO, or by printing a conductive ink in many cases. The pitch of the wiring pattern 3 inside the device is similar to or less than the pitch of the metal protrusions 4 formed on the semiconductor element 5 because of the circuit pitch formed on the substrate 1. There is no problem because it can be pulled straight, but connection to the outside of the device is usually difficult to connect unless it is wider than the pitch of the metal protrusions 4, and low impedance is required for the power supply etc. supplied to the semiconductor element Therefore, the wiring pattern 2 to the outside of the device is often designed as wide as possible.
Wiring pattern 4 of the device outside is drawn into the side surface direction of the semiconductor element 5, by doing so, we're doing broadening of expansion and low impedance or pattern pitch of the wiring pattern. Naturally, the external connection metal projection of the semiconductor element 5 is also formed in a position facing the wiring pattern 2 to the outside of the device.

【0009】通常、半導体素子の側向は何も形成されな
いムダなスペースであることが多いので、ここに装置外
部との接続場所を形成することになる。こうすることに
よって、6の基板端面と、半導体素子5との距離7は、半
導体素子5の基板端面6側に装置外部との接続場所を設け
る方式に比較して、基板端面と半導体素子の距離7を充
分に短くすることができるのである。図1では、4本の装
置外部との配線パターンを示したが、その数はもちろん
半導体素子、半導体装置によっても異なるし、パターン
の引き出しも、図のように半導体素子の側面方向を中心
に行えばよく、四角、及び一部は半導体素子と基板端面
とを結ぶ領域に存在してもかまわない。要は、いかに、
半導体素子側面のムダなスペースを装置外部との接続パ
ターンの引きまわしに用いれるかを考えた設計を行えば
良いのである。このように、半導体素子と基板端面との
距離を短くしたことで、基板寸法を小さくでき、基板の
原板からの取り効率が向上するので、基板のコストを低
下させることができる。これは、基板の面積当たりのコ
ストが高いアクティブマトリクス液晶パネル基板、イメ
ージセンサー用基板等において著しい効果がある。さら
に、基板性能に関係のない部分が小さくでき、基板を用
いた製品の商品価値を高めることができる。液晶パネル
等では、額縁と呼ばれる部位に相当し、ここを小さくで
きるので商品価値が高まる。半導体素子5は、8の絶縁樹
脂によって基板1と接着しているのであるが、さらにこ
の様子をわかりやすくするために、図1のA−A′断面図
を図4に示す。図4中で、5は半導体素子を示し、その電
極9上に、例えばCr−Cu,Ti−Pd等の金属を被
着した後、金属突起4を形成する。金属突起4は、Au,
Cu,ハンダ等の金属であり、電気メッキ,スパッタ等
で形成されることが多い。電極9は、半導体素子に供給
する電源、入力信号、あるいは出力信号を半導体素子外
部へ取り出す接続部である。4の金属突起が、基板1上の
装置外部との配線パターン2及び装置内部の配線パター
ン3に、絶縁樹脂8の接着力で押しつけられている。ここ
では、接着剤による半導体素子のフリップチップ実装に
ついての例で説明したが、従来から行われているハンダ
バンプによる共晶接続法や、金属突起の代替物質を印刷
等で形成する方法でもかまわない。
Usually, the side of the semiconductor element is often a wasteful space in which nothing is formed, and a connection place with the outside of the device is formed here. By doing so, the distance 7 between the substrate end face 6 and the semiconductor element 5 is smaller than the distance between the substrate end face and the semiconductor element as compared with the method of providing a connection place with the outside of the device on the substrate end face 6 side of the semiconductor element 5. 7 can be made sufficiently short. In FIG. 1, four wiring patterns with the outside of the device are shown, but the number differs depending on the semiconductor element and the semiconductor device, and the pattern is drawn out centering on the lateral direction of the semiconductor element as shown in the figure. For example, the square and a part thereof may exist in a region connecting the semiconductor element and the end face of the substrate. The point is, how
The design should be made in consideration of whether a wasteful space on the side surface of the semiconductor element is used for routing the connection pattern with the outside of the device. As described above, by reducing the distance between the semiconductor element and the end face of the substrate, the dimensions of the substrate can be reduced, and the efficiency of removing the substrate from the original plate can be improved, so that the cost of the substrate can be reduced. This has a remarkable effect in an active matrix liquid crystal panel substrate, an image sensor substrate, or the like, which has a high cost per substrate area. Further, a portion irrelevant to the substrate performance can be reduced, and the commercial value of a product using the substrate can be increased. In a liquid crystal panel or the like, it corresponds to a part called a picture frame, which can be made smaller, thereby increasing its commercial value. The semiconductor element 5 is bonded to the substrate 1 by the insulating resin 8. To further illustrate this state, FIG. 4 is a cross-sectional view taken along the line AA ′ of FIG. In FIG. 4, reference numeral 5 denotes a semiconductor element, on which a metal such as Cr—Cu or Ti—Pd is deposited on an electrode 9 and then a metal projection 4 is formed. The metal projection 4 is made of Au,
It is a metal such as Cu or solder, and is often formed by electroplating, sputtering, or the like. The electrode 9 is a connection part for taking out a power supply, an input signal, or an output signal supplied to the semiconductor element to outside the semiconductor element. The metal projection 4 is pressed against the wiring pattern 2 with the outside of the device and the wiring pattern 3 inside the device on the substrate 1 by the adhesive force of the insulating resin 8. Here, an example of flip-chip mounting of a semiconductor element using an adhesive has been described, but a conventional eutectic connection method using solder bumps or a method of forming a substitute material for metal projections by printing or the like may be used.

【0010】さらに、本発明の半導体装置の構造を液晶
パネルに応用した例を図5に示す。11は基板ガラスであ
り、前述の基板に相等し、16の対向ガラスとの間に液晶
が封入されている。11の基板ガラス上には図1で説明し
たような方式に従ってパネルの駆動用半導体素子15が実
装されている。12は駆動用半導体素子へ入力信号を送出
するための入力配線パターンであり、13は駆動用半導体
素子からの出力をパネルに出力するための出力配線バタ
ーンであり、それぞれ、装置外部との配線パターン2及
び装置内部の配線パターン3に相等する。入力配線パタ
ーンは図示されるように、駆動用半導体素子間の空スペ
ースで接続ピッチを拡大し、17のフレキシブルコネクタ
ーと異方性導電膜で実装,接続される。これは、何もフ
レキシブルコネクターを用いなくとも、ハンダ付け,ワ
イヤーボンディング等既知の実装手段を用いても良い。
FIG. 5 shows an example in which the structure of the semiconductor device of the present invention is applied to a liquid crystal panel. Reference numeral 11 denotes a substrate glass, which is equivalent to the above-described substrate, and has liquid crystal sealed between the glass and the opposite glass 16. A panel driving semiconductor element 15 is mounted on the substrate glass 11 according to the method described with reference to FIG. Reference numeral 12 denotes an input wiring pattern for transmitting an input signal to the driving semiconductor element, and reference numeral 13 denotes an output wiring pattern for outputting an output from the driving semiconductor element to a panel. 2 and the wiring pattern 3 inside the device. As shown in the figure, the connection pitch of the input wiring pattern is increased by an empty space between the driving semiconductor elements, and the input wiring pattern is mounted and connected to 17 flexible connectors and an anisotropic conductive film. For this, known mounting means such as soldering and wire bonding may be used without using any flexible connector.

【0011】[0011]

【発明の効果】以上説明したように、本発明の半導体装
置の構造では、半導体素子がフェースダウン実装されて
いる基板上で半導体素子の基板端面側の側面側から多く
の装置外部との配線パターンを引き出し、そこで、装置
外部との接続をとるようにしたので以下の効果を有す
る。
As described above, in the structure of the semiconductor device according to the present invention, a large number of wiring patterns from the side of the semiconductor element end face to the outside of the device are mounted on the substrate on which the semiconductor element is mounted face down. Is brought out, and the connection with the outside of the apparatus is taken. Therefore, the following effects are obtained.

【0012】(1)半導体素子と基板端面との距離を小
さくすることができるため、基板寸法を小さくでき、基
板の原板からの取り効率が向上するので、基板のコスト
を低下させることができる。
(1) Since the distance between the semiconductor element and the end face of the substrate can be reduced, the dimensions of the substrate can be reduced, and the efficiency of removing the substrate from the original plate can be improved, so that the cost of the substrate can be reduced.

【0013】(2)特に、外部配線パターンのピッチ変
換部を隣り合う半導体素子間に配置したことで、ピッチ
変換部の長さ分は吸収され、半導体素子と基板端面との
実質的な直線距離は短くなるため、小型化に大いに寄与
できることになる。
(2) In particular, since the pitch converter of the external wiring pattern is arranged between adjacent semiconductor elements, the length of the pitch converter is absorbed, and the substantial linear distance between the semiconductor element and the end face of the substrate is obtained. Is shortened, which can greatly contribute to miniaturization.

【0014】(3)基板寸法が小さくなるにともなっ
て、基板性能に関係のない部分が小さくなるので、基板
を用いた製品の商品価値を高めることができる。
(3) As the size of the substrate becomes smaller, a portion not related to the performance of the substrate becomes smaller, so that the commercial value of a product using the substrate can be increased.

【0015】(4)基板寸法が小さくなるため、製品の
重量を減らすことができる。
(4) Since the substrate size is reduced, the weight of the product can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体装置の構造を、基板裏面よ
り見た平面図である。
FIG. 1 is a plan view of the structure of a semiconductor device according to the present invention as viewed from the back surface of a substrate.

【図2】従来の半導体装置の構造を基板裏面より見た平
面図である。
FIG. 2 is a plan view of the structure of a conventional semiconductor device as viewed from the back surface of a substrate.

【図3】従来の半導体装置の構造を示す斜視図である。FIG. 3 is a perspective view showing a structure of a conventional semiconductor device.

【図4】本発明による半導体装置の構造を示す断面図で
ある。
FIG. 4 is a sectional view showing a structure of a semiconductor device according to the present invention.

【図5】本発明による半導体装置の構造を示す斜視図で
ある。
FIG. 5 is a perspective view showing a structure of a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1………基 板 2………装置外部との配線パターン 3………装置内部の配線パターン 4………金属突起 5………半導体素子 6………基板端面 7………基板端面と半導体素子の距離 8………絶縁樹脂 9………電 極 11………基板ガラス 12………入力配線パターン 13………出力配線パターン 15………駆動用半導体素子 16………対向ガラス 17………フレキシブルコネクター 1 …………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Board edge 7 Distance of semiconductor element 8 Insulating resin 9 Electrode 11 Substrate glass 12 Input wiring pattern 13 Output wiring pattern 15 Driving semiconductor element 16 Opposing glass 17 ……… Flexible connector

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】複数の半導体素子が基板上に形成されてな
り、 前記各半導体素子に形成されてなる電極と電気的に接続
してなる入力配線パターンと、前記各半導体素子に形成
されてなる電極と電気的に接続してなる出力配線パター
ンとが前記基板上に形成されてなる半導体装置におい
て、 前記入力配線パターンは線幅が徐々に広くなるピッチ変
換部を有し、前記半導体素子の間に前記ピッチ変換部が
配置されるように形成されてなり、 前記複数の半導体素子のうち第1の半導体素子と第2の
半導体素子の間の領域に、前記第1の半導体素子に接続
してなる前記入力配線パターンと前記第2の半導体素子
に接続してなる前記出力配線パターンが隣接して形成さ
れてなることを特徴とする半導体装置。
A plurality of semiconductor elements formed on a substrate; an input wiring pattern electrically connected to electrodes formed on each of the semiconductor elements; and an input wiring pattern formed on each of the semiconductor elements. In a semiconductor device in which an output wiring pattern electrically connected to an electrode is formed on the substrate, the input wiring pattern has a pitch conversion portion in which a line width is gradually increased. The pitch converter is formed so as to be disposed in a region between the first semiconductor element and the second semiconductor element of the plurality of semiconductor elements, and is connected to the first semiconductor element. Wherein the input wiring pattern and the output wiring pattern connected to the second semiconductor element are formed adjacent to each other.
【請求項2】 前記入力配線パターンのピッチより前記
出力配線パターンのピッチが狭いことを特徴とする請求
項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a pitch of said output wiring pattern is smaller than a pitch of said input wiring pattern.
JP25310698A 1998-09-07 1998-09-07 Semiconductor device Expired - Lifetime JP3058151B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25310698A JP3058151B2 (en) 1998-09-07 1998-09-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25310698A JP3058151B2 (en) 1998-09-07 1998-09-07 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP1705190A Division JP2864612B2 (en) 1990-01-26 1990-01-26 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2000002576A Division JP3241030B2 (en) 2000-01-11 2000-01-11 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH11163497A JPH11163497A (en) 1999-06-18
JP3058151B2 true JP3058151B2 (en) 2000-07-04

Family

ID=17246589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25310698A Expired - Lifetime JP3058151B2 (en) 1998-09-07 1998-09-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3058151B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518663B1 (en) * 1999-08-30 2003-02-11 Texas Instruments Incorporated Constant impedance routing for high performance integrated circuit packaging

Also Published As

Publication number Publication date
JPH11163497A (en) 1999-06-18

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