JP3057712B2 - Method for manufacturing crystalline silicon substrate - Google Patents

Method for manufacturing crystalline silicon substrate

Info

Publication number
JP3057712B2
JP3057712B2 JP2143909A JP14390990A JP3057712B2 JP 3057712 B2 JP3057712 B2 JP 3057712B2 JP 2143909 A JP2143909 A JP 2143909A JP 14390990 A JP14390990 A JP 14390990A JP 3057712 B2 JP3057712 B2 JP 3057712B2
Authority
JP
Japan
Prior art keywords
crystalline silicon
thin film
small holes
glass substrate
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2143909A
Other languages
Japanese (ja)
Other versions
JPH0437118A (en
Inventor
龍一 川瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP2143909A priority Critical patent/JP3057712B2/en
Publication of JPH0437118A publication Critical patent/JPH0437118A/en
Application granted granted Critical
Publication of JP3057712B2 publication Critical patent/JP3057712B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ガラス基板上に化学気相成長法を用いて、
結晶シリコン薄膜を形成した結晶シリコン基板に係わ
り、さらに言えば、液晶テレビや投写型テレビやプリン
タ、イメージスキャナ等に用いられる薄膜トランジスタ
アレイの製造に利用される結晶シリコン基板及びその製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention uses a chemical vapor deposition method on a glass substrate,
The present invention relates to a crystalline silicon substrate on which a crystalline silicon thin film is formed, and more particularly, to a crystalline silicon substrate used for manufacturing a thin film transistor array used for a liquid crystal television, a projection television, a printer, an image scanner, and the like, and a method for producing the same. .

〔従来技術とその課題〕[Conventional technology and its problems]

化学気相成長法には、常圧化学気相成長法、減圧化学
気相成長法(以下、減圧CVD法という)、プラズマ化学
気相成長法(以下、プラズマCVD法という)等がある
が、多結晶シリコン薄膜あるいは微結晶シリコン薄膜等
の結晶シリコン薄膜をガラス基板に形成するには、たと
えば減圧CVD法を用いて、基板温度を500〜700℃程度と
して作製する方法が用いられている。また、プラズマCV
D法を用いて、シラン(SiH4)のようなシリコン原子を
含む原料を水素のような希釈ガスで高希釈し、高入力電
力で成膜するような方法が知られている。
Chemical vapor deposition methods include atmospheric pressure chemical vapor deposition, reduced pressure chemical vapor deposition (hereinafter referred to as low pressure CVD), plasma chemical vapor deposition (hereinafter referred to as plasma CVD), and the like. In order to form a crystalline silicon thin film such as a polycrystalline silicon thin film or a microcrystalline silicon thin film on a glass substrate, for example, a method in which a substrate temperature is set to about 500 to 700 ° C. by using a low pressure CVD method is used. Also, plasma CV
There is known a method in which a raw material containing silicon atoms such as silane (SiH 4 ) is highly diluted with a diluent gas such as hydrogen using the D method, and a film is formed with a high input power.

しかし、いずれも結晶粒径が小さく、たとえば薄膜ト
ランジスタの半導体として用いて電界効果移動度が100c
m2/V・S以上のトランジスタの作製は困難であった。
However, each has a small crystal grain size and, for example, has a field effect mobility of 100 c when used as a semiconductor of a thin film transistor.
It was difficult to fabricate a transistor having m 2 / V · S or more.

そこで固相成長を用いたり、レーザアニールを行い、
結晶シリコン薄膜の結晶粒径を拡大してトランジスタの
特性を向上させている。しかし固相成長は500〜700℃と
いう高温で、10〜20時間という長時間の焼成を必要と
し、またレーザアニールも同様に長時間の処理を必要と
するので工場の生産性、およびコストの面で問題が多
い。
Therefore, using solid phase growth or performing laser annealing,
The crystal grain size of the crystalline silicon thin film is enlarged to improve the characteristics of the transistor. However, solid phase growth requires a high temperature of 500 to 700 ° C and requires a long firing time of 10 to 20 hours, and laser annealing also requires a long time treatment. There are many problems.

〔課題を解決するための手段〕[Means for solving the problem]

本発明は、ガラス基板の一面にレジストを塗布し、小
孔形状をパターニングした後、ガラス基板をエッチング
することにより、均一に小孔を形成し、かつ該小孔内の
みにシリコン単結晶微粒子を分布させ、その後に化学気
相成長法により、小孔内にシリコン単結晶微粒子が分布
した面上に、結晶シリコン薄膜を形成する結晶シリコン
基板の製造方法によりなされる。
In the present invention, a resist is applied to one surface of a glass substrate, and after patterning the shape of the small holes, the glass substrate is etched to form small holes uniformly, and silicon single crystal fine particles are formed only in the small holes. This is performed by a method of manufacturing a crystalline silicon substrate by forming a crystalline silicon thin film on a surface where silicon single crystal fine particles are distributed in small holes by a chemical vapor deposition method.

また、化学気相成長法においてグロー放電法を用いる
と、プラズマにより原料の分解と表面反応を促進し、結
晶シリコン薄膜の結晶化を促進する効果がある。
Further, when the glow discharge method is used in the chemical vapor deposition method, the decomposition of the raw material and the surface reaction are promoted by the plasma, and the crystallization of the crystalline silicon thin film is promoted.

〔作用〕[Action]

本発明の機構は定かではないが、ガラス基板上の小孔
内のシリコン単結晶微粒子が、ガラス基板上に化学気相
堆積法により堆積するシリコン薄膜の結晶成長の核とな
り、低温で結晶粒径の大きな結晶シリコン薄膜が比較的
簡単に形成されると考えられる。
Although the mechanism of the present invention is not clear, the silicon single crystal fine particles in the small holes on the glass substrate serve as nuclei for the crystal growth of the silicon thin film deposited on the glass substrate by the chemical vapor deposition method. Is considered to be relatively easy to form.

また小孔を形成することにより、シリコン単結晶微粒
子を均一にガラス基板上に分布することが可能になり、
形成されるシリコン結晶薄膜の結晶粒を均一化できる。
Also, by forming the small holes, it becomes possible to uniformly distribute the silicon single crystal fine particles on the glass substrate,
Crystal grains of the formed silicon crystal thin film can be made uniform.

〔実施例1〕 以下、本発明について、図面を用いて詳細に説明す
る。
Embodiment 1 Hereinafter, the present invention will be described in detail with reference to the drawings.

ガラス基板1(コーニング社製低膨張ガラスコーニン
グ7059)上に、感光性レジストを塗布し、マスク露光、
現像して0.01〜1.0μm程度の小孔をパターニングし
た。なお、パターニングに用いるレジストは、電子線レ
ジストでもよい。
A photosensitive resist is applied onto a glass substrate 1 (Corning 7059 low-expansion glass Corning), and a mask is exposed.
After development, small holes of about 0.01 to 1.0 μm were patterned. Note that the resist used for patterning may be an electron beam resist.

その後、フッ酸のエッチング液でガラスをエッチング
することにより、小孔5をガラス基板に形成した。小孔
は、ガラス基板に均一に分布させ、小孔間の距離が1.0
〜5.0μmで格子状とした。また、小孔の深さは、0.1〜
1.0μmである。
Thereafter, the small holes 5 were formed in the glass substrate by etching the glass with an etching solution of hydrofluoric acid. The pores are evenly distributed on the glass substrate, and the distance between the pores is 1.0
It was formed into a lattice shape at 5.05.0 μm. In addition, the depth of the small hole is 0.1 to
1.0 μm.

次に、小孔を形成したガラス基板上に0.01〜1.0μm
程度のシリコン単結晶微粒子2を散布し、その後、ガラ
ス基板を布で拭き取り、小孔内にのみシリコン単結晶微
粒子を残すことにより、シリコン単結晶微粒子を均一に
分散させた(第1図参照)。
Next, a 0.01-1.0 μm
The silicon single crystal fine particles 2 were dispersed, and then the glass substrate was wiped off with a cloth to leave the silicon single crystal fine particles only in the small holes, thereby uniformly dispersing the silicon single crystal fine particles (see FIG. 1). .

次にプラズマCVD法によるグロー放電を用い、原料ガ
スをSiH4およびH2とし、低電力密度(0.1〜0.3W/cm2
でH2/SiH4=8/1〜10/1の希釈率とし、基板温度を200〜4
00℃としてシリコン薄膜を堆積すると、粒径が100〜500
Å程度の結晶シリコン薄膜が形成された結晶シリコン基
板を得ることができる(第2図参照)。
Next, low power density (0.1-0.3W / cm 2 ) using glow discharge by plasma CVD method with SiH 4 and H 2 as source gas
In the H 2 / SiH 4 = 8 / 1~10 / 1 dilution ratio, 200-4 substrate temperature
When a silicon thin film is deposited at 00 ° C, the particle size is 100 to 500.
A crystalline silicon substrate having a crystalline silicon thin film of about Å can be obtained (see FIG. 2).

このようにして作製した結晶シリコン基板を用いた薄
膜トランジスタの電界効果移動度は100cm2/V・S以上と
良好な特性を示した。
The field effect mobility of the thin film transistor using the crystalline silicon substrate manufactured as described above was 100 cm 2 / V · S or more, showing good characteristics.

〔実施例2〕 実施例1と同様な、小孔内にシリコン単結晶微粒子を
均一に分布させたガラス基板を、減圧CVD法を用いて、
原料をSiH4とし、基板温度を500〜600℃としてシリコン
薄膜を堆積すると、粒径が300〜1000Åの結晶シリコン
薄膜が形成された結晶シリコン基板を得ることができ
た。
[Example 2] A glass substrate in which silicon single crystal fine particles were uniformly distributed in small holes as in Example 1 was formed using a low-pressure CVD method.
When a silicon thin film was deposited at a substrate temperature of 500 to 600 ° C. using SiH 4 as a raw material, a crystalline silicon substrate on which a crystalline silicon thin film having a grain size of 300 to 1000 ° was formed was obtained.

このようにして作製した結晶シリコン基板を用いた薄
膜トランジスタの電界効果移動度は100cm2/V・S以上と
良好な特性を示した。
The field effect mobility of the thin film transistor using the crystalline silicon substrate manufactured as described above was 100 cm 2 / V · S or more, showing good characteristics.

〔発明の効果〕〔The invention's effect〕

以上に述べたように、本発明は、ガラス基板上に小孔
を形成し、該小孔内のみにシリコン単結晶微粒子を分布
させた後、シリコン薄膜を化学気相成長法で堆積するこ
とにより、低温で比較的簡単に粒径の大きな結晶シリコ
ン薄膜を形成可能であり、従来の固相成長やレーザアニ
ール等の煩雑で長時間の工程を省くことが可能となる。
As described above, the present invention forms small holes on a glass substrate, distributes silicon single crystal fine particles only in the small holes, and then deposits a silicon thin film by chemical vapor deposition. In addition, a crystalline silicon thin film having a large particle size can be formed relatively easily at a low temperature, and a complicated and long process such as conventional solid phase growth and laser annealing can be omitted.

この粒径の大きな結晶シリコン薄膜が形成された結晶
シリコン基板を用いれば、トランジスタ特性の良好な結
晶シリコン薄膜トランジスタアレイの形成が可能であ
り、大面積の薄膜形成も可能なことから、大面積のディ
スプレイや駆動回路を同時に形成したアクティブ・マト
リクス方式のLCDの作製が簡単になり、工場の生産性が
向上し、製品のコストも低減できる。
Using a crystalline silicon substrate on which a crystalline silicon thin film having a large particle size is formed, a crystalline silicon thin film transistor array having excellent transistor characteristics can be formed, and a large area thin film can be formed. This makes it easier to manufacture active matrix LCDs with a driver and a driving circuit formed at the same time, improving factory productivity and reducing product costs.

【図面の簡単な説明】[Brief description of the drawings]

第1図は、小孔内にシリコン単結晶微粒子を分布させた
ガラス基板の一実施例を示す断面図、第2図は、本発明
の結晶シリコン基板の一実施例を示す断面図である。 1……ガラス基板 2……シリコン単結晶微粒子 3……結晶シリコン基板 4……結晶シリコン薄膜 5……小孔
FIG. 1 is a cross-sectional view showing one embodiment of a glass substrate in which silicon single crystal fine particles are distributed in small holes, and FIG. 2 is a cross-sectional view showing one embodiment of a crystalline silicon substrate of the present invention. DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Silicon single crystal fine particle 3 ... Crystal silicon substrate 4 ... Crystal silicon thin film 5 ... Small hole

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ガラス基板の一面にレジストを塗布し、小
孔形状をパターニングした後、ガラス基板をエッチング
することにより、均一に小孔を形成し、かつ該小孔内の
みにシリコン単結晶微粒子を分布させ、その後に化学気
相成長法により、小孔内にシリコン単結晶微粒子が分布
した面上に、結晶シリコン薄膜を形成する結晶シリコン
基板の製造方法。
1. A method of coating a resist on one surface of a glass substrate, patterning the shape of the small holes, etching the glass substrate to uniformly form small holes, and forming silicon single crystal fine particles only in the small holes. And then forming a crystalline silicon thin film on the surface where the silicon single crystal fine particles are distributed in the small holes by a chemical vapor deposition method.
【請求項2】化学気相成長法においてグロー放電を用い
ることを特徴とする請求項(1)記載の結晶シリコン基
板の製造方法。
2. The method according to claim 1, wherein a glow discharge is used in the chemical vapor deposition method.
JP2143909A 1990-06-01 1990-06-01 Method for manufacturing crystalline silicon substrate Expired - Lifetime JP3057712B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2143909A JP3057712B2 (en) 1990-06-01 1990-06-01 Method for manufacturing crystalline silicon substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2143909A JP3057712B2 (en) 1990-06-01 1990-06-01 Method for manufacturing crystalline silicon substrate

Publications (2)

Publication Number Publication Date
JPH0437118A JPH0437118A (en) 1992-02-07
JP3057712B2 true JP3057712B2 (en) 2000-07-04

Family

ID=15349904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2143909A Expired - Lifetime JP3057712B2 (en) 1990-06-01 1990-06-01 Method for manufacturing crystalline silicon substrate

Country Status (1)

Country Link
JP (1) JP3057712B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4655448B2 (en) * 2002-11-08 2011-03-23 セイコーエプソン株式会社 Thin film transistor manufacturing method
US8258025B2 (en) 2009-08-07 2012-09-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing microcrystalline semiconductor film and thin film transistor
US9177761B2 (en) 2009-08-25 2015-11-03 Semiconductor Energy Laboratory Co., Ltd. Plasma CVD apparatus, method for forming microcrystalline semiconductor film and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH0437118A (en) 1992-02-07

Similar Documents

Publication Publication Date Title
US5695819A (en) Method of enhancing step coverage of polysilicon deposits
US4698316A (en) Method of depositing uniformly thick selective epitaxial silicon
JP2004165682A (en) Multi-step cvd method for thin film transistor
KR970006723B1 (en) Formation of polycrystalline silicon thin films with large grain
JPH05136062A (en) Polycrystalline silicon thin film and its low temperature formation method
JP3057712B2 (en) Method for manufacturing crystalline silicon substrate
JP2001274404A (en) Thin-film transistor and method of manufacturing the same
JP3320180B2 (en) Method for manufacturing thin film transistor
JPH05315269A (en) Forming method for thin film
JPH0437120A (en) Crystalline silicon substrate and manufacture thereof
JP3353832B2 (en) Method and apparatus for manufacturing thin film transistor
JPS59213169A (en) Thin film transistor
JP2616918B2 (en) Display device
JP3008455B2 (en) Method for manufacturing crystalline silicon film
JP2795781B2 (en) Method of forming impurity layer
JPH0661198A (en) Manufacture of thin film device
JPH05343685A (en) Manufacture of silicon thin film transistor
KR20050068491A (en) Method for deposition of semiconductor layer
JPH05110088A (en) Manufacture of thin film transistor circuit
JPH0437119A (en) Crystalline silicone substrate and manufacture thereof
JPH05144841A (en) Method of manufacturing thin film transistor
JPH05198504A (en) Silicon thin film and formation thereof
JPH07263342A (en) Manufacture of semiconductor device
JPH04306821A (en) Compound semiconductor crystal growth method
JPS6345465B2 (en)