JP3056152B2 - Frame pulse signal integration circuit of FIP module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pulse signal integration circuit of a FIP module, and more particularly, to each FIP module.
The present invention relates to a frame pulse signal integration circuit of an FIP module that integrates the timing of a frame pulse signal output from a module.

[0002]

2. Description of the Related Art In a FIP module using a fluorescent display tube as a display element, a single FIP module displays a plurality of digits of characters, symbols, and the like. Making it possible. For example, banks are used to display interest rate information and the like. As an example of a conventional FIP module, FIP manufactured by NEC
The module FM256GX16BA-101A will be described.

FIG. 5 is a block diagram showing a schematic configuration of a conventional FIP module. The FIP module shown in FIG. 5 includes a display control unit 2 that controls the entire display of the FIP module, a crystal oscillator 1 that generates a clock signal serving as a basis for the timing of the display control, and a display element of a phosphor that is arranged in a lattice. , A driver 3 for controlling lighting of each display element, and a display memory 4 for storing display data for the fluorescent display tube 5.

Next, the operation of the above-described FIP module will be described. FIG. 6 is a diagram showing connection of signals between FIP modules, and each signal is connected to an external controller (not shown). 5 and 6, a module selection signal MS is a signal for selecting an FIP module to which display data or a command is to be written from a plurality of connected FIP modules, and a data signal DATA is a data or a data to be written to the display control unit 2. The command / data selection signal C / D is a signal for inputting a command. The command / data selection signal C / D is a signal for distinguishing whether a data signal input to the display control unit is a command or data. The frame pulse signal FRP is a signal for instructing writing of data and commands to the control unit, and is a synchronization signal that is periodically output every time display of one screen is completed.

Of the above-mentioned signals, the frame pulse signal F
Signals other than RP are supplied from an external controller to each FIP module and are common to all FIP modules. The frame pulse signal is monitored by an external controller, and is used for smoothly performing scroll display by updating display data in synchronization with the frame pulse signal when performing scroll display or the like.

The frame pulse signal FRP is generated by measuring the pulse width and period using a counter or the like based on the clock signal C1 which is the oscillation output of the crystal oscillator 1 supplied to the display control unit 2, and generates the frame pulse signal FRP. It is output periodically immediately after the power is turned on. FIG. 7 is a time chart showing the output of the frame pulse signal FRP. The pulse width is 80 μS and the period is 10 mS. Immediately after turning on the power of the FIP module, the crystal oscillator 1 of each FIP module
Since the time until the oscillation output of the FIP module becomes stable varies for each crystal oscillator, the output timing of the frame pulse signal FRP of each FIP module is not constant, and FIG.
It varies as shown. FIG. 8 is an explanatory diagram showing how the output timing of the frame pulse signal FRP of each FIP module varies.

[0007] The frame pulse signal output of each FIP module is an open collector output to save signal lines for connection to an external controller, and is wired-ORed to one signal line and output. Therefore, when the external controller controls the scroll display,
The FI selected by the module selection signal MS to identify whether the frame pulse signal is from the IP module.
By writing a frame pulse output command to the P module, a frame pulse signal FRP is output from a desired FIP module.

[0008]

In the prior art described above, a command for selecting a module for outputting a frame pulse signal at the time of scroll display needs to be issued, so that the software processing of the external controller is complicated. There was a problem of becoming.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a frame pulse signal integration circuit of an FIP module which can simplify software processing for scroll display. I do.

[0010]

In order to solve the above-mentioned problems, the present invention provides control means for controlling lighting of a fluorescent display tube, and oscillating means for outputting a pulse signal defining display timing of the fluorescent display tube. And masking means for masking a pulse signal output from the oscillating means for a predetermined time after the fluorescent display tube is turned on and input to the control means. Also, the present invention
The control means counts a pulse signal output from the oscillation means, and outputs a frame pulse signal when a predetermined number is counted. The mask release signal for releasing the mask of the mask means is provided by the fluorescent display tube. It is characterized in that they are commonly input to each .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a frame pulse signal integration circuit of an FIP module according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a frame pulse signal integration circuit of an FIP module according to an embodiment of the present invention. F shown in FIG.
The IP module includes a display control unit 2 that controls the entire display of the FIP module, a crystal oscillator 1 that generates a clock signal serving as a basis for display control timing, and a mask release signal from an external controller (not shown). Masking circuit 6 for masking clock signal input to display control unit 2
And a fluorescent display tube 5 having phosphor display elements arranged in a grid.
A driver 3 for controlling lighting of each display element; and a display memory 4 for storing display data for the fluorescent display tube 5.

Next, the operation of the frame pulse signal integration circuit of the FIP module according to one embodiment of the present invention will be described. FIG. 2 illustrates a FIP according to one embodiment of the present invention.
5 is a time chart illustrating an operation of a mask circuit in a frame pulse signal integration circuit of the module. FIG.
Represents each FIP generated by the frame pulse signal integration circuit of the FIP module according to one embodiment of the present invention.
6 is a time chart illustrating a timing of outputting a frame pulse signal FRP of a module.

First, after the power of the FIP module is turned on, a time sufficient for stabilizing the oscillation output C1 of the crystal oscillator 1 is secured, and then the mask release signal MSK is turned on from an external controller. The mask circuit 6 masks the clock signal C2 input to the display control unit 2 while the mask release signal MSK is off (that is, mask setting), and while the mask release signal MSK is on (that is, mask release). It has a function of inputting the output C1 as a clock signal of the display control unit 2. In this case, the clock signal C2 input to the display control unit 2 is masked while the gate release signal MSK is “0”, and “ Immediately after it becomes 1 ", the mask is released and the clock signal C2 is input to the display control unit 2.

The mask release signal MSK is a signal common to a plurality of connected FIP modules, and a clock signal C2 input to the display controller 2 in each FIP module.
The variation of the input timing is within at least one clock even when the phase difference between the oscillation outputs of the respective crystal oscillators 1 is considered.

Next, the display controller 2 controls the clock signal C2.
To generate a frame pulse signal. In this case, each F
Since the variation between the clock signals C2 input to the display controller 2 of the IP module is within one clock, the frame pulse signal FRP generated by measuring the pulse width and period using a counter or the like based on the clock signal C2. The variation in the output is also within one clock, and as shown in FIG.
Frame pulse signal FR output from IP module
P has almost the same timing.

In this case, the timing variation of one clock corresponds to the oscillation frequency of the crystal oscillator 1 of 16 MHz, for example.
In this case, the pulse width is 62.5 nS, and the pulse width of the frame pulse signal FRP is usually 80 μS and the period is 10 mS. However, since it is a sufficiently small value, the variation is practically acceptable. .

Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 4 is a block diagram showing a frame pulse signal integration circuit of an FIP module according to another embodiment of the present invention. In the present embodiment, FIG.
A clock signal CLK is input from an external controller (clock signal generating means; not shown) instead of the crystal oscillator 1 and the mask circuit 6 therein. The clock signal CLK is applied to each F
A frame pulse signal FRP is generated by the display control unit 2 based on the clock signal CLK as a signal common to the IP modules, and the frame pulse signal FRP can be shared. When the external controller stops outputting the clock signal CLK, the same effect as that of the mask circuit 6 can be obtained.

[0018]

As described above, according to the present invention, by integrating the frame pulse signals of a plurality of connected FIP modules, the output of the frame pulse signal of an arbitrary FIP module can be changed to all the FIP modules. In this case, it is possible to omit a process of issuing a command for selecting an FIP module that outputs a frame pulse when performing control such as scroll display.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a frame pulse signal integration circuit of an FIP module according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation of a mask circuit in a frame pulse signal integration circuit of the FIP module according to one embodiment of the present invention.

FIG. 3 is a time chart showing a timing of outputting a frame pulse signal FRP of each FIP module, which is generated by a frame pulse signal integration circuit of the FIP module according to one embodiment of the present invention.

FIG. 4 is a block diagram showing a frame pulse signal integration circuit of an FIP module according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a conventional FIP module.

FIG. 6 is a diagram showing signal connections between FIP modules.

FIG. 7 is a time chart showing an output of a frame pulse signal FRP.

FIG. 8 shows a frame pulse signal F of each FIP module.
It is explanatory drawing which shows a mode that the output timing of RP varies.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Crystal oscillator (oscillation means) 2 Display control part (control means) 3 Driver (control means) 4 Display memory (control means) 5 Fluorescent display tube 6 Mask circuit (mask means)

Claims (2)

(57) [Claims] 1. A control means for controlling lighting of a fluorescent display tube, an oscillating means for outputting a pulse signal for defining a display timing of the fluorescent display tube, and a predetermined time after a power supply of the fluorescent display tube is turned on, A mask means for masking a pulse signal output from the oscillation means and input to the control means, wherein the frame pulse signal integration circuit of the FIP module is provided. 2. The control means counts a pulse signal output from the oscillating means, and outputs a frame pulse signal when a predetermined number is counted, and a mask release signal for releasing masking of the mask means. 2. The frame pulse signal integration circuit of the FIP module according to claim 1, wherein the signal is input in common to each of said fluorescent display tubes .