JPH10161612A - Multiple image plane liquid crystal display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the peripheral circuits, by supplying a switch panel for making each liquid crsytal display unit supply an image signal to a picture element of the last frame or line, as a starting pulse of an adjacent liquid crystal display unit. SOLUTION: When an H start pulse 34 is input from a shift resistor driving circuit 40, each H shift resistor 18 of a liquid crystal display unit 4 of the first frame successively generates the switch pulses in synchronization with the rise of the H clocks. And the last switch pulse is input to a H input terminal 36 of each liquid crystal display unit 4 of the second frame through a H output terminal 6, and supplied as a H start pulse 34 to the H shift resistor 18. Further when a V start pulse 30 is input from a shift resistor driving circuit 40, each V shift resistor of the liquid crystal display unit 4 of the first line successively generates the switch pulses. And the last pulse is supplied to the V shift resistor 20 of each liquid crystal display unit 4 of the second line, as the V start pulse 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen liquid crystal display device in which a plurality of liquid crystal display devices are arranged adjacent to each other to form a larger screen.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a conventional liquid crystal display device. First, a conventional liquid crystal display device will be described with reference to FIG. The liquid crystal display device 12 shown in FIG. 5 has a large number of pixel elements 16, an H shift register 18 (a first scanner according to the present invention), and a V shift register 20 (a second scanner according to the present invention) on a substrate 14. ),
An H switch element 22, a V switch element 24 and the like are arranged. The pixel elements 16 are arranged in a matrix (only a part is shown in the figure), and
6, and by storing a video signal in the capacitor 26, the optical transmittance of the liquid crystal cell of each pixel element 16 changes to form a video. One terminal of each capacitor 26 is connected to the common electrode 28.

A V-switch element 24 is provided for each pixel element 16. When the V-switch element 24 is turned on, a video signal is supplied to a capacitor 26 of each pixel element 16. Further, the control terminals of the V switch elements 24 are commonly connected to each row, so that the ON / OFF control of the V switch elements 24 of each row is performed collectively. The V shift register 20 supplies switch pulses PV1 to PVp (p is a positive integer) for sequentially turning on the V switch elements 24 for each row to each V switch element 24. The V shift register 20 has a configuration in which a V start pulse 30 (a second start pulse according to the present invention) is externally input through a V input terminal 32. When the V start pulse 30 is input, V The shift register 20 synchronizes with a V clock VCK also supplied from the outside, and sequentially starts at a predetermined time interval from the V switch elements 24 in the first row (the uppermost row in the figure). Are supplied to the V switch element 24.

In the liquid crystal display device 12, video signals are simultaneously supplied to adjacent n columns (n is a positive integer) of pixel elements 16. Therefore, the H switch elements 22 are provided for every n columns,
2 turns on, the video signal V supplied simultaneously from the outside
1 to Vn are supplied to the corresponding n columns of pixel elements 16 through the H switch element 22. ON / OFF of each H switch element 22 is controlled by the H shift register 18.
The H shift register 18 includes switch pulses PH1 to PHm (m) for sequentially turning on the H switch elements 22.
Is supplied to each H switch element 22. An H start pulse 34 (a first start pulse according to the present invention) is externally input to the H shift register 18 through an H input terminal 36. The H start pulse 34
Is input, the H shift register 18 synchronizes with an externally supplied H clock HCK, and outputs the H switch element corresponding to the first n columns (the leftmost n columns in the figure) of the pixel elements 16. 22 and a switch pulse P for sequentially turning on the H switch elements 22 at certain time intervals.
H1 to PHm are supplied to the H switch element 22.

FIG. 6A is a timing chart showing the operation of the H shift register 18, and FIG. 6B is a timing chart showing the operation of the V shift register 20. As shown in this figure, the H shift register 18 outputs the H start pulse 3
When 4 is input, a switch pulse PH1 is generated in synchronization with the next rise of the H clock HCK, and then switch pulses PH2 to PHm are generated one after another in synchronization with the rise of each H clock HCK. On the other hand, when the V start pulse 30 is input, the V shift
The switch pulse PV1 is generated in synchronization with the rise of the clock VCK, and then the switch pulses PV2 to PVp are generated one after another in synchronization with the rise of each V clock VCK. Note that each switch pulse PV1 to PVp is
The high level is maintained while all the H switch elements 22 are turned on. Therefore, a video signal is sequentially written for each pixel element 16 in each row. Further, in each row, the video signal is collectively written for each of the pixel elements 16 in the continuous n columns as described above. In FIG. 6, the scale of the time axis of (A) and the scale of the time axis of (B) are large, and one cycle of the V clock VCK is about m times one cycle of the H clock HCK. It has become.

By arranging a plurality of such liquid crystal display devices 12 adjacently, a multi-screen liquid crystal display device having a larger screen is constructed. FIG. 7 is a block diagram showing an example of a conventional multi-screen liquid crystal display device. The multi-screen liquid crystal display device 38 is configured by arranging the liquid crystal display devices 12 in a matrix of x columns and y rows. And
In order to operate the liquid crystal display device 12 as described above, it is necessary to supply the H start pulse 34 and the V start pulse 30 to each liquid crystal display device 12, and in a multi-screen liquid crystal display device, it differs for each liquid crystal display device 12. Since it is necessary to supply the H start pulse 34 and the V start pulse 30 at appropriate timing, a shift register driving circuit 40 that generates these pulses for each of the x × y liquid crystal display devices 12 has a peripheral circuit. It is provided as.

[0007]

As described above, in the conventional multi-screen liquid crystal display device 38, the shift register driving circuit 40 for supplying the H start pulse 34 and the V start pulse 30 for each liquid crystal display device 12 is provided. Since it is provided as a peripheral circuit, the circuit scale becomes large as a whole, which is disadvantageous in reducing the size and cost of the device.
Further, since the number of man-hours required for the operation is increased by the provision of the shift register drive circuit 40, this is disadvantageous in terms of cost reduction. Therefore, an object of the present invention is to provide a multi-screen liquid crystal display device 38 that realizes a significant reduction in peripheral circuits.

[0008]

According to the present invention, in order to achieve the above object, a plurality of liquid crystal display devices are arranged adjacent to each other, and each liquid crystal display device includes a plurality of pixel elements arranged in a matrix, When a first start pulse is input, a first switch pulse for turning on a switch element for supplying a video signal to the pixel element is sequentially supplied to the switch element for each pixel element in each column of a matrix. When the first scanner and the second start pulse are input,
A multi-screen liquid crystal display, comprising: a second scanner for supplying a second switch pulse for turning on a switch element for supplying a video signal to the pixel element to the switch element for each of the pixel elements in each row of a matrix; In the display device, either one of the first and second scanners is pulsed at a timing close to the first or second switch pulse for supplying a video signal to the pixel element in the last column or row. The pulse generated by the pulse generation circuit is supplied as the first or second start pulse to the first or second scanner of an adjacent liquid crystal display device. , Characterized in that.

According to the present invention, a plurality of liquid crystal display devices are arranged adjacent to each other. When each of the liquid crystal display devices receives a plurality of pixel elements arranged in a matrix and a first start pulse, A first scanner for supplying a first switch pulse to the switch element for sequentially turning on a switch element for supplying a video signal to the pixel element for each pixel element in each column of a matrix, and a second start A second scanner for supplying a second switch pulse to the switch element for sequentially turning on a switch element for supplying a video signal to the pixel element for each pixel element in each row of a matrix when a pulse is input; Wherein the first scanner includes a first switch pulse for supplying a video signal to the pixel elements in a last column. A first pulse generation circuit for generating a pulse at a contact timing, wherein the pulse generated by the first pulse generation circuit generates the first start signal with respect to the first scanner of an adjacent liquid crystal display device. Supplied as a pulse, the second scanner includes a second pulse generation circuit that generates the pulse at a timing close to the second switch pulse for supplying a video signal to the pixel element in the last row. Wherein the pulse generated by the second pulse generation circuit is supplied as the second start pulse to the second scanner of an adjacent liquid crystal display device.

In the present invention, the pulse generating circuit generates a pulse at a timing close to the first or second switch pulse for supplying a video signal to the last pixel element in the column or row, The pulse generated by the generation circuit is supplied as a first or second start pulse to a first or second scanner of an adjacent liquid crystal display device. Further, in the present invention, the first pulse generating circuit of the first scanner generates a pulse at a timing close to the first switch pulse for supplying a video signal to the pixel element in the last column. A pulse generated by one pulse generation circuit is supplied to a first scanner of an adjacent liquid crystal display device as a first start pulse. Then, the second pulse generation circuit of the second scanner generates a pulse at a timing close to the second switch pulse for supplying a video signal to the pixel element in the last row, and generates the second pulse. The pulse generated by the circuit is supplied as a second start pulse to a second scanner of an adjacent liquid crystal display device. Therefore, in the present invention, it is not necessary to provide a peripheral circuit for generating the first start pulse and the second start pulse for each liquid crystal display device, so that the device can be reduced in size and cost, and furthermore, can be arbitrarily selected. A multi-screen liquid crystal display device having the above screen size can be easily configured.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a block diagram showing an example of a multi-screen liquid crystal display device according to the present invention, and FIG. 2 is a circuit diagram showing a liquid crystal display device constituting the multi-screen liquid crystal display device of FIG. The liquid crystal display device shown in FIG. 2 has almost the same configuration as the liquid crystal display device shown in FIG. 5, and the same components as those in FIG.
The description of them is omitted here. This multi-screen liquid crystal display device 2 has x × y (x and y are both positive integers)
Are arranged in a matrix of x columns and y rows. In this multi-screen liquid crystal display device 2, one shift register drive circuit 40 is provided as a peripheral circuit, and generates an H start pulse 34 and a V start pulse 30. Then, the H start pulse 34 is supplied to each liquid crystal display device 4 arranged at the position of the first column of each row of the liquid crystal display device 4 (the leftmost column in FIG. 1). The signal is input to the H shift register 18 through a terminal 36. On the other hand, the V pulse is supplied to each liquid crystal display device 4 arranged at the position of the first row of each column of the liquid crystal display device 4 (the uppermost position in FIG. 1), and the V input terminal of the liquid crystal display device 4 The signal is input to the V shift register 20 through 32.

In each liquid crystal display device 4, the last switch pulse PHm output from the H shift register 18 is output to the outside through the H output terminal 6, and the last switch pulse PVp output from the V shift register 20 is VV. It is output to the outside through the output terminal 8. The liquid crystal display device 4 is different from the liquid crystal display device of FIG. 5 in that the H output terminal 6 and the V output terminal 8 are provided.
Then, as shown in FIG. 1, in each row of the matrix of the liquid crystal display device 4, the H input terminals 36 of the second and subsequent liquid crystal display devices 4 are connected to the H output terminals 6 of the liquid crystal display device 4 adjacent to the left side, respectively. Have been. In each column of the liquid crystal display device 4, the V input terminal 32 of the second or subsequent liquid crystal display device 4 is connected to the V output terminal 8 of the liquid crystal display device 4 adjacent above.

Next, the operation will be described. FIG. 3 is a timing chart showing the operation of the H shift register 18, and FIG. 4 is a timing chart showing the operation of the V shift register 20. First, the operation of the H shift register 18 will be described. As shown in FIG. 3, when the H start pulse 34 is input from the shift register driving circuit 40, each H shift register 18 of the liquid crystal display device 4 in the first column causes the next H clock HCK.
, A switch pulse PH1 is generated in synchronization with the rising edge of each of the H clocks HCK, and then switch pulses PH2 to PHm are generated one after another in synchronization with the rising edge of each H clock HCK. When the last switch pulse PHm is output from each H shift register 18, this switch pulse PHm
Is input to the H input terminal 36 of each liquid crystal display device 4 in the second column through the H output terminal 6 of each liquid crystal display device 4, and the H shift register 18 of each liquid crystal display device 4 in the second column starts H. It is supplied as a pulse 34.

The H shift register 18 of each liquid crystal display device 4 in the second column outputs the H start pulse 34 (switch pulse P
Hm) is input, H of each liquid crystal display device 4 in the first column is input.
Similarly to the shift register 18, a switch pulse PH1 is generated in synchronization with the next rising of the H clock HCK,
Thereafter, switch pulses PH2 to PHm are generated one after another in synchronization with the rise of each H clock HCK. The last switch pulse PHm is, as in the case described above, the H shift register 18 of each liquid crystal display device 4 in the third column.
Is supplied as an H start pulse 34, and thereafter, the H start pulse 34 is sequentially supplied to the liquid crystal display devices 4 in the fourth and subsequent columns sequentially from the H shift register 18 of the immediately preceding liquid crystal.

Next, the operation of the V shift register 20 will be described. As shown in FIG. 4, the shift register driving circuit 40
, The V shift register 20 of the liquid crystal display device 4 in the first row switches the switch pulse PV1 in synchronization with the rise of the next V clock VCK.
After that, switch pulses PV2 to PVp are generated one after another in synchronization with the rise of each V clock VCK. The scale of the time axis in FIG. 3 is greatly different from the scale of the time axis in FIG. 4, and one cycle of the V clock VCK is about m times as large as one cycle of the H clock HCK. When the last switch pulse PVp is output from each V shift register 20, this switch pulse PVp is applied to the V input terminal of each liquid crystal display device 4 in the second row through the V output terminal 8 of each liquid crystal display device 4. 32, and supplied as a V start pulse 30 to the V shift register 20 of each liquid crystal display device 4 in the second row.

The V shift register 20 of each liquid crystal display device 4 in the second row uses the V start pulse 30 (switch pulse P
When Vp) is input, the V of each liquid crystal display device 4 in the first row is
Similarly to the shift register 20, a switch pulse PV1 is generated in synchronization with the next rising of the V clock VCK,
Thereafter, switch pulses PV2 to PVp are generated one after another in synchronization with the rise of each V clock VCK. Then, the last switch pulse PVp is applied to the V shift register 20 of each liquid crystal display device 4 in the third row, as in the case described above.
The V start pulse 30 is supplied to the liquid crystal display devices 4 in the fourth and subsequent rows similarly from the V shift register 20 of the immediately preceding liquid crystal.

That is, the multi-screen liquid crystal display device 2
In the first embodiment, the H start pulse 34 and the V start pulse 30 are supplied from the shift register drive circuit 40 to the liquid crystal display devices 4 in the first column and the first row. The H shift register 18 is supplied with the H start pulse 34 from the liquid crystal display device 4 in the immediately preceding column, and similarly, the V shift register 20 of the liquid crystal display device 4 in each of the second and subsequent rows is immediately forwarded. The V start pulse 30 is supplied from the liquid crystal display device 4 in the row. Therefore, in the multi-screen liquid crystal display device 2, one shift register driving circuit 40
It is not necessary to provide the shift register drive circuit 40 for each liquid crystal display device 4 as in the related art. Therefore, miniaturization and cost reduction of the device can be realized, and a multi-screen liquid crystal display device having an arbitrary screen size can be easily configured.

In this embodiment, the H-shift register 18 and the V-shift register 20 output the last switch pulse as the H start pulse 34 and the V start pulse 3
Since it is used as 0, in this case, the last shift stage of each of the H shift register 18 and the V shift register 20 functions as the first and second pulse generation circuits of the present invention. In the above embodiment, the H shift register 18 and the V shift register 20 receive the first switch pulse at the next H clock HCK and V clock VCK, respectively, when the H start pulse 34 and the V start pulse 30 are input. , But some shift registers generate the first pulse as soon as the start pulse is input. In such a case, a shift register longer by one stage is used as the H shift register 18 and the V shift register 20, and an additional shift stage (in the present invention) is delayed by one clock after the last switch pulse. A pulse may be output from the first and second pulse generation circuits concerned), and the pulse may be supplied to the next liquid crystal display device 4 as an H start pulse 34 and a V start pulse 30.

In addition to the addition of the shift stage to the shift register as described above, a timing circuit (first and second pulse generation circuits according to the present invention) is provided to adjust the timing, and the subsequent liquid crystal display is adjusted. The H start pulse 34 and the V start pulse 30 may be supplied to the device at an appropriate timing. In the above embodiment, each switch pulse is generated by the shift register. However, the switch pulse generated at the timing as described above can be generated not only by the shift register but also by various timing circuits. In the above embodiment, the video signal is simultaneously written to the pixel elements 16 in n columns. However, the present invention is of course applicable to the liquid crystal display device 4 of a type in which the video signal is sequentially written for each pixel element 16 in one column. It is possible.

In the above embodiment, the liquid crystal display devices 4 are arranged in a plurality of rows and columns. However, the plurality of liquid crystal display devices 4 are arranged horizontally or vertically, for example, horizontally or vertically. It is also possible to configure the screen described above, and even in such a case, the above effects can be obtained by applying the present invention. However, in such a configuration, the liquid crystal display device 4 adjacent to only one of the H shift register 18 and the V shift register 20 outputs the H start pulse 3
A 4 or V start pulse 30 will be provided. In this case, for example, the last shift paragraph number of one of the shift registers functions as the pulse generation circuit of the present invention.

[0021]

As described above, according to the present invention, in the pulse generation circuit, the pulse generation circuit is provided at a timing close to the first or second switch pulse for supplying a video signal to the last pixel element in the column or row. A pulse is generated, and the pulse generated by the pulse generation circuit is supplied as a first or second start pulse to a first or second scanner of an adjacent liquid crystal display device. Further, in the present invention, the first pulse generating circuit of the first scanner generates a pulse at a timing close to the first switch pulse for supplying a video signal to the pixel element in the last column. A pulse generated by one pulse generation circuit is supplied to a first scanner of an adjacent liquid crystal display device as a first start pulse. Then, the second pulse generation circuit of the second scanner generates a pulse at a timing close to the second switch pulse for supplying a video signal to the pixel element in the last row, and generates the second pulse. The pulse generated by the circuit
It is supplied as a second start pulse to a second scanner of an adjacent liquid crystal display device. Therefore, in the present invention, it is not necessary to provide a peripheral circuit for generating the first start pulse and the second start pulse for each liquid crystal display device, so that the device can be reduced in size and cost, and furthermore, can be arbitrarily selected. A multi-screen liquid crystal display device having the above screen size can be easily configured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a multi-screen liquid crystal display device according to the present invention.

FIG. 2 is a circuit diagram showing a liquid crystal display device constituting the multi-screen liquid crystal display device of FIG. 1;

FIG. 3 is a timing chart showing an operation of an H shift register 18.

FIG. 4 is a timing chart showing an operation of the V shift register 20.

FIG. 5 is a circuit configuration diagram illustrating an example of a conventional liquid crystal display device.

6A is a timing chart showing the operation of the H shift register 18, and FIG. 6B is a timing chart showing the operation of the V shift register 20. FIG.

FIG. 7 is a block diagram illustrating an example of a conventional multi-screen liquid crystal display device.

[Explanation of symbols]

2 ... multi-screen liquid crystal display device, 4 ... liquid crystal display device,
6 H output terminal, 8 V output terminal, 12 liquid crystal display device, 14 substrate, 16 pixel element, 18 H
Shift register, 20 ... V shift register, 22 ...
H switch element, 24 V switch element, 26 capacitor, 28 common electrode, 30 V start pulse,
32 V input terminal, 34 H start pulse, 36
H input terminal, 38 ... multi-screen liquid crystal display device, 40 ...
... Shift register drive circuit.

Claims (9)

[Claims] 1. A liquid crystal display device comprising: a plurality of liquid crystal display devices arranged adjacent to each other; each liquid crystal display device includes: a plurality of pixel elements arranged in a matrix; A first scanner for supplying a first switch pulse for turning on a switch element for supplying a video signal to the pixel element to the switch element in sequence for each of the pixel elements in a column; And a second scanner that supplies a second switch pulse for turning on a switch element that supplies a video signal to the pixel element to the switch element, sequentially for each of the pixel elements in each row of the matrix. In the multi-screen liquid crystal display device, one of the first and second scanners is provided for supplying a video signal to the pixel element in the last column or row. A pulse generation circuit that generates a pulse at a timing close to the first or second switch pulse, wherein the pulse generated by the pulse generation circuit is transmitted to the first or second scanner of an adjacent liquid crystal display device. A multi-screen liquid crystal display device supplied as the first or second start pulse. 2. The method according to claim 1, wherein the pulse generated by the pulse generation circuit is the first or second switch pulse for supplying a video signal to the pixel element in the last column or row. The multi-screen liquid crystal display device according to claim 1. 3. A liquid crystal display device comprising a plurality of liquid crystal display devices arranged adjacent to each other, wherein each of the liquid crystal display devices includes a plurality of pixel elements arranged in a matrix and a first start pulse.
A first scanner for supplying a first switch pulse to the switch element for sequentially turning on a switch element for supplying a video signal to the pixel element for each pixel element in each column of a matrix, and a second start A second scanner for supplying a second switch pulse to the switch element for sequentially turning on a switch element for supplying a video signal to the pixel element for each pixel element in each row of a matrix when a pulse is input; Wherein the first scanner generates a pulse at a timing close to the first switch pulse for supplying a video signal to the pixel elements in the last column. 1 pulse generating circuit, wherein the pulse generated by the first pulse generating circuit is transmitted to the first scanner of an adjacent liquid crystal display device. The second start pulse is supplied as the first start pulse, and the second scanner generates the pulse at a timing close to the second switch pulse for supplying a video signal to the pixel element in the last row. Wherein the pulse generated by the second pulse generation circuit is supplied as the second start pulse to the second scanner of the adjacent liquid crystal display device. Multi-screen liquid crystal display device. 4. The apparatus according to claim 3, wherein the pulse generated by the first pulse generation circuit is the first switch pulse for supplying a video signal to the pixel elements in a last column. The multi-screen liquid crystal display device as described in the above. 5. The pulse generated by the second pulse generation circuit is the second switch pulse for supplying a video signal to the pixel element in the last row. The multi-screen liquid crystal display device as described in the above. 6. The pulse generated by the first pulse generation circuit is generated after the first switch pulse for supplying a video signal to the pixel element in the last column is generated.
4. The multi-screen liquid crystal display device according to claim 3, wherein the first switch pulse is generated at the same time interval as the time interval between the first switch pulses. 7. The pulse generated by the second pulse generation circuit is generated after the second switch pulse for supplying a video signal to the pixel element in the last row is generated.
4. The multi-screen liquid crystal display device according to claim 3, wherein the second switch pulse is generated at the same time interval as the time interval between the second switch pulses. 8. The multi-screen liquid crystal display device according to claim 1, wherein video signals are supplied to the pixel elements in a plurality of columns at the same timing. 9. The multi-screen liquid crystal display device according to claim 1, wherein said first and second scanners include a shift register.