WO2006095304A1

WO2006095304A1 - Backlighted lcd display devices and driving methods therefor

Info

Publication number: WO2006095304A1
Application number: PCT/IB2006/050692
Authority: WO
Inventors: Eugene Boiko; John R. Hughes
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-03-10
Filing date: 2006-03-06
Publication date: 2006-09-14
Also published as: CN101138018A; TW200703194A; JP2008533519A

Abstract

An active matrix liquid crystal display device, and a method for the driving thereof, comprising driving the pixels (12) with a pre-determined drive voltage level, and driving the pixels with overdrive correction levels of drive voltage; wherein the pre-determined drive voltage level is the same for each pixel (12), and the overdrive correction level of drive voltage for each pixel (12) is the overdrive corrected voltage level for each respective pixel (12) corresponding to the data signal for the respective pixel (12). A backlight (28) may be switched on or off in relation to whether the pixels (12) or certain pixels are being driven with the pre-determined drive voltage level or with an overdrive correction level of drive voltage.

Description

DESCRIPTION

DISPLAY DEVICES AND DRIVING METHODS THEREFOR

The present invention relates to matrix display devices and systems, and to driving or addressing methods for such display devices.

Liquid crystal display devices are well known, and usually comprise a plurality of pixels arranged in an array of rows and columns.

Typically the pixels are addressed or driven as follows. The rows of pixels are selected one at a time. The pixels within the row currently selected are provided with respective display settings by virtue of respective data voltages being applied to each of the columns. Such data voltages are known by a number of names in the art, including data signals, video signals, image signals, drive voltages, column voltages, and so on.

Selection of each of the rows one by one, with driving of the columns as required during each row selection, provides display of one frame of the image being displayed. The display is then refreshed by a further frame being displayed in the same manner, and so on.

The level of a data voltage applied to a pixel determines how much light is output by that pixel by controlling the extent of the optical modulation effect of the liquid crystal layer in the pixel. It is known that due to capacitance effects and time-response of the liquid crystal layer, the liquid crystal layer can fail to reach the optical modulation condition it would reach in a steady-state situation for a given drive voltage by the end of the time the drive voltage is applied in the addressing scheme. A correction method called overdrive correction (ODC) (which may also be termed overdrive compensation) has been employed to alleviate this effect. Under ODC, a pixel is driven at a higher or lower voltage level than the voltage level that would be required for steady-state operation, so that by the end of the relevant voltage application period the voltage present across the pixel has reached a level estimated to be substantially equal to what the steady-state level should be. Further details of known ODC methods are described in US 5,495,265 and WO 2004/013835, which are incorporated herein by reference. The correction to be applied under ODC (i.e. how different the level of voltage applied to the pixel to achieve a given voltage across the liquid crystal layer of the pixel is from the given voltage) varies according to the liquid crystal panel design. Moreover the required correction varies according to what voltage level a pixel is at in the frame prior to that being corrected, and what voltage level is being sought in the present frame i.e. the pixel's current data setting and it's next data setting (this is often referred to as voltage pair). The correction required is typically calculated anew for each pixel for each frame. Thus, in conventional ODC schemes, it is required to have a frame buffer, so the voltage pairs can be determined, a look-up table comprising a matrix of many voltage pairs and many voltage settings (and possibly different panels) so the appropriate correction can be read-off for the determined voltage pair, and a processor for determining the correction from these items.

Another complication with ODC is that the correction to be applied can also vary with temperature. Given the large number of variables already employed in conventional ODC, this requires further complicated calculations and so on. WO 2004/034135 A1 describes one example in which an ODC scheme employing frame buffers and a look-up table with many matrix elements are compensated for temperature by the use of plural look-up tables each with many matrix elements. In addition, in order to implement ODC for grey level transitions toward or near the extremes of the liquid crystal transmission curve, additional buffers and/or increased selector matrix complexity in the panel driver IC are typically needed, resulting in increased silicon area and cost.

Liquid crystal displays often have a backlight, e.g. a fluorescent lamp, arranged such that such that light from the backlight passes through the pixels where it is modulated by the liquid crystal layer. US 2004/0012551 A1 describes a variable backlight control system employed in a driving scheme. It is separately known to drive other liquid crystal panels with so-called black fields inserted between the picture image fields, i.e. a driving scheme is employed in which in each frame a pixel is driven for some of the time at a data voltage level and for the rest of the frame is driven in black mode, as described in US 5,912,651 which is incorporated herein by reference. The visual effect perceived by a viewer is such that this approach can reduce the blurring effect of a moving image.

The present inventors have realised it would be desirable to provide

ODC driving schemes for matrix display devices that alleviate or reduce the large amount of processing required with conventional ODC schemes. The present inventors have also realised it would be desirable to provide ODC driving schemes for matrix display devices that remove the need for, or reduce the size of, frame buffers and/or look-up tables as used in conventional ODC schemes.

In a first aspect, the present invention provides an active matrix liquid crystal display device, comprising: a plurality of pixels; driving circuitry arranged to drive each pixel with a pre-determined drive voltage level followed by an overdrive correction level of drive voltage; wherein the pre-determined drive voltage level is the same for each pixel, and the overdrive correction level of drive voltage for each pixel is the overdrive corrected voltage level for each respective pixel corresponding to the video data signal applicable to the respective pixel. The active matrix liquid crystal display device may further comprise a backlight and backlight control circuitry, wherein the backlight control circuitry is arranged to switch the backlight on or off in relation to whether the driving circuitry is driving the pixels or certain pixels with the pre-determined drive voltage level or with an overdrive correction level of drive voltage. The driving circuitry and the backlight control circuitry may be arranged such that: the pixels or certain pixels are driven at the pre-determined voltage level for a first period of time, and during the first period of time the backlight is in a switched off state; and the pixels or certain pixels are addressed with their respective overdrive correction drive voltage levels for a second period of time, and during the second period of time the backlight is off.

The driving circuitry and the backlight control circuitry may be arranged such that the pixels or certain pixels continue to be addressed with their respective overdrive correction drive voltage levels during a third period of time, and during the third period of time the backlight is switched on.

The driving circuitry and the backlight control circuitry may be arranged such that: during a first time period of a frame, rows of the active matrix liquid crystal display device are driven sequentially, each pixel in a row being driven with its respective overdrive correction drive voltage level, and during the first time period of the frame, the backlight is in a switched off state; during a second time period of the frame, the rows are driven sequentially, each pixel in a row being driven with its respective video signal data voltage level without overdrive correction, and the backlight is switched on at the start of the second time period and remains switched on for the duration of the second time period; and during a third time period of the frame, the rows are driven sequentially at the common pre-determined voltage level, and the backlight remains switched on for the duration of the third time period. The driving circuitry may be arranged such that: driving pulses at the pre-determined voltage level applied to the rows of the active matrix liquid crystal display device are of shorter duration than driving pulses at the respective ODC drive voltages applied to the rows of the active matrix liquid crystal display device. The driving circuitry may be arranged such that: driving pulses at the respective ODC drive voltages are applied to the rows sequentially on a row- by-row basis as a function of time; and driving pulses at the pre-determined voltage level are applied simultaneously to plural rows of the active matrix liquid crystal display device. In a further aspect, the present invention provides a method of driving an active matrix liquid crystal display device comprising a plurality of pixels; the method comprising performing the following steps for different pixels: driving the pixel with a pre-determined drive voltage level; and driving the pixel with an overdrive correction level of drive voltage; wherein the pre-determined drive voltage level is the same for each pixel, and the overdrive correction level of drive voltage for each pixel is the overdrive corrected voltage level for each respective pixel corresponding to the data signal for the respective pixel. The method may further comprise switching a backlight on or off in relation to whether the pixels or certain pixels are being driven with the predetermined drive voltage level or with an overdrive correction level of drive voltage.

The method may be performed such that: the pixels or certain pixels are driven at the pre-determined voltage level for a first period of time, and during the first period of time the backlight is in a switched off state; and the pixels or certain pixels are addressed with their respective overdrive correction drive voltage levels for a second period of time, and during the second period of time the backlight is off. The method may be performed such that: addressing the pixels or certain pixels with their respective overdrive correction drive voltage levels is continued during a third period of time, and during the third period of time the backlight is switched on.

The method may be performed such that: during a first time period of a frame, rows of the active matrix liquid crystal display device are driven sequentially, each pixel in a row being driven with its respective overdrive correction drive voltage level, and during the first time period of the frame, the backlight is in a switched off state; during a second time period of the frame, the rows are driven sequentially, each pixel in a row being driven with its respective video signal data voltage level without overdrive correction, and the backlight is switched on at the start of the second time period and remains switched on for the duration of the second time period; and during a third time period of the frame, the rows are driven sequentially at the common predetermined voltage level, and the backlight remains switched on for the duration of the third time period.

The method may be performed such that: driving pulses at the pre- determined voltage level are applied to the rows of the active matrix liquid crystal display device with a shorter duration than driving pulses at the respective ODC drive voltages are applied to the rows of the active matrix liquid crystal display device.

The method may be performed such that: driving pulses at the respective ODC drive voltages are applied to the rows sequentially on a row- by-row basis as a function of time; and driving pulses at the pre-determined voltage level are applied simultaneously to plural rows of the active matrix liquid crystal display device.

In a further aspect, the present invention provides a method of driving an active matrix liquid crystal display device, comprising: applying a blank field to pixels of the device; and applying an overdrive corrected video field to the pixels.

The method may further comprise flashing a backlight for illuminating the pixels. The overdrive correction drive voltage applied to a pixel may be a corrected voltage calculated or specified according to the device properties. The overdrive correction drive voltage may be the voltage level applied to a pixel under an overdrive correction drive scheme so that during the course of the overdrive corrected voltage application, or by the end of the overdrive corrected voltage application, the optical modulation level of the liquid crystal layer of the pixel has reached, or is closer to reaching than would otherwise be the case, the optical modulation level that the liquid crystal layer of the pixel would reach if the specified or received uncorrected data voltage level (e.g. data signal, video signal) were applied to the pixel for longer than the delays in voltage response of a pixel caused by capacitance effects and time-response of the liquid crystal layer. In a further aspect, the present invention provides an active matrix liquid crystal display device, and a method for the driving thereof, comprising driving the pixels with a pre-determined drive voltage level, and driving the pixels with overdrive correction levels of drive voltage; wherein the pre-determined drive voltage level is the same for each pixel, and the overdrive correction level of drive voltage for each pixel is the overdrive corrected voltage level for each respective pixel corresponding to the data signal for the respective pixel. A backlight may be switched on or off in relation to whether the pixels or certain pixels are being driven with the pre-determined drive voltage level or with an overdrive correction level of drive voltage.

In a further aspect, each frame a pixel is driven to a pre-determined level prior to being driven with an ODC level of drive voltage. The predetermined level may be one corresponding to dark state, i.e. "black". In a given frame all the pixels may be driven to the pre-determined level prior to all the pixels being driven with their respective ODC level of drive voltage. By virtue of this, for each pixel, and for each frame, the required ODC level of voltage is always based upon the same starting point, i.e. there is no longer any occurrence of the two-dimensional matrix of prior art ODC systems in which the data voltage to be achieved across the pixel in the present frame is arranged in a matrix compared to the voltage level of the pixel in the previous frame (the above mentioned voltage pairs). This removes the need for the frame buffer and a conventional ODC look-up table with a two-dimensional matrix of given data voltage to be achieved compared to buffered voltage level from previous frame.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a schematic diagram of an active matrix liquid crystal display device;

Figure 2 is a block diagram showing a column driver circuit of the active matrix liquid crystal display device of Figure 1 ; Figure 3 is a flowchart showing process steps employed for a given row of pixels in an adapted ODC driving process;

Figure 4 is a schematic illustration (not to scale) showing a plot of the light transmission from a pixel against time during the course of the process shown in Figure 3;

Figure 5 is a schematic illustration showing the order in which rows 1 to m are addressed as a function of time over the course of a frame in a driving scheme;

Figure 6 is a schematic illustration (not to scale) showing a plot of the light transmission from a pixel against time for a pixel over the course of a frame as a result of voltage application shown in Figure 5;

Figure 7 is a block diagram showing another example of a column driver circuit of an active matrix liquid crystal display device as shown in Figure 1 ;

Figure 8 is a schematic illustration showing ODC voltage driving pulses and blank field driving pulses being provided to rows 1 to m sequentially; and

Figure 9 is a schematic illustration showing ODC voltage driving pulses being provided to rows 1 to m sequentially and blank field driving pulses being provided simultaneously.

Figure 1 is a schematic diagram of an active matrix liquid crystal display device in which a first embodiment of the invention is implemented. The display device, which is suitable for displaying video pictures, comprises an active matrix addressed liquid crystal display panel 10 having a row and column array of pixels which consists of m rows (1 to m) with n horizontally arranged pixels 12 (1 to n) in each row. Only a few of the pixels are shown for simplicity.

Each pixel 12 is associated with a respective switching device in the form of a thin film transistor, TFT, 11. The gate terminals of all TFTs 11 associated with pixels in the same row are connected to a common row conductor 14 to which, in operation, selection (gating) signals are supplied. Likewise, the source terminals associated with all pixels in the same column are connected to a common column conductor 16 to which data (video) signals are applied. The drain terminals of the TFTs are each connected to a respective transparent pixel electrode 17 forming part of, and defining, the pixel. The conductors 14 and 16, TFTs 11 and pixel electrodes 17 are carried on one transparent plate while a second, spaced, transparent plate carries an electrode common to all the pixels (hereinafter referred to as the common electrode). Liquid crystal is disposed between the plates.

A backlight 28 is disposed such that light from the backlight 28 passes through the panel and is modulated according to the transmission characteristics of the pixels 12. The backlight is controlled by a backlight control module 30.

The display panel is operated as follows. The device is driven one row at a time by scanning the row conductors 14 with a selection (gating) signal so as to turn on the rows of TFTs in turn and applying data (video) signals to the column conductors for each row of picture display elements in turn as appropriate and in synchronism with the selection signals so as to build up a complete display frame (picture). Using one row at time addressing, all TFTs 11 of the selected row are switched on for a period determined by the duration of a selection signal during which the data signals are transferred from the column conductors 16 to the pixels 12

The row conductors 14 are supplied in their order of selection with selection signals by a row driver circuit 20 comprising a digital shift register controlled by regular timing pulses from a timing and control circuit 21. In the intervals between selection signals, the row conductors 14 are supplied with a substantially constant reference potential by the row driver circuit 20.

ODC drive voltages (data voltages) 23 are supplied to the column conductors 16 from a column driver circuit 22. The column driver circuit 22 is supplied with video signals 25 from a video processing circuit 24 and timing pulses 27 from the timing and control circuit 21 in synchronism with row scanning to provide serial to parallel conversion appropriate to the row at a time addressing of the panel 10. The column driver circuit 22 is further supplied with D. C. voltages 29 from a voltage supply 26. In this embodiment the D. C. voltages 29 provided by the voltage supply 26 are in the form of one or several discrete D. C. voltage levels.

Figure 2 is a block diagram showing the column driver circuit 22 in more detail. The column driver circuit 22 comprises a selector control module 90 which is coupled to the timing and control circuit 21 for receiving the timing pulses 27 from the timing and control circuit 21.

The column driver circuit 22 further comprises n selectors 92, one for each of the n column conductors 16. Each selector 92 is coupled to the selector control module 90. The column driver circuit 22 further comprises n output buffers 82, each respective output buffer 82 being coupled to a respective selector 92 and a corresponding respective common column conductor 16.

The column driver circuit 22 further comprises a resistive digital-to- analog converter (R-DAC) 91 , which is coupled to the voltage supply 26 for receiving the D. C. voltages 29 from the voltage supply 26. The R-DAC 91 is coupled to each of the selectors 92 by a common bus 93 comprising N lines, one for each of N voltage levels providing a respective one of N grey levels.

In operation, the R-DAC 91 converts the D. C. voltages 29 and provides N voltage levels, one on each respective line of the bus 93, to all of the selectors 92. For each selector 92 respectively, the selector control module 90, under timing control of the timing pulses 27, instructs the respective selector 92 as to which of the N voltage levels to select in accordance with the video signal 25 received for the respective column conductor 16. The chosen voltage level is selected by the selector 92 and input into the respective buffer 82, from where it is output and applied to the column conductor 16 as a respective ODC drive voltage level 23.

Other details of the liquid crystal display device, except where otherwise stated below, may be as per any conventional active matrix liquid crystal display device driven with an ODC scheme, and are in this particular embodiment the same as, and operate the same as, the liquid crystal display device disclosed in US 5,495,265, the contents of which are contained herein by reference. Alternatively, some or all of the details may also and/or instead be the same as the liquid crystal display device disclosed in US 5,130,829, the contents of which are contained herein by reference.

However, in this embodiment the video processing circuit 24 the voltage supply 26 and the column driver circuit have been adapted to carry out an ODC driving scheme including blank field insertion, as will be described in more detail with reference to Figures 2, 3 and 4.

In overview, each frame a pixel is driven to a pre-determined level prior to being driven with an ODC level of drive voltage. In this embodiment, the predetermined level is one corresponding to dark state, i.e. "black". Furthermore, in this embodiment, in a given frame all the pixels are driven to the predetermined level prior to all the pixels being driven with their respective ODC level of drive voltage. By virtue of this, for each pixel, and for each frame, the required ODC level of voltage is always based upon the same starting point, i.e. there is no longer any occurrence of the two-dimensional matrix of prior art ODC systems in which the data voltage to be achieved across the pixel in the present frame is arranged in a matrix compared to the voltage level of the pixel in the previous frame (the above mentioned voltage pairs). This removes the need for the frame buffer and a conventional ODC look-up table with a two- dimensional matrix of given data voltage to be achieved compared to buffered voltage level from previous frame.

This process therefore requires different voltage levels to be applied compared to a conventional ODC version of the device, hence the voltage supply 26 in this embodiment is adapted accordingly to provide the required voltages. In particular, for example, for N pixel brightness settings, only N D. C. voltage levels are required for ODC driving in this embodiment, compared to conventional ODC driving that would require more than N D. C. voltage levels. This is because conventional ODC driving typically requires additional voltage levels to be provided so as to cope with overdrive transitions to, or near, threshold voltage V_th and/or saturation voltage V_sat, voltages outside of V_th and V_sat consequently being needed in conventional ODC arrangements. Furthermore, in conventional ODC arrangements, certain voltage levels are required for which no ODC will occur. These different reasons for additional voltage levels tend to be avoided by the present embodiment, since by virtue of the required ODC level of voltage always being based upon the same starting point, these variations are not included.

Furthermore, in this embodiment the visual appearance produced by the above driving process is further improved by turning the backlight on and off in relation to the ODC voltage level driving and blank field driving stages, as will be explained in more detail below with reference to Figures 2 and 3.

Figure 3 is a flowchart showing process steps employed for a given row of pixels in the adapted ODC driving process according to this embodiment. Figure 4 is a schematic illustration (not to scale) showing a plot 34 of the light transmission 36 from a pixel against time 38 during the course of the process steps s2, s4 and s6 to be described below with reference to Figure 3. The light transmission 36 is the relative transmission from the pixel for a given light entering the pixel - i.e. the plot 34 is the situation without consideration of whether the backlight is switched on or off.

At step s2, the pixels are driven with a blank field for a first period of time indicated by reference numeral 40 in Figure 4, i.e. in this embodiment all the pixels are driven at a common pre-determined voltage level, the predetermined voltage level being one that provides a low light transmission level 48, which may be considered as "black" display output. During the first time period 40, the backlight 28 is in a switched off state, as indicated by the expression "BACKLIGHT OFF" in Figure 4.

At step s4, the pixels are addressed with their respective ODC drive voltage levels, i.e. the ODC video field is applied, for a second period of time indicated by reference numeral 42 in Figure 4. The column driver circuit 22 selects the appropriate ODC drive voltage level 23 for a given pixel according to the received video signal 25 as described above with reference to Figure 2. During the second time period 42, the backlight 28 is off, as indicated by the expression "BACKLIGHT OFF" in Figure 4. It is noted that carrying out driving of a frame using steps s2 and s4 alone provides an improved form of ODC driving, and in other embodiments such a process may be employed in such a simple fashion. If so, the backlight may be switched so as to be on continuously. Another possibility is the backlight may be switched so as to be on during only part of a frame cycle, for example being switched on substantially only during the step s4 of applying the video field. However, in this embodiment, at step s6, the backlight 28 is flashed, i.e. the backlight 28 is switched on and, during the course of a third period of time indicated by reference numeral 44 in Figure 4, is left on, as indicated by the expression "BACKLIGHT ON" in Figure 4. During step s6, i.e. during the third period 44, the pixels continue to be addressed with their respective ODC drive voltage levels as in step s4, i.e. the ODC video field continues to be applied during the third period of time 44.

In the above process, the backlight is switched on and off in a scanning mode, i.e. is operated in a scanning backlight mode, i.e. the backlight is arranged in a number of portions, each portion corresponding to a number of consecutive rows of pixels, and the only portion of the backlight driven at a given time is the portion of the backlight corresponding to that group of consecutive rows of pixels in which the row being selected is located.

In this embodiment, the first period 40 is of approximately equal duration to the second period 42, whereas the third period 44 is half the duration of each of the first period 40 and second period 42, such that the ratio of backlight off to backlight on is 4:1. Generally, for example in other embodiments, this ratio should preferably be between 4:1 and 1 :1 , although other ratios may be employed.

Furthermore, in this embodiment, the voltage driving stages are fully synchronised with the switching on and off of the backlight, but this need not be so in other embodiments. For example, the backlight may be switched off a short time after the driving voltage for the blank field starts to be applied.

The first, second and third periods 40, 42, 44 together provide an addressing frame 49. The process, i.e. steps s2, s4 and s6 is then repeated for each further frame, providing for example a first period 50, a second period 52 and a third period 54 of a further frame 59, and so on. In this embodiment the addressing frequency is 70Hz such that there are 70 frames 49, 59 per second, although this frequency may be a different value in other embodiments.

By driving all the pixels to the common pre-determined voltage level in step s2, the following ODC driving is always performed from a given starting voltage, such that a two-dimensional array of voltage pairs for calculation of the ODC voltage is no longer required (hence use of a frame buffer and a two- dimensional look-up table is no longer required). The ODC driving process carried out in steps s4 and s6 is therefore dramatically simplified, for example no longer requiring a look-up table nor a frame buffer RAM. By effectively dividing the ODC driving into a first stage when the backlight 28 is off (i.e. second period 42) and a second stage when the backlight 28 is on (i.e. third period 44) the contrast ratio of the display is improved, since the image light level displayed is only displayed during the more stable or correct stage of the third period 44 rather than the more varying stage of the second period 42. Furthermore, the contrast ratio is also improved by virtue of the backlight 28 being off during the first period 40 when the blank field is being inserted.

In the above described embodiment, the backlight is used in a scanning mode. In a second main embodiment, the backlight is used in a strobing mode rather than a scanning mode, as follows. In this second main embodiment, the active matrix liquid crystal display device is as shown in Figure 1 , but is operated as will now be described with reference to Figures 5 and 6.

Figure 5 is a schematic illustration showing the order in which the rows 1 to m are addressed as a function of time 70 over the course of a frame 69 in the driving scheme of this second main embodiment. Figure 6 is a schematic illustration (not to scale) showing a plot 74 of the light transmission 76 from a pixel against time 70 for a pixel over the course of the frame 69 as a result of the voltage application shown in Figure 5. Again, the light transmission 76 is the relative transmission from the pixel for a given light entering the pixel - i.e. the plot 74 is the situation without consideration of whether the backlight 28 is switched on or off. Referring to Figure 5, during the course of a first time period 60 of the frame 69 the rows are driven sequentially from row 1 to row m, each pixel in a row being driven with its respective appropriate ODC drive voltage level. During the first time period 60 the backlight 28 is in a switched off state. Referring now to Figure 6, as ODC is being applied, the transmission level of the pixel rises to the level which will be required to be displayed during an impending second time period 62.

Referring again to Figure 5, during the course of the second time period 62 the rows are driven sequentially from row 1 to row m, each pixel in a row being driven with its respective video signal data voltage level, i.e. the pixel is driven without ODC during this second time period. The backlight 28 is switched on at the start of the second time period 62 and remains switched on for the duration of the second time period 62. Referring again to Figure 6, the transmission 76 of the pixel is at the required video signal data voltage level to be displayed for illumination by the backlight 28 which is now switched on.

Referring again to Figure 5, during the course of a third time period 64 the rows are driven sequentially from row 1 to row m with a blank field i.e. in this embodiment all the pixels are driven at a common pre-determined voltage level. The backlight 28 remains switched on for the duration of the third time period 64. Referring again to Figure 6, the transmission 76 of the pixel is a low light transmission level 68, which may be considered as "black" display output, resulting from the application of the pre-determined voltage level.

Thus, in other words, in this second main embodiment, the panel is addressed with video data twice followed by a 'blank' frame for every video (super-) frame. In a first video sub-frame overdrive voltages are applied to get the correct transmission level by a second video sub-frame. In the second video sub-frame normal voltages are applied in order to maintain the correct transmission level. The backlight is switched on during the second video sub- frame and the 'blank' frame, which in this case is 'black'. Note that two distinct sets of grey level voltages are used in this embodiment, the first being the overdrive voltages (i.e. the ODC drive voltage levels) for the first sub-frame and the second being the normal (i.e. the video signal data voltage levels) for the second sub-frame. This is however not necessarily significantly disadvantageous, because in many applications it may be desirable to have both these sets of drive voltages available anyway, for example so that the normal voltage levels may be used (rather than ODC) when power consumption reduction is desired to be available as a user-selectable or automatically triggered option. A further advantage is that although there may be more than one set of grey levels, only one set is required at any given time, thus the selection matrix is relatively simple. Moreover, typically with buffers, it is the number of buffers being used simultaneously that tends to require increasing silicon, rather than different buffers provided they are not required to be operated simultaneously.

By applying the voltages in the above described manner, different brightness of different rows is avoided or reduced. By strobing the backlight, i.e. flashing the backlight for all the rows each time, the rows addressed earlier in a frame would otherwise be brighter than those addresses later in the frame, as they would have more time for the liquid crystal to respond and for the benefits of ODC to take hold. Therefore, in this embodiment, by use of the third time period, i.e. having the backlight 28 switched on whilst applying the blank field (common pre-determined voltage level), these effects are evened out over the whole frame i.e. over all the rows 1 to m. Another possibility is this approach could nevertheless be used with a scanning backlight.

As is mentioned above, it may be desirable to be able to switch between ODC mode and non-ODC mode in a given panel. The following embodiment, described below with reference to Figures 1 and 7, is particularly suited to providing this facility in an efficient manner.

The active matrix liquid crystal display device of this embodiment is again as shown in Figure 1 , except in this embodiment certain details of the column driver circuit 22 are different compared to the column driver circuit 22 of the first embodiment. Figure 7 is a block diagram showing the column driver circuit 22 of this embodiment. The column driver circuit 22 of this embodiment comprises the following parts which were are also in the column driver circuit 22 of the first embodiment as shown in Figure 2, and which are indicated by the same reference numerals: a selector control module 90, n selectors 92, n output buffers 82, and a resistive digital-to-analog converter (R-DAC) 91. These parts are coupled together and to other parts of the active matrix liquid crystal display device in the same way as in the example of Figure 2, except where indicated below.

The column driver circuit 22 of this embodiment further comprises a look-up table (LUT) 112 and an N-of-X selector 110, both of which are coupled to the selector control module 90. The N-of-X selector 110 is also coupled to the selectors 92 via the bus 93, and to the R-DAC 91 via a particular piece of the bus 93 indicated as bus 93a in Figure 7.

In this embodiment, the D. C. voltages 29 received by the R-DAC 91 from the voltage supply 26 comprise X levels, where X > N. In operation, the N-of-X selector 110, under the control of the selector control module 90, selects, and forwards to the selectors, a set of N voltage levels from the available X voltage levels. Thus, in this embodiment, plural different sets of N voltages may be employed. Thus, for example, different sets of N voltages may be employed in order to perform temperature compensation, and/or for switching between ODC-mode and one for non-ODC mode. Thus, in this embodiment, design flexibility is provided in that the selector control module comprises a programmable circuit including the LUT 112 that is programmed to select the set of N voltage levels by reading off required sets of values from the LUT 112. This provides a flexible arrangement that can be used, for example, to provide a common design for use in a number of different liquid crystal panels, the appropriate voltage levels for a given type of panel being read off accordingly from the LUT. However, in other embodiments, plural sets of voltage levels can be provided in less flexible ways, not involving an LUT, for example by having pre-determined fixed sets available, which may for example be conveniently used as a fixed design for a given type of liquid crystal panel. So, to recap, this embodiment, and in particular the column driver circuit shown in Figure 7, provides at least two dynamically selectable sets of N greyscale level voltages, one for ODC-mode and one for non-ODC mode. Further selectable sets, e.g. for reflective mode compared to transmissive mode of display operation may be provided as required. In other embodiments, other ways of providing two or more sets of dynamically selectable sets of greyscale level voltages may be implemented, for example selectable fixed sets of voltages, selectable programmable and fixed sets, and so on.

An advantage of these dynamically selectable sets of greyscale levels is that the column driver circuit 22 can be used in a variety of different panels, and the greyscale voltages can be programmed according to the particular panel to be used in any particular circumstances. Furthermore, other variables, for example temperature compensation, use of different frame rates, and so on, can be accommodated in one design of product.

In the embodiments shown in Figure 7 and Figure 2, the (column) buffers 82 are connected after the (1-of-N) selectors 92. This may be referred to as "buffer per column" architecture, and is typically used in large panels. In other embodiments, particularly but not exclusively for smaller panels, another so-called "buffer per grey level" architecture may be employed, in which the buffers are connected before the 1-fo-N selectors i.e. one buffers (or one set of buffers) is shared by all the columns. In further embodiments, yet more complex circuitry comprising use of a

RAM may be employed. Video data and synchronisation is arranged in conventional fashion for non-ODC mode, however an additional clock generation circuit block generating a higher frequency clock is used for ODC mode (with blank field insertion). An advantage of this implementation is that the display scan timing becomes disassociated from the data and clocks at the interface. A variable frame rate is possible with optional synchronisation to the internal scan rate of the display as is normal in current mobile display applications. However, this is at the expense of a trade-off with the need to use a full frame buffer RAM. In each of the above embodiments, temperature compensation of the

ODC driving may be implemented in similar fashion to conventional ODC driving arrangements, i.e. different ODC drive voltage level values are required for given voltage data levels according to the temperature. Such processing is simplified with the present invention compared to conventional ODC arrangements as there is typically significantly less data to be temperature compensated. The order in which different actions take place in a given frame in the above embodiments may be varied in other embodiments. For example, referring to Figure 4, in the first embodiment above, a frame 49 starts with the first time period 40 and ends with the third time period 44. However, in other embodiments, a frame may start with the third time period, followed by the time period and ending with the second time period; in other words the delimitation of where a frame starts and ends compared to the three stages of a frame may be different in other embodiments. The same considerations apply, for example to the frames in Figures 4, 5, 8 and 9.

In the above embodiments, either all the pixels are driven to the blank field pre-determined voltage at the same time or consecutively (i.e. without any pixels or rows being driven to ODC voltage levels in the meantime). However, this need not be the case, and in other embodiments some pixels but not all the pixels, e.g. some rows but not all the rows, are driven to the blank field predetermined voltage followed by some other pixels or rows of pixels being driven with ODC voltage levels.

In the above embodiments, for a given pixel, driving with an ODC voltage level is alternated with driving with a blank field pre-determined voltage. However, this need not be the case, and in other embodiments the following may be implemented: (i) a given pixel may be driven with an ODC voltage plural times, then with the blank field one time, then an ODC voltage plural times, then with the blank field one time, and so on; or

(ii) a given pixel may be driven with an ODC voltage plural times, then with the blank field plural times, then an ODC voltage plural times, then with the blank field plural times, and so on; or (iii) a given pixel may be driven with an ODC voltage one time, then with the blank field plural times, then an ODC voltage one time, then with the blank field plural times, and so on.

In some embodiments, for example embodiments (i), (ii) and (iii) described in the preceding paragraph, the selection pulses for driving the pixels with a blank field (i.e. with a common pre-determined voltage level) may be made shorter than the selection pulses for driving the pixels with video data. This is shown schematically in Figure 8, which is a schematic illustration showing ODC voltage driving pulses 104 being provided to the rows 1 to m sequentially on a row-by-row basis as a function of time 102 over the course of a video frame 105; with blank field driving pulses 106, which are of shorter duration than the video voltage driving pulses 104, being provided to the rows 1 to m sequentially on a row-by-row basis as a function of time 102 over the course of a blank frame 107 that follows the video frame 105, the blank frame 107 thereby being shorter than the video frame 105. This advantageously shortens the required addressing time. However, this need not be the case, and in other embodiments, the selection pulses for driving the pixels with a blank field (i.e. with a common pre-determined voltage level) may be the same width as, or longer than, the selection pulses for driving the pixels with video data.

In some embodiments, for example embodiments (i), (ii) and (iii) described in the paragraph before the preceding paragraph, the driving of the pixels with a blank field (i.e. with a common pre-determined voltage level) is carried out one row at a time within a frame. However, as each pixel is being driven to the same voltage level, such row-by-row selection is not compulsory, hence in other embodiments some or all of the rows may be selected for driving with the common pre-determined voltage level at the same time. This is shown schematically in Figure 9, which is a schematic illustration showing ODC voltage driving pulses 94 being provided to the rows 1 to m sequentially on a row-by-row basis as a function of time 92 over the course of a video frame 95; with blank field driving pulses 96 for each row 1 to m being provided simultaneously during a blank frame 97, with the blank frame 97 thereby being shorter than the video frame 95. This advantageously shortens the required addressing time.

In the above embodiments, the pre-determined voltage applied during the blank fields is a voltage level that provides a low display output, which may be considered as black. However, this need not be the case, and in other embodiments a pre-determined voltage level producing a grey output may be used. This may be used, for example, to provide simpler ODC driving values.

In those embodiments where the backlight is not switched on during the blank field, such a grey level may have no detrimental effect on contrast ratio, However, even in embodiments where this is not the case, the decrease in contrast ratio may be a trade-off worth paying with respect to simpler ODC driving values, say.

Furthermore, in some embodiments the pre-determined voltage applied during the blank fields may correspond to VSAT (saturation voltage) or VTH (threshold voltage) of the liquid crystal. In these cases the transition to 'blank' may itself be overdriven to improve the extent to which the transition is completed within a given time.

For each of the above embodiments, it may be desirable to be able to operate the panel in non-ODC mode as well as in ODC mode, e.g. for reasons of power consumption in mobile and handheld applications. Two distinct sets of driving voltage levels may then be needed in order to define the correct gamma curve in each operating mode. This may be achieved by: a) having two fixed drive voltage level sets available and a mechanism that allows to select one or the other voltage set; or b) having one fixed voltage level set, with the other voltage level set being programmable via a look-up-table; or c) having both voltage level sets that are programmable via a lookup-table - this being the most flexible solution capable of being used with a number of panels without modifications to the driver IC. The invention idea in its most general form: each pixel element (R, G and B) in an LCD is addressed alternately with greyscale levels corresponding to video data and a pre-determined greyscale level. The overdrive technique is applied to transitions from the pre-determined greyscale level to the next greyscale corresponding to video data. The pre-determined greyscale level is the same for all pixel elements.

Various aspects of the above embodiments may be summarised as follows.

In place of conventional (constant output) backlight a strobing or scanning backlight may be used to enhance image quality. Both the overdrive technique and conventional (i.e. non-ODC) driving technique may be combined, for example the transition from the pre-determined greyscale level to the next video data is overdriven and is then followed by more video data which is not overdriven (applied conventionally to the pixel) one or several times before the next addressing with the pre-determined greyscale level. Equally, transitions to the per-determined greyscale level may be overdriven and/or repeated one or several times in succession. Variations on these schemes may include addressing whole frames alternately with video data and the pre-determined greyscale level ('blank field insertion'), or addressing parts of each frame with video data and addressing the rest of the frame with the pre-determined greyscale level ('blank stripe insertion'). It is to be noted that the sequence: video data with overdrive; then possibly video data without overdrive

(one or more times); then pre-determined grey level (one or more times); then video data with overdrive is applied on pixel level but not necessarily on whole frame level, i.e. it is possible to have both video data and 'blank' data present in the same frame - frames do not have to be wholly 'blank' or video. In a simple implementation, the following applies:

- there are no additional circuit blocks or extensions of existing circuits required;

- there is provided an expanded voltage range for column driving compared with conventional driving (the column driver IC may be modified in order to cope with higher voltage);

- data sequence and synchronization at the LCD module interface is different from conventional driving: i.e. the following may be performed: VIDEO DATA 1 , 'BLANK' DATA, VIDEO DATA 2, 'BLANK' DATA, VIDEO DATA 3, and so on (note video data and/or blank data may be repeated one or more times);

- unswitched, strobing or scanning backlight mode may be used. In some embodiments, the following may be provided:

- additional circuit block(s) to enable selection of 1 set or several sets (dynamic row-to-row or frame-to-frame) of N column driving voltages (N = the number of grey scales). The column driving voltage sets may be fixed in the column driver IC(s) or externally, or they could be programmable in the column driver IC(s) or provided externally by some means, for example using a liner programmable DAC;

- expanded voltage range for column driving compared with conventional driving;

- data sequence and synchronization at the LCD module interface may be different from conventional driving, e.g. may be as follows: VIDEO DATA 1 ,

'BLANK' DATA, VIDEO DATA 2, 'BLANK' DATA, VIDEO DATA 3, and so on. Note video data and/or blank data may be repeated one or more times. Note also that if a whole 'blank' frame is sent then the data could be replaced with a 'blank frame command' instead of sending the data for each pixel). The various embodiments tend to respectively provide one or more of the following advantages: the need for a frame buffer RAM at module level may be eliminated (providing saving of Si area and cost); the need for a look-up-table may be eliminated or at least the size of the look-up-table may be reduced (providing saving of Si area and cost); the need for extra column drive buffers may be eliminated (providing saving of Si area and cost); the need for extra column switch matrices may be eliminated (providing saving of Si area and cost); motion blur due to slow response of AMLCD panel may be reduced (performance improvement); motion blur due to 'sample & hold effect' may be reduced (performance improvement); the look-up-table or tables may be generated more easily than is the case with conventional ODC systems. In the case of conventional ODC, accurate timing measurements typically must be made for all or part of the possible grey scale transitions. Here, typically, only accurate luminance measurements are considered or required since the look-up-table may determine the gamma curve of the panel in the above embodiments.

Claims

1. An active matrix liquid crystal display device, comprising: a plurality of pixels (12); driving circuitry arranged to drive each pixel (12) with a pre-determined drive voltage level followed by an overdrive correction level of drive voltage; wherein the pre-determined drive voltage level is the same for each pixel (12), and the overdrive correction level of drive voltage for each pixel (12) is the overdrive corrected voltage level for each respective pixel (12) corresponding to the data signal for the respective pixel (12).

2. An active matrix liquid crystal display device according to claim 1 , further comprising a backlight (28) and backlight control circuitry (30), wherein the backlight control circuitry (30) is arranged to switch the backlight (28) on or off in relation to whether the driving circuitry is driving the pixels (12) or certain pixels with the pre-determined drive voltage level or with an overdrive correction level of drive voltage.

3. An active matrix liquid crystal display device according to claim 2, wherein the driving circuitry and the backlight control circuitry (30) is arranged such that: the pixels (12) or certain pixels are driven at the pre-determined voltage level for a first period of time (40), and during the first period of time (40) the backlight (28) is in a switched off state; and the pixels (12) or certain pixels are addressed with their respective overdrive correction drive voltage levels for a second period of time (42), and during the second period of time (42) the backlight (28) is off.

4. An active matrix liquid crystal display device according to claim 3, wherein the driving circuitry and the backlight control circuitry (30) is arranged such that: the pixels (12) or certain pixels continue to be addressed with their respective overdrive correction drive voltage levels during a third period of time (44), and during the third period of time (44) the backlight (28) is switched on.

5. An active matrix liquid crystal display device according to claim

2, wherein the driving circuitry and the backlight control circuitry (30) is arranged such that: during a first time period (60) of a frame (69), rows of the active matrix liquid crystal display device are driven sequentially, each pixel (12) in a row being driven with its respective overdrive correction drive voltage level, and during the first time period (60) of the frame (69), the backlight (28) is in a switched off state; during a second time period (62) of the frame (69), the rows are driven sequentially, each pixel (12) in a row being driven with its respective video signal data voltage level without overdrive correction, and the backlight (28) is switched on at the start of the second time period (62) and remains switched on for the duration of the second time period (62); and during a third time period (64) of the frame (69), the rows are driven sequentially at the common pre-determined voltage level, and the backlight (28) remains switched on for the duration of the third time period (64).

6. An active matrix liquid crystal display device according to any of claims 1 to 5, wherein the driving circuitry is arranged such that: driving pulses (106) at the pre-determined voltage level applied to the rows of the active matrix liquid crystal display device are of shorter duration than driving pulses (104) at the respective ODC drive voltages applied to the rows of the active matrix liquid crystal display device.

7. An active matrix liquid crystal display device according to any of claims 1 to 5, wherein the driving circuitry is arranged such that: driving pulses (94) at the respective ODC drive voltages are applied to the rows sequentially on a row-by-row basis as a function of time; and driving pulses (96) at the pre-determined voltage level are applied simultaneously to plural rows of the active matrix liquid crystal display device.

8. A method of driving an active matrix liquid crystal display device comprising a plurality of pixels (12); the method comprising performing the following steps for different pixels (12): driving the pixel (12) with a pre-determined drive voltage level; and driving the pixel (12) with an overdrive correction level of drive voltage; wherein the pre-determined drive voltage level is the same for each pixel (12), and the overdrive correction level of drive voltage for each pixel (12) is the overdrive corrected voltage level for each respective pixel (12) corresponding to the data signal for the respective pixel (12).

9. A method of driving an active matrix liquid crystal display device according to claim 8, further comprising switching a backlight (28) on or off in relation to whether the pixels (12) or certain pixels are being driven with the pre-determined drive voltage level or with an overdrive correction level of drive voltage.

10. A method of driving an active matrix liquid crystal display device according to claim 9, wherein: the pixels (12) or certain pixels are driven at the pre-determined voltage level for a first period of time (40), and during the first period of time (40) the backlight (28) is in a switched off state; and the pixels (12) or certain pixels are addressed with their respective overdrive correction drive voltage levels for a second period of time (42), and during the second period of time (42) the backlight (28) is off.

11. A method of driving an active matrix liquid crystal display device according to claim 10, wherein: addressing the pixels (12) or certain pixels with their respective overdrive correction drive voltage levels is continued during a third period of time (44), and during the third period of time (44) the backlight (28) is switched on.

12. A method of driving an active matrix liquid crystal display device according to claim 9, wherein: during a first time period (60) of a frame (69), rows of the active matrix liquid crystal display device are driven sequentially, each pixel (12) in a row being driven with its respective overdrive correction drive voltage level, and during the first time period (60) of the frame (69), the backlight (28) is in a switched off state; during a second time period (62) of the frame (69), the rows are driven sequentially, each pixel (12) in a row being driven with its respective video signal data voltage level without overdrive correction, and the backlight (28) is switched on at the start of the second time period (62) and remains switched on for the duration of the second time period (62); and during a third time period (64) of the frame (69), the rows are driven sequentially at the common pre-determined voltage level, and the backlight (28) remains switched on for the duration of the third time period (64).

13. A method of driving an active matrix liquid crystal display device according to any of claims 8 to 12, wherein: driving pulses (106) at the pre-determined voltage level are applied to the rows of the active matrix liquid crystal display device with a shorter duration than driving pulses (104) at the respective ODC drive voltages are applied to the rows of the active matrix liquid crystal display device.

14. A method of driving an active matrix liquid crystal display device according to any of claims 8 to 12, wherein: driving pulses at the respective ODC drive voltages (94) are applied to the rows sequentially on a row-by-row basis as a function of time; and driving pulses (96) at the pre-determined voltage level are applied simultaneously to plural rows of the active matrix liquid crystal display device.

15. A method of driving an active matrix liquid crystal display device, comprising: applying a blank field to pixels (12) of the device; and applying an overdrive corrected video field to the pixels (12).

16. A method of driving an active matrix liquid crystal display device according to claim 15, further comprising: flashing a backlight (28) for illuminating the pixels (12).