WO2007010482A2

WO2007010482A2 - Display devices and driving method therefor

Info

Publication number: WO2007010482A2
Application number: PCT/IB2006/052454
Authority: WO
Inventors: Steven C. Deane; Alan G. Knapp
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-07-20
Filing date: 2006-07-18
Publication date: 2007-01-25
Also published as: WO2007010482A3; TW200717407A

Abstract

Driving schemes are described in which rows (1 to m) are selected one at a time and column data voltages are inverted to provide inversion schemes for active matrix liquid crystal display devices comprising pixels (12) arranged in rows (1 to m) and columns (1 to n). The polarity of column data signals is only inverted every set of row. An odd number of sets of column voltages are applied within the frame. This reduces power consumption, and also drives the array of pixels during the frame blanking interval so as to reduce undesirable display artefacts.

Description

DESCRIPTION

DISPLAY DEVICES AND DRIVING METHOD THEREFOR

The present invention relates to display devices comprising pixels arranged in rows and columns, and to driving or addressing methods for such display devices. The present invention is particularly related to driving schemes in which column drive voltages are inverted to provide inversion schemes.

Liquid crystal display devices are well known, and usually comprise a plurality of pixels arranged in an array of rows and columns.

Conventionally the pixels are addressed or driven as follows. The rows of pixels are selected one at a time, starting with row one and working through the remaining rows in successive order, by application of a selection voltage.

This is sometimes referred to as switching of the rows by means of a switching voltage. For display devices, e.g. active matrix liquid crystal display devices

(AMLCDs), where switching of the pixels is implemented using thin film transistors (TFTs), such selecting or switching of individual rows is sometimes referred to as gating, as the switching voltage is applied to the gates of the transistors of the relevant row.

The pixels within the row currently selected are provided with respective display settings by virtue of respective data voltages being applied to each of the columns. Such data voltages are known by a number of names in the art, including data signals, video signals, image signals, drive voltages, column voltages, and so on.

Selection of each of the rows one by one, with driving of the columns as required during each row selection, provides display of one frame of the image being displayed. The display is then refreshed by a further frame being displayed in the same manner, and so on.

In addition, inversion schemes are implemented in many liquid crystal display devices. According to known inversion schemes, two different polarities of data voltage are employed (note these need not actually be positive and negative in an absolute sense, provided they produce opposite polarity voltages across the light modulating layer, e.g. liquid crystal layer, of the particular display device). Inversion schemes are employed to alleviate degradation of the liquid crystal material that would otherwise occur under continuous single-polarity operation.

Any given pixel has different polarities applied to it in different frames (usually alternating frames), i.e. the polarity for the pixel is inverted over time. In addition, in some inversion schemes pixels are also inverted on a positional basis with respect to other pixels, as follows.

Considering first one column of pixels, different pixels are provided with different polarities. Typically, alternate pixels down the column are provided with different polarity of data voltage. This is performed by varying the polarity in time with the row selection procedure. If all the columns are given the same distribution of drive voltage polarity (i.e. all the pixels in a row have the same polarity), the inversion scheme is known as a row inversion scheme. However, if additionally, in each row, adjacent pixels are provided with different polarity, then the inversion scheme is known as a pixel inversion scheme, dot inversion scheme or checker board inversion scheme. Thus in either pixel or row inversion schemes, the data voltages applied to a given column are inverted each time a new row is selected. However, the use of such schemes disadvantageously involves increased power consumption since power is consumed each time the data voltage applied to a column is inverted. Various addressing schemes have been devised for reducing the amount of power consumed by pixel or row inversion, by virtue of the schemes inverting the polarity less often than when the rows are selected on a conventional next row basis.

For example, US-A1 -2003/0107544 describes a pixel or row inversion scheme in which the order in which rows are selected is such that a first plurality of successive rows of those rows to be driven with a first polarity are driven consecutively, followed by a first plurality of successive rows of those rows to be driven with a second polarity, followed by a second plurality of successive rows of those rows to be driven with the first polarity, and so on. WO 03/030137 describes another pixel or row inversion scheme in which the order in which rows are selected is such that two consecutive odd numbered rows are driven consecutively, followed by two consecutive even numbered rows, followed by the next two consecutive odd numbered rows, followed by the next two consecutive even numbered rows, and so on, and where furthermore each second pair of consecutive odd numbered rows and each second pair of consecutive even numbered rows are selected in reverse order within the pair. In a separate example, WO 03/030137 describes yet another pixel or row inversion scheme, in which the order in which rows are selected is such that two consecutive odd numbered rows are driven consecutively, followed by two consecutive even numbered rows but selected in reverse order, followed by the next two consecutive odd numbered rows driven consecutively, followed by the next two consecutive even numbered rows but selected in reverse order, and so on.

A driving scheme having similarities to those of WO 03/030137 is described in WO 03/007285.

However, all of the above described addressing schemes which have been devised for reducing the amount of power consumed by pixel or row inversion tend to suffer, to some extent or other, from image artefacts introduced into the displayed image at rows where temporal changes in the driving polarity are made.

In WO 2006/006122, driving schemes are described in which rows are selected one at a time and column data voltages are inverted to provide inversion schemes for display devices comprising pixels arranged in rows and columns. The order in which rows are selected is such that a first group of first polarity rows is selected in a first order, a first group of second polarity rows is selected in a second order, a second group of first polarity rows is selected in the second order, and a second group of second polarity rows is selected in the first order, the first order being one of ascending or descending row number order, and the second order being the other of ascending or descending row number order. In one implementation described in WO 2006/006122, a method of driving the pixel array comprises selecting the rows of pixels one row at a time; and applying respective data voltages to the columns of pixels each time a row is selected, the polarity of the data voltage applied to a given column being inverted between a first polarity and a second polarity such that positionally successive rows are driven with a different polarity of data voltage; selecting the rows of pixels one row at a time comprising the following steps performed in the following order:

(i) successively selecting, in a first order, the rows of a first group of first polarity rows being positionally successive rows of those rows being driven with the first polarity; (ii) successively selecting, in a second order, the rows of a first group of second polarity rows being positionally successive rows of those rows being driven with the second polarity, the rows of the first group of first polarity rows and the rows of the first group of second polarity rows being positionally interlaced such that together they are a plurality of positionally successive rows; (iii) successively selecting, in the second order, the rows of a second group of first polarity rows being positionally successive rows of those rows being driven with the first polarity; and (iv) successively selecting, in the first order, the rows of a second group of second polarity rows being positionally successive rows of those rows being driven with the second polarity, the rows of the second group of first polarity rows and the rows of the second group of second polarity rows being positionally interlaced such that together they are a plurality of positionally successive rows which positionally succeeds the plurality of positionally successive rows of, together, the first group of first polarity rows and the first group of second polarity rows; wherein the first order is one of ascending or descending row number order, and the second order is the other of ascending or descending row number order. Each group of first polarity rows or second polarity rows may comprise three or more rows. In another implementation described in WO 2006/006122 the method comprises: selecting the rows of pixels one row at a time; and applying respective data voltages to the columns of pixels each time a row is selected, the polarity of the data voltage applied to a given column being inverted between a first polarity and a second polarity such that positionally successive rows are driven with a different polarity of data voltage; selecting the rows of pixels one row at a time comprising the following steps performed in the following order:

(i) successively selecting, in a first order, the rows of a first group of three or more first polarity rows being positionally successive rows of those rows being driven with the first polarity; and (ii) successively selecting, in a second order, the rows of a first group of three or more second polarity rows being positionally successive rows of those rows being driven with the second polarity, the rows of the first group of first polarity rows and the rows of the first group of second polarity rows being positionally interlaced such that together they are a plurality of positionally successive rows; wherein the first order is one of ascending or descending row number order, and the second order is the other of ascending or descending row number order.

Such methods help alleviate unwanted display artefacts. A cause of, or contribution to, the earlier described image artefacts arises since due to parasitic capacitance effects, the pixel responds to a root-mean-square voltage (Vrm_s) which would tend to vary smoothly with consecutive lines, but by selecting the rows temporally in a positionally non-consecutive order the variation in V_rms no longer occurs smoothly in terms of the positionally consecutive rows. The human eye is not very sensitive to a brightness variation between two positionally consecutive rows, and so driving schemes in which the average brightness over two positionally consecutive rows remains reasonably constant over the course of a larger number of positionally consecutive rows (for a given uniform data level) will tend to reduce the level of image artefacts introduced by a power saving driving scheme.

In order to implement the schemes mentioned above, the rows are grouped into sets. For example, a first set may comprise the first 6 even rows, and the next set may comprise the first 6 odd rows. In this example, in order to make the row addressing cycles fit the total number of rows, the total number of rows needs to be a multiple of 12. The physical number of rows of pixels may not satisfy this relationship, as the physical display design may not be designed for the particular drive scheme to be used. In order to overcome this problem, dummy rows can be added, so that the total number of rows is the desired multiple of 12 (in this example). Row addressing operations are carried out for these dummy rows so that the repetitive cycle of the row addressing circuitry does not need to be broken for the addressing of the last rows of the display.

While the various schemes disclosed in WO 2006/006122 reduce image artefacts, the inventors have identified one problem which relates to the transition between frames.

Each frame has the opposite polarity pattern applied to the columns compared to the previous frame. For example, if the first set of rows of one frame is of positive polarity and the last set is of negative polarity, then the first set of rows of the next frame will be of negative polarity and the last set will be of positive polarity.

This invention is based on the recognition that these prolonged periods of equal polarity, which bridge across the transitions between frames, can also give rise to image artefacts.

These image artefacts can be caused in AMLCDs by the way the columns and counter (common) electrode are driven during the frame blanking interval. In particular, the last column data applied is retained during the frame blanking interval, and this causes the prolonged period of the same polarity.

This is particularly significant for small AMLCDs, such as those used in mobile phones, where problems may be exacerbated by the low power drive schemes mentioned above.

According to one aspect of the present invention there is provided a method of driving an active matrix liquid crystal display device having an array of pixels arranged in rows and columns, the method comprising selecting rows of pixels in a sequence and during each row selection, applying column voltages to the columns of pixels, wherein for one frame of image data, the sequence of rows comprises: a first set of rows for which a first set of column voltages of a first polarity are applied, followed by a second set of rows for which a second set of column voltages of a second, opposite polarity are applied, followed by further sets of rows, wherein the polarity of column voltages for each set of rows is opposite to the previous set of rows, and wherein an odd number of sets of column voltages are applied within the frame.

This drive method enables unwanted display artefacts to be reduced by providing a transition between polarity signals between successive frames. Thus, an odd number of sets of column voltages are applied, corresponding to an odd number of sets of rows, although some of these rows may be dummy rows.

Each set preferably comprises at least 4 rows, for example least at least 6 rows. In one example, each set comprises either 6 consecutive odd numbered rows or 6 consecutive even numbered rows, the sets together defining all rows.

For one group of sets, the rows can be selected in a row number ascending order, and for another group of sets the rows can be selected in a row number descending order. The rows may not all comprise physical rows of pixels (as mentioned above), and dummy rows may be used. Thus, selecting rows of pixels for addressing may comprise selecting physical rows of pixel and dummy rows of pixels. The addressing of at least some of the dummy rows of pixels can then take place in a frame blanking time period. In one example, the number of dummy rows comprises the difference between the number of physical rows and a larger odd integer multiple of the number of rows in each set. This means that dummy rows are used to bring the total number up to the desired odd multiple.

The last set of rows can be addressed for a first time period corresponding to the time used to address the other sets of rows, followed by a second time period of first duration with the same polarity as during the first time period, followed by a third time period of the same first duration with the opposite polarity as during the second time period, the frame blanking time period ending after the third time period.

This arrangement makes sure that the last set of rows and the first set of rows of the next frame are addressed with opposite polarity signals and for equal lengths of time.

Alternatively, the last set of rows can be addressed for a first time period corresponding to the time used to address the other sets of rows, followed by a second time period with a common electrode voltage, the second time period lasting for the remainder of the frame blanking time period, This arrangement makes sure that the last set of rows and the first set of rows of the next frame are addressed with opposite polarity signals and for equal lengths of time corresponding to the time period allocated to other sets of rows. For any additional time period within the frame blanking time, the common electrode voltage is used. The invention also provides a drive circuit for an active matrix liquid crystal display device having an array of pixels arranged in rows and columns, the circuit being arranged to implement the method of any preceding claim.

The invention also provides an active matrix liquid crystal display device comprising an array of pixels arranged in rows and columns, and a drive circuit of the invention for driving the array of pixels.

Further features and advantages of the present invention will become apparent from reading of the following description of preferred embodiments of the present invention, given by way of example only, and with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an active matrix liquid crystal display device in which embodiments of the invention are implemented;

FIG. 2a shows a positive polarity data voltage being applied to a pixel of the display device of FIG. 1 ; FIG. 2b shows a negative polarity data voltage being applied to the same pixel of the display device of FIG. 1 ; FIG. 3 shows a row inversion scheme applied to the display device of FIG. 1 ;

FIG. 4 shows a pixel inversion scheme applied to the display device of FIG. 1 ; FIG. 5 shows a driving scheme;

FIG. 6 is a flowchart showing process steps carried out by display driver apparatus implementing the driving scheme of FIG. 5;

FIG. 7 shows a driving scheme of the invention;

FIG.s 8A and 8B show in schematic form known driving schemes which can also be modified using the teaching of the invention;

FIG. 9 shows the brightness variation for the drive scheme of FIG. 8B;

FIG. 10 shows the effect of applying the invention to the drive scheme of FIG. 8B on the brightness variation; and

FIG. 11 is used to show different timing approaches for implementing the invention.

The general structure and operation of an AMLCD are well known. A typical example is described in US-A-5130829 whose whole contents are incorporated herein by way of reference material, as are the contents of WO2006/006122, WO 03/030137 and WO 03/007285. Briefly, such a display device comprises an array of pixels, arranged in rows and columns, each comprising an electro-optic display element and an associated switching device, usually in the form of thin film transistor (TFT). Each display element comprises a pixel electrode and a respective portion of a counter electrode, common to all the pixels in the array, together with liquid crystal material between the respective electrodes. The pixels are connected to sets of row and column address conductors, each pixel being located adjacent the intersection between a respective conductor of each set, via which the pixels are addressed with selection (scanning) signals being applied to each of the row conductors in sequence to select that row and with data (video information) signals being supplied in synchronism with row selection via the column address conductors to the pixels of the selected row and determining the display outputs of the individual pixels of the row concerned. The data signals are derived by appropriately sampling an input video signal in a column address circuit coupled to the column address conductors. Each row of pixels is addressed in turn so as to build up a display from the whole array in one frame (field) period, with the array of pixels being repeatedly addressed in this manner in successive frames. There is a need to refresh the pixels regularly with video information. In the case of an AMLCD, the polarity of the data signal voltage applied to the display elements needs to be inverted periodically in order to prevent degradation of the LC material. In simple drive schemes, this may be done for example after each field (so-called field inversion) or after each row has been addressed as well (so-called line or row inversion).

AMLCDs typically can suffer from many unwanted display artefacts which degrade the quality of the display image. These display artefacts can result from a variety of causes, many of which are due to parasitic capacitance effects present in the pixel array. Certain image artefacts may be caused in particular by the way in which the pixel columns and the counter electrode are driven during the frame blanking interval, i.e. the period between successive frame address periods for the pixel array in which all rows are driven. This is especially significant for relatively small AMLCDs, such as those employed as mobile phones, where the problems may be aggravated by certain kinds of drive schemes intended to reduce power consumption levels. The present invention is concerned with alleviating this kind of problem.

FIG. 1 is a schematic diagram of an active matrix liquid crystal display device in which embodiments of the invention are implemented. The display device, which is suitable for displaying video pictures, comprises an active matrix addressed liquid crystal display panel 10 having a row and column array of pixels which consists of m rows (1 to m) with n horizontally arranged pixels 12 (1 to n) in each row. Only a few of the pixels are shown for simplicity.

Each pixel 12 is associated with a respective switching device in the form of a thin film transistor, TFT, 11. The gate terminals of all TFTs 11 associated with pixels in the same row are connected to a common row conductor 14 to which, in operation, selection (gating) signals are supplied. Likewise, the source terminals associated with all pixels in the same column are connected to a common column conductor 16 to which data (video) signals are applied. The drain terminals of the TFTs are each connected to a respective transparent pixel electrode 20 forming part of, and defining, the pixel. The conductors 14 and 16, TFTs 11 and electrodes 20 are carried on one transparent plate while a second, spaced, transparent plate carries a counter electrode common to all the pixels (hereinafter referred to as the common electrode). Liquid crystal is disposed between the plates.

The display panel is operated in conventional manner. Light from a light source disposed on one side enters the panel and is modulated according to the transmission characteristics of the pixels 12. The device is driven one row at a time by scanning the row conductors 14 with a selection (gating) signal so as to turn on the rows of TFTs in turn and applying data (video) signals to the column conductors for each row of picture display elements in turn as appropriate and in synchronism with the selection signals so as to build up a complete display frame (picture). The order in which the rows are selected during the scanning will be described below. Using one row at time addressing, all TFTs 11 of the selected row are switched on for a preselected period determined by the duration of the selection signal corresponding to a video signal line time during which the video information signals are transferred from the column conductors 16 to the pixels 12. Upon termination of the selection signal, the TFTs 11 of the row are turned off for the remainder of the frame period, thereby isolating the pixels from the conductors 16 and ensuring the applied charge is stored on the pixels until the next time they are addressed in the next frame period.

The row conductors 14 are supplied in their order of selection with selection signals by a row driver circuit 20 comprising a digital shift register controlled by regular timing pulses from a timing and control circuit 21. In the intervals between selection signals, the row conductors 14 are supplied with a substantially constant reference potential by the drive circuit 20. Video information signals are supplied to the column conductors 16 from a column driver circuit 22, here shown in a highly simplistic form, comprising one or more shift register/sample and hold circuits. The circuit 22 is supplied with video signals from a video processing circuit 24 and timing pulses from the circuit 21 in synchronism with row scanning to provide serial to parallel conversion appropriate to the row at a time addressing of the panel 10. Other details of the liquid crystal display device, except where otherwise stated below in relation to the order in which the rows are selected in relation to their column polarity, may be as per any conventional active matrix liquid crystal display device, and are in the present particular embodiments the same as, and operate the same as, the liquid crystal display device disclosed in aforementioned US 5,130,829.

The way in which the data voltage, as applied to the columns, is varied between two polarities, will now be explained with reference to FIGS. 2a and 2b. FIGS. 2a and 2b each show schematically (not to scale) an above mentioned pixel 12, formed (inter-alia) from a pixel electrode 20, the (corresponding portion of) the above mentioned common electrode (indicated by reference numeral 32 in FIGS. 2a and 2b), and (the corresponding portion of) the liquid crystal layer therebetween (indicated by reference numeral 36 in FIGS. 2a and 2b).

The common electrode 32 is maintained at a constant reference voltage, in this example 8V, as shown in both FIGS. 2a and 2b. FIG. 2a shows the case when a positive polarity data voltage is applied to the pixel. In this example a voltage of 11V is applied to the pixel electrode 20, as shown, providing a potential difference across the liquid crystal layer of +3V (referenced to the common electrode 32). In this example, this is the positive polarity. In a grey scale display the magnitude of this potential difference provides the relevant grey scale, due to voltage magnitude dependence of the electro-optic effect of the light modulating layer, i.e. the liquid crystal layer 36. However, if the display were binary, then the magnitude of the potential difference would simply correspond to a fully on state. FIG. 2b shows the case when a negative polarity data voltage is applied to the pixel. More particularly, the situation shown is when the same magnitude (3V) of potential difference is required as was applied in the FIG. 2a example. Thus in this case a voltage of 5V is applied to the pixel electrode, resulting in the required -3V potential difference across the liquid crystal layer (referenced to the common electrode 32).

It is noted that in both FIGS. 2a and 2b the voltage applied to the pixel electrode 20 is, in an absolute sense, positive. However, the 5V signal provides a negative polarity across the liquid crystal layer 36, whereas the 11 V signal provides a positive polarity across the liquid crystal layer 36. Thus, in this specification, the terminology positive and negative polarity of data voltage is to be understood to include examples such as those described with reference to FIGS. 2a and 2b, as well as other examples where, say, the common electrode is held at OV, and the positive and negative polarity applied data voltages are indeed positive and negative in an absolute sense as well as in the sense of the resulting potential drop across the light modulating layer.

Also, although in the example shown in FIGS. 2a and 2b, the common electrode 32 is held at a d.c. potential (here 8V), in other drive schemes (known as common electrode drive schemes) the common electrode is driven with an inverting square waveform, and the present invention may equally be implemented with such schemes.

Either a row inversion scheme or a pixel inversion scheme may be used. It is convenient to first describe in more detail what is meant by these. FIG. 3 shows a row inversion scheme applied to the above described device. FIG. 3 shows, for one frame, the polarity (where a "1" indicates a positive polarity, and a "-1" indicates a negative polarity) of data voltage (indicated in general by reference numeral 44) for each of the columns of the above described device (for clarity only the first four columns are shown) as applied to each row number (indicated in general by reference numeral 42). For clarity only the first 16 rows, i.e. rows 1-16 are shown.

For column 1 , row 1 is positive, and thereafter the polarity is alternated for successive rows, i.e. row 2 is negative, row 3 is positive, and so on. All the other columns, e.g. columns 2, 3 and 4 as shown, have the same polarities for the same rows as per column 1. Thus, as can be seen, any given row has the same polarity across all the columns, i.e. the inversion takes place on a row basis, hence the terminology "row inversion" is used to describe this arrangement.

FIG. 4 on the other hand shows a pixel inversion scheme applied to the above described device. FIG. 4 also shows, for one frame, the polarity (where again a "1" indicates a positive polarity, and a "-1" indicates a negative polarity) of data voltage (indicated in general by reference numeral 44) for each of the columns of the above described device (for clarity only the first four columns are shown) as applied to each row number (indicated in general by reference numeral 42). For clarity only the first 16 rows, i.e. rows 1-16 are shown. For column 1 , row 1 is positive, and thereafter the polarity is alternated for successive rows, i.e. row 2 is negative, row 3 is positive, and so on. So far this is the same as per FIG. 3. However, as shown in FIG. 4, for column 2, the positive and negative polarities are reversed compared to column 1. This pattern is repeated for alternating columns, i.e. column 3 is the same as column 1 , column 4 is the same as column 2, and so on. Thus, as can be seen, any two neighbouring pixels are of opposite polarity, hence the terminology "pixel inversion" is used to describe this arrangement.

In another form of pixel inversion, applied to some colour liquid crystal displays, three adjacent columns (one for each of the colours red, blue and green) have a first polarity for a given row, then the next three adjacent columns have the other polarity, and so on.

The situation for each of the above described row or pixel inversion schemes has been explained in terms of the polarities applied in one frame. In the next frame, the positive polarities and negative polarities are reversed. A particularly preferred drive scheme, as described in WO

2006/006122, applied to any one of the above described row or pixel inversion schemes will now be discussed. For clarity, the embodiments will be described in terms of column 1 (e.g. of FIGS. 3 and 4) only.

FIG. 5 shows a driving scheme according to a first preferred embodiment according to IB 2005/052221. FIG. 5 shows, for one frame, the polarity (where a "1" indicates a positive polarity, and a "-1" indicates a negative polarity) of data voltage (indicated by reference numeral 44) for a single column of the above described device as applied to each row number (indicated by reference numeral 42). For clarity only the first 24 rows, i.e. rows 1-24 are shown. FIG. 5 further shows the temporal order in which the rows are selected, as indicated by the time arrow 46. Thus, the first row to be selected is that whose polarity is shown in the far left column, i.e. row 2 which is driven with a positive polarity, then row 4 is selected and driven with a positive polarity, and so on. Thus it can be seen that the order of selection of the 24 rows shown in FIG. 5 is as follows (where +ve indicates positive polarity and - ve indicates negative polarity): row 2 (+ve), row 4 (+ve), row 6 (+ve), row 8(+ve), row 10 (+ve), row 12

(+ve), row 11 (-ve), row 9 (-ve), row 7 (-ve), row 5 (-ve), row 3 (-ve), row 1 (- ve), row 24 (+ve), row 22 (+ve), row 20 (+ve), row 18 (+ve), row 16 (+ve), row 14 (+ve), row 13 (-ve), row 15 (-ve), row 17 (-ve), row 19 (-ve), row 21 (-ve), row 23 (-ve). The order of selection of the rows is based on groups of rows comprising six rows, such that a first group comprising the first six rows to be driven with positive polarity (i.e. rows 2, 4, 6, 8, 10 and 12) is selected in ascending row number order (i.e. in the order 2, 4, 6, 8, 10 12); following which a second group comprising the first six rows to be driven with negative polarity (i.e. rows 1 , 3, 5, 7, 9 and 11 ) is selected in descending, i.e. reverse, row number order (i.e. in the order 11 , 9, 7, 5, 3, 1 ); following which a third group comprising the next six rows to be driven with positive polarity (i.e. rows 14, 16, 18, 20, 22 and 24) is selected in descending, i.e. reverse, row number order (i.e. in the order 24, 22, 20, 18, 16, 14); following which a fourth group comprising the next six rows to be driven with negative polarity (i.e. rows 13, 15, 17, 19, 21 , 23) is selected in ascending row number order (i.e. in the order 13, 15, 17, 19, 21 , 23). The remaining rows of the device, i.e. row 25 onwards (not shown in FIG. 5) are selected by repeating this cycle of: a next positive polarity group comprising the next six rows to be driven with positive polarity is selected in ascending row number order; following which a next negative polarity group comprising the next six rows to be driven with negative polarity is selected in descending, i.e. reverse, row number order; following which a next positive polarity group comprising the next six rows to be driven with positive polarity is selected in descending, i.e. reverse, row number order; following which a next negative polarity group comprising the next six rows to be driven with negative polarity is selected in ascending row number order; and so on.

In the arrangement shown in FIG. 1 , the row driver circuit 20, the timing and control circuit 21 , the column driver circuit 22 and the video processing unit 24 may together be considered to form a display driver apparatus or circuit. Such a display driver apparatus may be adapted in any suitable manner to implement the row selection ordering of this embodiment. For example, the row driver circuit 20 may be programmed to select the rows in the order described above, the column driver circuit may be adapted to switch the column polarities as described, and the video processing circuit may be adapted by provision of a buffer or memory (not shown) for storing video data for those rows not selected in their numerical order, i.e. the buffer may store the video data for rows 1 , 3, 5, 7, 9 and 11 whilst rows 2, 4, 6, 8, 10 and 12 are selected, then use the stored video data when rows 1 , 3, 5, 7, 9 and 11 are later selected after rows 2, 4, 6, 8, 10 and 12.

FIG. 6 is a flowchart showing process steps carried out by the display driver apparatus in this embodiment to provide, for a single frame, the row ordering and polarities shown in FIG. 5, for the row inversion case.

At step s2, row 2 is selected and a positive polarity data voltage is applied to each column. Row 2 is selected by the row driver circuit 20 applying a selection voltage to row 2. Application of the positive polarity data voltage is implemented as follows. A video signal (i.e. specifying the magnitude of the data voltage to be applied to each column) is provided by the video processing circuit 24 and effectively sampled at the correct time for each column by virtue of the column driver circuit 22 connecting the video signal to the respective columns at the right times, under timing control of the timing and control circuit 21. Whether the polarity is positive or negative is controlled and implemented by a combination of the column driver circuit 22 and the video processing circuit 24 under the control of the timing and control circuit 21. If the column driver circuit 22 is only implementing row and field inversion it may be supplied with video signals from the video processing circuit 24 which are inverted in polarity either every field (frame) or every field

(frame) and every row. In this case the video processing circuit 24 carries out the switching between the two drive voltage polarities.

If the column driver circuit 22 is implementing pixel inversion then the video processing circuit 24 supplies the column driver circuit 22 with two sets of video signals. At any moment in time one of these sets is positive and the other negative. Signals from one or other of these two sets of inputs are directed to alternate columns in the display in order to provide the required drive polarities. The video processing circuit 24 may swap over the polarity of these two sets of signals row by row and at the end of each field, although this function may also be integrated into the column driver circuit 22.

At step s4, the next row is selected, namely row 4, as this is the next consecutive row of the first group of six rows which are to have positive polarity applied thereto, and a positive polarity data voltage is applied to each of the columns.

This process is repeated (indicated by a broken arrow between step s4 and s6 in FIG. 5) for the remaining rows of the first group of six rows which are to have positive polarity applied thereto until, at step s6, row 12 is selected and a positive polarity data voltage is applied to each of the columns.

In this embodiment, the number of rows forming a "group" is six, hence the next six rows to be selected will be the first group of negative polarity rows

(i.e. rows 1 , 3, 5, 7, 9, and 11 ). Furthermore, as described above, this group will be selected in descending, i.e. reverse, row number order (i.e. 11 , 9, 7, 5,

3, 1 ).

Thus, at step sδ, row 11 is selected and a negative polarity data voltage is applied to each column. Next, at step s10, row 9 is selected and a negative polarity data voltage is applied to each column. This process is repeated (indicated by a broken arrow between step s10 and s12 in FIG. 5) for the remaining rows of the first group of six rows which are to have negative polarity applied thereto until, at step s12, row 1 is selected and a negative polarity data voltage is applied to each of the columns.

The next six rows to be selected will be the next group, i.e. the second group, of positive polarity rows (i.e. rows 14, 16, 18, 20, 22 and 24). Furthermore, as described above, this group will be selected in descending, i.e. reverse, row number order (i.e. in the order 24, 22, 20, 18, 16, 14).

Thus at step s14, row 24 is selected and a positive polarity data voltage is applied to each column. Next, at step s16, row 22 is selected and a positive polarity data voltage is applied to each column. This process is repeated (indicated by a broken arrow between step s16 and s18 in FIG. 5) for the remaining rows of the second group of six rows which are to have positive polarity applied thereto until, at step s18, row 14 is selected and a positive polarity data voltage is applied to each of the columns.

The next six rows to be selected will be the next group, i.e. the second group, of negative polarity rows (i.e. rows 13, 15, 17, 19, 21 , 23). As described above, this group will be selected in ascending row number order (i.e. in the order 13, 15, 17, 19, 21 , 23).

Thus, at step s20, row 13 is selected and a negative polarity data voltage is applied to each column. Next, at step s22, row 15 is selected and a negative polarity data voltage is applied to each column. This process is repeated (indicated by a broken arrow between step s22 and s24 in FIG. 5) for the remaining rows of the second group of six rows which are to have negative polarity applied thereto until, at step s24, row 23 is selected and a negative polarity data voltage is applied to each of the columns. As described above, the remaining rows are selected and have positive or negative polarity applied to the columns in a repeat of the cycle described for rows 1-24 by allocating the rows into groups of six consecutive rows of a given polarity, then selecting them (and applying appropriate polarity data voltage to the columns) according to the cycle of: the next group of positive polarity rows selected in ascending row number order (the first these being shown in FIG. 5 as step s26, in which row

26 is selected and a positive polarity data voltage is applied to each column), then the next group of negative polarity rows selected in descending row number order, then the next group of positive polarity rows selected in descending row number order, then the next group of negative polarity rows selected in ascending row number order, and so on (indicated by a broken arrow between step s26 and s28 in FIG. 5) until at step s28 the last to be selected row, i.e. the (m-1 )th row (in this embodiment, where the display has say 600 rows by 800 columns, row 599) is selected and a negative polarity data voltage is applied to each column (the mth row, here row 600, having been selected previously as part of the last group of positive polarity rows). This completes addressing of this frame. During addressing of the next frame, the positive and negative polarities are reversed, but the rows are selected in the order given above.

In the above described process, the row is selected then the voltage is applied to the column. Alternatively, this order may be reversed. Whichever order is used, it is usual for the column voltage to be held until after the row has been deselected.

The above described driving scheme leads to advantageous effects, as described in WO 2006/006122. As with, for example, the driving scheme of WO 03/030137, the driving scheme leads to a reduction of power consumption.

In addition, the driving scheme provides an advantageous reduction (or tendency to reduce) in visible horizontal bands or other image artefacts. In particular, groups of six rows of the same polarity can be driven consecutively, hence saving power, but artefacts in the form of groups of six rows or at the interface of groups of six rows are removed or at least tend to be reduced.

It should be borne in mind that the scheme has been described in detail for a given frame, however the polarities will then reverse in the next frame. Hence, whereas in the frame described above, the even numbered rows have positive polarity, in the next frame the odd numbered rows will have positive polarity.

Although the particular driving scheme described with reference to figures 5 and 6 offers advantages over conventional schemes and the improved schemes intended to reduce power consumption discussed in the introduction, such as that described in WO 03/030137 for example, in alleviating problems with unwanted display artefacts, problems with particular kinds of unwanted display artefacts can, in certain circumstances, still occur. Small AMLCDs, particularly those designed for mobile use, tend to have significant column-pixel coupling capacitance. If severe, this can lead to issues such as vertical cross talk, but at lower values it can lead to some more subtle issues such as every second line in the display image (each row of pixels producing a respective line) being brighter than average, leading to a fine horizontal stripe image artefact. The magnitude of the brightness variation is inversely proportional to the number of lines in the display image, and so is most visible in small AMLCDs, which generally have fewer lines than large AMLCDs.

This issue is made significantly worse when low power drive schemes, such as those of WO 03/030137 and WO 2006/006122 described above, are employed where the columns and common electrode are inverted every n lines instead of every line, which reduces the power consumption due to the inversion scheme. This operation, however, also serves at the same time to magnify the brightness variation by the factor n (the number of rows addressed in each inversion period).

In these known methods, then in low power modes of operation the columns and common electrode are generally undriven, or left at the final addressed value, during the frame blanking interval in order to save power. It is now understood, that this can make these image artefacts significantly worse. Thus, these image artefacts are particularly visible for small AMLCDs when used in a low power, standby, mode. The present invention is based on this insight.

In accordance with the present invention, driving of the column conductors, 16, and the common electrode, 20, of the AMLCD during the frame blanking interval is carefully selected so as to eliminate, or at least reduce, the unwanted artefacts, while at the same time not significantly increasing power consumption. The key to eliminating, or reducing, the image artefacts is to equalise the effects of the capacitive coupling of the columns to all pixels. This is achieved by driving the columns and common electrode with the correct inversion mode during the frame blanking period. The simplest, and lowest power, way to accomplish this is to invert the columns/common electrode an odd number of times in each frame, assuming the inversions are equally spaced. Then they are driven to the same potential. After they are driven to the same potential, they may be left in a high impedance state, thereby allowing the drive buffers to enter a low power idle mode.

To achieve the correct number of inversions, the columns and common electrode may be driven for several dummy row periods after the addressing of the last physical pixel row. This will at most require one further inversion, so does not have a significant power consumption. More complex schemes in the frame blanking interval are possible, while still employing the general principle of driving the columns and counter electrode for part of the frame blanking time to achieve cancellation or reduction of the artefacts.

As an example embodiment of the present invention, consider a 208 row display, which is to be addressed in the manner described with reference to figures 5 and 6 with inversion of the columns/common electrode every 6 lines, (so-called "6 line dancing scan"). In this scheme, then normally it would be needed to extend the physical display to an even multiple of 6 logical rows for the addressing scheme to work, so the display would be addressed with 216 logical rows (36 inversions). This, however, results in the image artefact described above. By means of the proposed drive scheme, in accordance with an embodiment of the invention, the display is addressed with an extra inversion period, so 222 logical rows (37 inversions), and results in the elimination of the image artefact. The 222 line example of the invention is explained with reference to

Figure 7, which shows the order of addressing the last rows, 205 to 222. Rows 205 to 216 form the last inverted "V" scan corresponding to the bottom right of Figure 5. Only the negative polarity cycle is shown in full.

As mentioned above, rows 209 onwards are dummy rows, and these are the rows addressed at times 70 shown. These dummy rows are addressed using the normal scan operation, and the purpose is to enable the same repeating row pattern to be used for the full display array. Thus, the dummy rows corresponding to times 70 are "addressed" during the normal frame time. These dummy rows bring the total number of rows of the addressing sequence up to a multiple of 12, namely 216. The invention provides the additional dummy rows 217 to 222, and these are addressed over time period 72. This time period is within the frame blanking period, and ensures that the total number of inversions is odd (37 inversions in this example). In this example, the column data is inverted at a uniform rate throughout the frame period and the frame blanking period, corresponding to the line time for 6 rows.

After the period 72, the first set of even rows will be addressed for the next frame, and with negative polarity.

The naming of the rows in the frame blanking period is somewhat arbitrary (as it simply represents the provision of data to the column data lines but with no physical rows), and the dummy rows 72 could for example all be named as even rows. Thus, it will be apparent to those skilled in the art that this drive scheme does not complicate the row driver architecture, and enables a repeating cyclic row addressing scheme to be employed and which simply restarts at the beginning of each frame with opposite polarity. The invention has been described above as applied to one specific so- called dancing row addressing scheme, but the invention can be employed in other schemes.

Figure 8A shows in more schematic format the row addressing scheme of Figure 5, as described in WO 2006/006122. Figure 8B shows a more conventional dancing row addressing scheme.

In Figure 8B, a group of rows (for example 12 as in the previous example, is addressed with the even rows in increasing sequence with one polarity, then with the odd rows in increasing sequence with the opposite polarity. In the next group of 12, the even rows are addressed in decreasing sequence with the one polarity, then the odd rows are addressed in decreasing sequence with the opposite polarity. These schemes both decrease the column data inversion rate compared to a standard line by line inversion, for example by a factor of 6 in the examples given, and this provides a power saving. The specific dancing row addressing schemes selected aim to reduce image artefacts which result from this reduced inversion rate. The main image artefact is brightness banding, in which every second line is brighter. Thus, the display output has dark and light bands. The brightness variation is found to be proportional to the ratio of the column data inversion time period to the frame time. Thus, the effect is worst for small displays (a small number of lines gives a relatively long line time and therefore relatively long column data inversion time) and for row addressing schemes which extend the inversion time (as in the examples above, by a factor of 6).

The effect is also worse in high aperture displays, as the effect is caused by column to pixel coupling capacitance, which is worse in smaller displays. One way to represent this effect is to illustrate the variation in brightness output for different rows when the data for a uniform brightness image is applied to the display.

Figure 9 shows the brightness variation for the display drive scheme of Figure 8B, with the conventional even number of inversions per frame. This is known as a dancing twisted row address scheme.

As shown in Figure 9, a uniform data voltage applied to the columns gives rise to an LC voltage (the y-axis) which varies between approximately 3.153 and 3.188, corresponding to a 1.1% variation. Although this variation is small, it is generally seen between adjacent rows, which highlights the visual artefact.

Figure 10 shows the effect of applying the invention, to provide an odd number of inversions. The total brightness variation has reduced, so that the range of voltages applied to the LC cells is 3.163 to 3.179, giving a fluctuation of 0.51%. As important is the fact that the brightness variations are spread over the sets of 12 rows, so that the banding is spread over a larger area. This is much less noticeable to the human eye. In the example above, it has been assumed that the additional inversion of extra dummy lines can be fitted perfectly into the frame blanking period. Typically, the frame time is 16.6ms (60Hz), and the frame blanking time is approximately 1ms. For a small display of 208 lines, this 1 ms frame blanking time may therefore correspond to approximately 13 line times (15.6ms/208 lines = 0.075ms line time).

Figure 11 is used to show the timing of inversion in different possible configurations. Figures 11A to C each show the polarity of column data voltage applied to the last set of rows (a set comprising six sequential odd or even rows in the examples above), the polarity applied to dummy rows during the frame blanking period, and the polarity applied to the first set of the next frame.

Figure 11A shows the situation when the frame blanking period is substantially equal to the line times for one set of rows. In this case, the polarity can simply invert for the frame blanking period and then restart at the next frame.

If the frame blanking period is much longer, there is a number of possibilities. Figure 11 B shows that after the time period T corresponding to the line times for a set of rows, a common electrode voltage (half way between the voltages for the opposite polarities) can be applied for the remainder of the frame blanking period.

Figure 11C shows that after the time period T corresponding to the line times for a set of rows, the remainder t of the frame blanking time period can be divided into two, the first half t/2 continuing the polarity of the preceding part of the frame blanking period, and the second half t/2 adopting the opposite polarity which is then applied to the first set of rows of the next frame. In this way, two longer inversions are provided, but of equal length to minimise the image artefacts. The invention is based on the recognition that long periods of column data addressing with the same polarity should be avoided during the frame blanking period, and provides drive schemes in which the frame blanking period is used as part of the addressing scheme to provide an odd total number of inversions. This provides a transition between frames which maintains the same, or substantially the same, polarity inversion rate across frame boundaries. The invention requires one extra inversion in the drive scheme, with a small additional power consumption, but provides significant reduction in image artefacts. In the example above, 14 dummy rows are added to a physical display of 208 rows to reach 222 rows. It will be appreciated that 210 rows is also an odd multiple of 6, so that only 2 dummy rows may be added, but this will in practice be shorter than the typical frame blanking period.

Detailed examples have been given with six rows per set, but this may be 4, 6, 8, 10 or indeed any other number. The higher the number, the greater the power savings because the inversion rate is reduced, but at the expense of worsened image artefacts.

Various other modifications and variations are possible, as will be appreciated by persons skilled in the art. For example, drive schemes proposed in WO 2006/006122 other than the particular one described above may be used.

Moreover, the invention may be applied to alternative inversion drive schemes intended to reduce power consumption, such as those described in WO 03/030137 and the drive scheme described in WO 03/007285. The invention may also be applied to other driving schemes in which different polarities are applied to different rows in a given column in arrangements other than alternate rows being different polarities. In such cases groups of rows of a given polarity are selected in the orders described above. In the above embodiments, the components and operation of the display driver apparatus are an example using an analogue column driver circuit 22. However, in other embodiments, a digital column driver may be used, in particular the digital column driver may comprise a digital shift register and a digital-to-analogue (D/A) converter for each column. In these cases, the display driver apparatus will be adapted as required.

Finally, although the above embodiments have all been described in relation to a particular liquid crystal display device, it will be appreciated that the row selection of the present invention may also be applied in other liquid crystal display devices. For example, in the above embodiments, the liquid crystal display device is a transmissive device. However, in other embodiments the liquid crystal display device may be a reflective device or a transflective device.

Claims

1. A method of driving an active matrix liquid crystal display device having an array of pixels (12) arranged in rows and columns, the method comprising selecting rows of pixels in a sequence and during each row selection, applying column voltages to the columns of pixels, wherein for one frame of image data, the sequence of rows comprises: a first set of rows (rows 2,4,6,8,10,12) for which a first set of column voltages of a first polarity are applied, followed by a second set of rows (rows 11 ,9,7,5,3,1 ) for which a second set of column voltages of a second, opposite polarity are applied, followed by further sets of rows, wherein the polarity of column voltages for each set of rows is opposite to the previous set of rows, and wherein an odd number of sets of column voltages are applied within the frame.

2. A method as claimed in claim 1 , wherein each set comprises at least 4 rows.

3. A method as claimed in claim 1 , wherein each set comprises at least 6 rows.

4. A method as claimed in claim 3, wherein each set comprises either 6 consecutive odd numbered rows or 6 consecutive even numbered rows, the sets together defining all rows.

5. A method as claimed in claim 4, wherein for one group of sets the rows are selected in a row number ascending order, and for another group of sets the rows are selected in a row number descending order.

6. A method as claimed in any preceding claim, wherein selecting rows of pixels for addressing comprises selecting physical rows of pixel and dummy rows of pixels (70,72).

7. A method as claimed in claim 6, wherein the addressing of at least some of the dummy rows of pixels (72) takes place in a frame blanking time period.

8. A method as claimed in claim 6 or 7, wherein the number of dummy rows (70,72) comprises the difference between the number of physical rows and a larger odd integer multiple of the number of rows in each set.

9. A method as claimed in claim 6 or 7 or 8, wherein the last set of rows is addressed for a first time period (T) corresponding to the time used to address the other sets of rows, followed by a second time period of first duration (t/2) with the same polarity as during the first time period, followed by a third time period of the same first duration (t/2) with the opposite polarity as during the second time period, the frame blanking time period ending after the third time period.

10. A method as claimed in claim 6 or 7 or 8, wherein the last set of rows is addressed for a first time period (T) corresponding to the time used to address the other sets of rows, followed by a second time period with a common electrode voltage, the second time period lasting for the remainder of the frame blanking time period.

11. A drive circuit (22) for an active matrix liquid crystal display device having an array of pixels arranged in rows and columns, the circuit being arranged to implement the method of any preceding claim.

12. An active matrix liquid crystal display device comprising an array of pixels (10) arranged in rows and columns, and a drive circuit (22) as claimed in claim 11 for driving the array of pixels.