JP3048814B2 - Step up down converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a step-up / down converter.

[0002]

2. Description of the Related Art At present, various devices require different currents and voltages depending on the use conditions thereof. Therefore, a current adapter having a multi-voltage output circuit (for example, Japanese Patent Application Laid-Open No. Hei 5-297962). See).

[0003] In recent years, portable electronic devices that have become widespread have been required to be able to use not only commercial alternating current but also direct current obtained from a DC socket in a vehicle as the current. The output voltage of such a DC power supply differs depending on the vehicle type (+ 10.5V or + 16V),
On the other hand, in the case of an electronic device, for example, 20 V at 2.
It is required to switch and use the first current voltage value of 0A, the second current voltage value of 2.4A at 16V, and the third current voltage value of 3.4A at 10V. It should be noted that such switching of the current and voltage values is specifically performed depending on the presence or absence of a secondary battery built in the electronic device, the magnitude of the load based on the operation state of the electronic device, and the like.

For this reason, a step-up / down converter is used for a power adapter of this kind of electronic equipment.

FIG. 3 is a circuit diagram for explaining the principle of this type of converter. This converter converts the DC voltage energy supplied from the input terminal into a P-type channel FET.
Switching element Q1 and N-type channel FE
The switching element Q2 made of T is made conductive (on) to be temporarily stored in an inductance element L such as a coil, and then both the switching elements Q1, Q2
Is turned off, the diode D1 is turned off.
The energy stored in the element L is released to the smoothing circuit 1 composed of the diode and the two capacitors through the current path formed by the above, and as a result, a current voltage is generated between the outputs 1 and 2 terminals.

The current voltage value output between the output terminals 1 and 2 is determined by the supply DC voltage energy and the element Q
1, determined based on the duty ratio of the on-off time of Q2 and the like.

FIG. 4 is a circuit diagram showing a conventional step-up / down converter using the above-mentioned principle, and (2) is a circuit for detecting the voltage between the output 1 and output 2 terminals.
It consists of two resistors connected in series. (3) is the above 2
A circuit for detecting a current flowing between the terminals, (4) is a voltage regulator composed of, for example, a semiconductor integrated circuit MB3759 manufactured by Fujitsu Limited, and the regulator is detected by the two detection circuits (2) and (3). The amount of load connected between the output terminals 1 and 2 is detected based on the voltage / current value, and the switching elements Q1, Q
2 to determine the duty ratio of the on-off time. Then, according to the duty ratio, the terminals OUT1 and OU
From T2, pulse signals having the same cycle and the same duty ratio are output.

The NPN-type transistor Q3 and the PNP-type transistor Q4 constitute a circuit for amplifying the pulse signal output from the terminal OUT1. The base, collector and emitter of the transistor Q3 are connected to the input terminal, the terminal OUT1 of the regulator (4) and the gate of the switching element Q1, respectively, and a resistor R1 is connected between the base and the collector. The base / collector and emitter of the transistor Q4 are respectively connected to a capacitor C1.
Through the terminal OUT1, the gate of the switching element Q1, and GND. Accordingly, during the high ("1") period of the pulse signal output from OUT1, the transistor Q3 is turned on and Q4 is turned off, and the voltage supplied from the input terminal is applied to the gate of the element Q1 via Q3. Therefore, the element Q1 is turned off. On the other hand, during the low ("0") period of the pulse signal, the transistor Q3 is turned off and the transistor Q4 is turned on.
Gate is grounded via Q4, and Q1 is turned on. When the pulse signal rises from low to high, the return of the element Q1 to the off state is slightly delayed due to the charge accumulation action in the capacitor C1.

On the other hand, PNP transistors Q5 and NP
The N-type transistor Q6 is for amplifying the pulse signal output from the terminal OUT2. The base, collector and emitter of the transistor Q5 are connected to terminals OU
T2, the input terminal and the gate of the switching element Q2, the base, collector and emitter of the transistor Q6 are connected to the terminal OUT2, the gate of the element Q2 and GND, respectively.
It is connected to the. Accordingly, during the high period of the pulse signal output from the terminal OUT2, Q5 is turned off and Q6 is turned on, so that the gate of the element Q2 is grounded via Q6,
The element Q2 is turned off. During the low period of the pulse signal, Q5 is turned on and Q6 is turned off.
A voltage supplied from the input terminal via Q5 is applied to the gate of the device, and the element Q2 is turned on.

FIG. 5 is an example of a time chart showing the relationship between the outputs of the terminals OUT1 and OUT2 and the on / off states of the switching elements Q1 and Q2 in the conventional example.

As apparent from FIG. 5, the return of the switching element Q1 during the off period is slightly later than that of the switching element Q2. It has been experimentally found that the conversion efficiency is increased by making the off duty of the switching element Q1 shorter than that of Q2.

[0012]

However, a switching element Q using a resistor R3 and a capacitor C1 as in the prior art.
If the on-duty of 1 is to be lengthened, as is clear from the time chart of FIG. 5, the extended period is not a complete on-state, but a period of gradually changing from the on-state to the off-state. In such a period, the conversion efficiency is lower than in the complete ON state.

As a method for solving this problem, it is conceivable to increase the hfe of the transistor Q3 to about twice that of the other transistors, but this method is not sufficient.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a feature that an inductance element,
A first switching element connected in series to an input end of the element, a means for smoothing an output from the inductance element, and a second switching element connected in parallel with the smoothing means on the output side of the inductance element When,
Means for detecting a voltage value output from the smoothing means;
Means for detecting a current value output from the smoothing means,
Means for detecting a load amount connected to the smoothing circuit based on the detected voltage / current value and generating a pulse signal having a duty ratio according to the load amount; Means for delaying off-period return, shaping means for shaping the pulse signal delayed for off-period return by the delay means, and outputting the signal as a signal for turning on and off the first switching element, and turning on and off the second switching element Means for supplying a pulse signal generated from the pulse generation means as a signal for performing the step-down converter,
The output shaping means includes a transistor connected between an input terminal of the first switching element and a gate of the first switching element, and a resistor connected between a base of the transistor and an output of the delay means. And a diode connected between the gate of the first switching element and the output of the delay means.

[0015]

[0016]

According to this structure, the change of the first switching element from the ON state to the OFF state becomes clear, and the conversion efficiency is improved.

[0017]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
The difference from the conventional example shown in FIG.
In that an NPN-type transistor Q7, a resistor R2, and a diode D2 for shaping the waveform of a pulse signal supplied to the gate are newly added. The above transistor Q
The collector and the emitter of 7 are connected to the input terminal and the gate of the switching element Q1, respectively, and the base is connected to the emitter of the transistor Q3 via the resistor R3. Diode D2 is connected between the gate of switching element Q1 and the emitter of transistor Q3.

In order to explain the operation of the present embodiment, the operation of the amplifier circuit composed of the transistors Q5 and Q6 for the pulse signal output from the terminal OUT2 of the regulator (4) and the switching element responding to the output of this amplifier circuit The operation of Q2 is the same as that of the related art, and a description thereof will be omitted.

In the present embodiment, during the high period of the pulse signal output from the terminal OUT1 of the regulator (4), the transistor Q3 is turned on, so that the current supplied from the input terminal passes through the transistor Q3 and the resistor R2. It is supplied to the transistor Q7. As a result, the transistor Q
7 is turned on, and the switching element Q
Since the voltage supplied from the input terminal is applied to one gate, the switching element Q1 is turned off. On the other hand, during the low period of the pulse signal, the transistor Q4 is turned on, so that the gate of the switching element Q1 is grounded via the diode D2 and the transistor Q4.
1 is turned on.

When the pulse signal changes from low to high, the pulse signal continues to be charged until the capacitor C1 that has released the electric charge during the low period of the pulse signal is charged (referred to as an extension period), as in the prior art. Is high, transistor Q3 remains off and Q4 remains on. As a result, during the extension period, the transistor Q
Since the switching element 7 is also in the off state, the switching element Q1 remains completely on.

FIG. 2 shows a terminal OU in the above-described embodiment.
6 is a time chart illustrating a relationship between pulse signals output from T1 and T2 and on / off operations of switching elements Q1 and Q2.

In this embodiment, the input terminal has a voltage of 10 V.
Is applied, and the conversion efficiency when obtaining an output of 20 V and 2 A from the output terminals 1 and 2 is about 89%, whereas the conversion efficiency of the conventional circuit shown in FIG. 4 is only about 80%. I have.

[0023]

As is apparent from the above description, according to the present invention, the conversion efficiency of the step-up / down converter can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation of the present embodiment.

FIG. 3 is a circuit diagram for explaining the principle of a step-up / down converter.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is a time chart showing the operation of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Smoothing circuit 2 Voltage detection circuit 3 Current detection circuit 4 Voltage regulator Q1 Switching element Q2 Switching element L Inductance element Q7 Transistor R2 Resistance D2 Diode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-68877 (JP, A) JP-A-56-101223 (JP, A) JP-A 1-148073 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H02M 3/155

Claims (1)

(57) [Claims] 1. An inductance element, a first switching element connected in series to an input end of the inductance element, means for smoothing an output from the inductance element, and a smoothing means on an output side of the inductance element. a second switching element connected in parallel, means for detecting a voltage value output from said smoothing means, means for detecting a current value outputted from said smoothing means, said based on the detected voltage and current values Detects the load connected to the smoothing circuit
Means a generation than the pulse generating means for generating a pulse <br/> scan signal having a duty ratio in accordance with the load as well as
Means for delaying the recovery of the off-period of the pulse signal, and
Shaping the pulse signal delayed in off-period return by delay means
And a signal for turning on and off the first switching element.
And shaping means for outputting as said second switching element
The above-mentioned pulse generation means as a signal for turning on and off
In step-up-down converter with means for supplying et generating pulse signals, the output shaping means, an input of the first switching element
Connected between the end and the gate of the first switching element.
Transistor and the base of the transistor and the delay
A resistor connected between the first switch and the output of the first switch.
Between the gate of the switching element and the output of the delay means.
A step-up / down converter, comprising: a continuous diode .