JPH07177734A - Step-up/down converter - Google Patents

Abstract

PURPOSE:To increase the conversion efficiency of a step-up/down converter by changing the on-duty ratio of a pulse signal to be supplied to a first switching element which is connected in series with an inductance element. CONSTITUTION:When a pulse signal(PS) which is output from a terminal OUT1 of a regulator 4 is at an H level, a transistor(Tr) Q3 is turned on and a current supplied by the regulator 4 is supplied to a TrQ7 through the TrQ3 and a resistor R2. As a result, a voltage is applied to a switching element(SW) Q1 through the TrQ7 and then the SWQ1 is turned off. When the PS is at an L level, on the other hand, the TrQ4 is turned on and the gate of the SWQ1 is grounded through a diode D2 and the TrQ4 and then the SWQ1 is turned on. When the level of the PS turns from L to H, the TrQ3 is kept off and the SWQ4 is kept on until a capacitor C1 which has discharged during the time when the PS is at the L level (during the extended period of time) is changed, although the PS is at the H level. As a result, the TrQ7 is kept off and the SWQ1 is kept on during the extended period of time.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a step-up / down converter.

[0002]

2. Description of the Related Art At present, there are cases in which various devices require different current and voltage depending on their usage conditions. Therefore, a current adapter equipped with a multi-voltage output circuit (for example, Japanese Patent Laid-Open No. Hei 5-297962). (See) is required.

Further, in portable electronic devices which have become widespread in recent years, in addition to commercial alternating current, it is required that direct current obtained from a DC socket in a vehicle can be used as the current. The output voltage value of such a DC power source varies depending on the vehicle type (+ 10.5V or + 16V),
On the other hand, in an electronic device, for example, at 20V depending on the usage situation, 2.
It is required to switch and use the first current voltage value of 0 A, the second current voltage value of 2.4 A at 16 V, and the third current voltage value of 3.4 A at 10 V. It should be noted that such switching of the current-voltage value is specifically performed depending on the presence or absence of a secondary battery built in the electronic device, the magnitude of the load based on the operating state of the electronic device, and the like.

For this reason, a step-up / down converter is used for the power adapter of this kind of electronic equipment.

FIG. 3 is a circuit diagram for explaining the principle of this type of converter. This converter converts the DC voltage energy supplied from the input end into a P-type channel FET.
Switching element Q1 and N-type channel FE
Both of the switching elements Q1 and Q2 are temporarily stored in the inductance element L such as a coil by bringing both switching elements Q2 made of T into a conductive (ON) state.
The diode D1 by turning off the diode.
Energy stored in the element L is discharged to the smoothing circuit 1 including a diode and two capacitors through a current path formed by the above, and as a result, a current voltage is generated between the output 1 and 2 terminals.

Further, the current voltage value output between the output 1 and the output 2 terminals is the supplied DC voltage energy and the element Q.
1, Q2 is determined based on the duty ratio of the on-off time.

FIG. 4 is a circuit diagram showing a conventional step-up / down converter using the above principle, and (2) is a circuit diagram for detecting the voltage between the output 1 and 2 terminals, which are connected in series. It consists of two resistors. (3) is a circuit for detecting a current flowing between the two terminals, and (4) is a voltage regulator composed of a semiconductor integrated circuit MB3759 manufactured by Fujitsu Ltd., for example.
The load amount connected between the output 1 and the output 2 terminals is detected based on the voltage and current values detected by the detection circuits (2) and (3), and the switching element Q is detected based on the detection result.
1, the duty ratio of the on-off time of Q2 is determined.
Then, according to the duty ratio, pulse signals having the same duty ratio are output from the terminals OUT1 and OUT2 in the same cycle.

The NPN type transistor Q3 and the PNP type transistor Q4 form a circuit for amplifying the pulse signal output from the terminal OUT1. The base, collector and emitter of the transistor Q3 are connected to the input terminal, the terminal OUT1 of the regulator (4) and the gate of the switching element Q1, respectively, and the resistor R1 is connected between the base and collector thereof. The base and collector and the emitter of the transistor Q4 are respectively the capacitor C1.
Is connected to the terminal OUT1, the gate of the switching element Q1 and the GND. Therefore, during the high (“1”) period of the pulse signal output from the OUT1, the transistor Q3 is turned on and Q4 is turned off, and the voltage supplied from the input terminal is applied to the gate of the element Q1 via the Q3. Therefore, the element Q1 is turned off. On the other hand, during the low (“0”) period of the pulse signal, the transistor Q3 is turned off and the transistor Q4 is turned on.
The gate of is brought into a grounded state through Q4, and the Q1 is turned on. When the pulse signal rises from low to high, the charge storage action on the capacitor C1 slightly delays the return of the element Q1 to the off state.

On the other hand, PNP type transistors Q5 and NP
The N-type transistor Q6 is for amplifying the pulse signal output from the terminal OUT2. The base, collector and emitter of the transistor Q5 have terminals OU, respectively.
T2 is connected to the input terminal and the gate of the switching element Q2, and the base, collector and emitter of the transistor Q6 are connected to the terminal OUT2, the gate of the element Q2 and GND, respectively.
It is connected to the. Therefore, during the high period of the pulse signal output from the terminal OUT2, Q5 is turned off and Q6 is turned on, so that the gate of the element Q2 is grounded via Q6,
The element Q2 is turned off. Further, during the low period of the pulse signal, Q5 is turned on and Q6 is turned off.
A voltage supplied from the input end is applied to the gate of the device through Q5, and the element Q2 is turned on.

FIG. 5 is an example of a time chart showing the relationship between the outputs from the terminals OUT1 and OUT2 and the ON / OFF states of the switching elements Q1 and Q2 in the conventional example.

As is apparent from FIG. 5, the OFF period recovery of the switching element Q1 is slightly later than that of Q2. It has been experimentally found that the conversion efficiency is increased by making the off duty of the switching element Q1 shorter than that of Q2.

[0012]

However, the switching element Q is formed by using the resistor R3 and the capacitor C1 as in the prior art.
When it is attempted to lengthen the on-duty of 1, the lengthened period is not the complete on-state as is apparent from the time chart of FIG. In such a period, the conversion efficiency is lower than that in the completely ON state.

As a method for solving this problem, the hfe of the transistor Q3 may be increased to about twice that of other transistors, but this method is not sufficient.

[0014]

The present invention has been made in view of the above points, and a first feature thereof is that an inductance element and a first switching element connected in series to the input end side of the element are provided. A means for smoothing the output from the inductance element, a second switching means connected in parallel with the smoothing means on the output side of the inductance element, a means for detecting a voltage value output from the smoothing means, Means for detecting a current value output from the smoothing means, means for generating a pulse signal for controlling ON / OFF of the first and second switching elements based on the detected voltage / current value, and the pulse generating means More specifically, there is provided means for changing the on-duty ratio of the pulse signal supplied to the first switching element, and means for shaping the output of the changing means. .

A second feature is that the inductance element, the first switching element connected in series to the input end side of the element, the means for smoothing the output from the inductance element, and the smoothing means in parallel. And a means for generating a pulse signal for controlling ON / OFF of the first and second switching elements, wherein the pulse generating means is provided to the second switching element with respect to the first switching element. The period in which the first switching element is turned on has the same period as the pulse signal to be supplied, and is the second period.
It is to supply a pulse signal that is larger than that of the switching element.

[0016]

According to this structure, the change of the first switching element from the ON state to the OFF state becomes clear, and the conversion efficiency is improved.

[0017]

FIG. 1 is a circuit diagram showing an embodiment of the present invention,
The difference from the conventional example shown in FIG.
The point is that an NPN type transistor Q7, a resistor R2, and a diode D2 for shaping the waveform of the pulse signal supplied to the gate of are newly added. Transistor Q above
The collector and the emitter of 7 are connected to the input end and the gate of the switching element Q1, respectively, and the base thereof is connected to the emitter of the transistor Q3 via the resistor R3. The diode D2 is connected between the gate of the switching element Q1 and the emitter of the transistor Q3.

To explain the operation of this embodiment, the operation of the amplifier circuit including the transistors Q5 and Q6 with respect to the pulse signal output from the terminal OUT2 of the regulator (4) and the switching element responding to the output of this amplifier circuit. Since the operation of Q2 is the same as the conventional one, its explanation is omitted.

In this embodiment, since the transistor Q3 is turned on during the high period of the pulse signal output from the terminal OUT1 of the regulator (4), the current supplied from the input terminal is passed through the transistor Q3 and the resistor R2. It is supplied to the transistor Q7. As a result, the transistor Q
7 is turned on, and the switching element Q is connected via this Q7.
Since the voltage supplied from the input terminal is applied to the gate of No. 1, the switching element Q1 is turned off. On the other hand, during the low period of the pulse signal, since the transistor Q4 is turned on, the gate of the switching element Q1 is grounded via the diode D2 and the transistor Q4, and as a result, Q
1 is turned on.

Further, when the pulse signal changes from low to high, the pulse signal is kept until the capacitor C1 which has discharged the electric charge is charged during the low period of the pulse signal (called an extension period) as in the conventional case. Is high, transistor Q3 remains off and Q4 remains on. As a result, during the above extension period, the transistor Q
Since 7 is also in the off state, the switching element Q1 remains completely turned on.

FIG. 2 shows the terminal OU in this embodiment described above.
7 is a time chart showing the relationship between the pulse signals output from T1 and T2 and the on / off operation of the switching elements Q1 and Q2.

In this embodiment, 10 V is applied to the input terminal.
While the conversion efficiency in obtaining 20V and 2A outputs from the output terminals 1 and 2 by applying the voltage of about 89% is about 89%, the conversion efficiency of the conventional circuit shown in FIG. 4 is about 80%. There is.

[0023]

As is apparent from the above description, according to the present invention, the conversion efficiency of the step-up / down converter can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of this embodiment.

FIG. 3 is a circuit diagram for explaining the principle of a step-up / down converter.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is a time chart showing an operation of a conventional example.

[Explanation of symbols]

 1 smoothing circuit 2 voltage detection circuit 3 current detection circuit 4 voltage regulator Q1 switching element Q2 switching element L inductance element Q7 transistor R2 resistance D2 diode

Claims (2)

[Claims] 1. An inductance element, a first switching element connected in series to an input end side of the element, a means for smoothing an output from the inductance element, and a smoothing means on an output side of the inductance element. Second switching means connected in parallel, means for detecting a voltage value output from the smoothing means, means for detecting a current value output from the smoothing means, and the above-mentioned detection voltage based on the detected current value. Means for generating a pulse signal for controlling on / off of the first and second switching elements, and means for changing an on-duty ratio of the pulse signal supplied from the pulse generating means to the first switching element,
A step-up / down converter comprising means for shaping the output of the changing means. 2. An inductance element, a first switching element connected in series to the input end side of the element, a means for smoothing an output from the inductance element, and a means connected in parallel with the smoothing means. And means for generating a pulse signal for controlling ON / OFF of the first and second switching elements, wherein the pulse generating means supplies a pulse signal to the second switching element with respect to the first switching element. A step-up / down converter which supplies a pulse signal having the same period and a period in which the first switching element is on for a period longer than that of the second switching element.