JP3035940B2 - Image display circuit - Google Patents
Image display circuitInfo
- Publication number
- JP3035940B2 JP3035940B2 JP1316216A JP31621689A JP3035940B2 JP 3035940 B2 JP3035940 B2 JP 3035940B2 JP 1316216 A JP1316216 A JP 1316216A JP 31621689 A JP31621689 A JP 31621689A JP 3035940 B2 JP3035940 B2 JP 3035940B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistance
- power supply
- image display
- display circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Transforming Electric Information Into Light Information (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は画像表示回路に関し、特に画像信号をアナロ
グ−ディジタル（A/D）変換するA/D変換器に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display circuit, and more particularly to an A / D converter for converting an image signal from analog to digital (A / D).
［従来の技術］ テレビをはじめとする画像機器分野で、液晶等を表示
部に用いた機器が増加している。例えば、液晶表示体を
用いた液晶テレビでは、液晶表示駆動部へ画像信号を転
送する方式として、アナログ値である画像信号をA/D変
換器を介してＮビットのディジタル値に変換して転送す
る方法がある。この方法では、画像データのデータ線の
数がアナログ値で画像信号を転送する場合に比べて、Ｎ
倍に増加する。従って、データ線の配線エリアが大きく
なるとか、液晶表示体を駆動するセグメント側でのシフ
トレジスタが（Ｎビット×水平方向画素数）分必要とな
り、回路規模が大きくなるといった問題点があった。[Prior Art] In the field of image devices such as televisions, devices using liquid crystal or the like for display units are increasing. For example, in a liquid crystal television using a liquid crystal display, as a method of transferring an image signal to a liquid crystal display driving unit, an image signal which is an analog value is converted into an N-bit digital value via an A / D converter and transferred. There is a way to do that. In this method, the number of data lines of the image data is N, compared to the case where the image signal is transferred with an analog value.
Increase by a factor of two. Therefore, there is a problem that the wiring area of the data line becomes large or a shift register on the segment side for driving the liquid crystal display is required for (N bits × the number of pixels in the horizontal direction), and the circuit scale becomes large.
これらの問題点を軽減するため、特開平01−68185号
では、第３図に示す様な構成をとっている。In order to reduce these problems, Japanese Patent Application Laid-Open No. 01-68185 employs a configuration as shown in FIG.
抵抗R1〜R8は直列接続され、その両端は基準電源VL及
びVHに接続されている。更に、抵抗R1にはゲート回路31
が、抵抗R8にはゲート回路32がそれぞれ並列に接続さ
れ、これらのゲート回路31,32はフレーム信号Ｆと反転
したにより交互にオン／オフされる。Resistor R 1 to R 8 are connected in series, and both ends thereof are connected to the reference power supply V L and V H. Furthermore, the gate circuit 31 to the resistor R 1
There, the gate circuit 32 to the resistor R 8 is connected in parallel, these gate circuits 31 and 32 are alternately turned on / off by the inverted frame signal F.
また、抵抗R1〜R8の各接続点電位Vmin,V1〜V5,Vmaxは
参照電圧としてコンパレータ群33の−端子に入力され、
＋端子には画像信号VDが入力される。即ち、この画像信
号VDの電圧が各参照電圧と比較されてコンパレータ群33
から比較結果が出力され、更にエンコーダ34により３ビ
ットの画像データD1〜D3に変換される。Further, the connection point potential Vmin of the resistors R 1 ~R 8, V 1 ~V 5, Vmax is the comparators 33 as the reference voltage - is input to the terminal,
The image signal VD is input to the + terminal. That is, the voltage of the image signal VD is compared with each reference voltage, and the comparator group 33
And outputs a comparison result, which is further converted by the encoder 34 into 3-bit image data D1 to D3.
ここで、抵抗R1,R8は抵抗値R/2,抵抗R2〜R7は抵抗値
Ｒに設定されており、前記ゲート回路31,32の交互オン
／オフにより、前記各参照電圧が前記フレーム信号F,
の出力反転に応じて、参照電圧間隔の1/2レベルシフト
する。従って、前記フレーム信号F,の出力ＨとＬでの
参照電圧を合わせると、15段階の画像信号レベルが識別
可能となり、画像データ信号は３ビットでありながら、
４ビットに近い階調表示が可能となる。Here, the resistances R 1 and R 8 are set to a resistance value R / 2, and the resistances R 2 to R 7 are set to a resistance value R. By alternately turning on / off the gate circuits 31 and 32, the respective reference voltages are changed. The frame signal F,
Is shifted by half the reference voltage interval in accordance with the output inversion of the reference voltage. Therefore, when the reference voltages at the outputs H and L of the frame signal F are combined, 15 levels of image signal levels can be identified, and while the image data signal is 3 bits,
A gradation display close to 4 bits becomes possible.
［発明が解決しようとする課題］ しかし、前者の例では、ゲート回路のオン抵抗が完全
に０オームでなければ、正確に参照電圧間隔の1/2レベ
ルシフトが行われない為、少なくとも数十オームのオン
抵抗を有する半導体スイッチでは実現不能であった。[Problems to be Solved by the Invention] However, in the former example, if the on-resistance of the gate circuit is not completely 0 ohm, a half-level shift of the reference voltage interval is not performed accurately. This cannot be realized with a semiconductor switch having an ohmic on-resistance.
そこで、本発明はこの様な問題点を解決するもので、
その目的とするところは、半導体スイッチを使用して正
確に参照電圧間隔の1/2レベルシフトを実現し、IC化に
適したA/D変換器を提供する事にある。Therefore, the present invention solves such a problem.
An object of the present invention is to provide an A / D converter suitable for IC implementation by accurately achieving a half-level shift of a reference voltage interval using a semiconductor switch.
［課題を解決するための手段］ 本発明の画像表示回路は、抵抗により規定される電圧
を基準にして画像信号をＮビットのディジタル信号に変
換するアナログ−ディジタル変換器を備えた画像表示回
路において、第１のスイッチと直列に接続された抵抗値
r/2の第１抵抗を有する第１及び第２の電流経路と、第
２のスイッチと直列に接続された抵抗値ｒの第２抵抗を
有する第３及び第４の電流経路と、2N−２個の等しい抵
抗値ｒを有する直列接続された第３抵抗とを備え、制御
信号に基づき前記第３抵抗の一端を前記第１の電流経路
を介して第１の電源端子に接続し、前記第３抵抗の他端
を前記第３の電流経路を介して第２の電源端子に接続す
る第１の状態と、前記制御信号に基づき前記第３抵抗の
前記一端を第４の電流経路を介して前記第１の電源端子
に接続し、前記第３抵抗の前記他端を前記第２の電流経
路を介して前記第２の電源端子に接続する第２の状態と
を所定の時間毎に切替えてなることを特徴とする。[Means for Solving the Problems] An image display circuit according to the present invention is an image display circuit provided with an analog-digital converter for converting an image signal into an N-bit digital signal with reference to a voltage defined by a resistor. , The resistance value connected in series with the first switch
first and second current paths having a first resistance of r / 2, third and fourth current paths having a second resistance of resistance r connected in series with the second switch, and 2 N A third resistor connected in series having two equal resistance values r, and one end of the third resistor is connected to a first power supply terminal via the first current path based on a control signal; A first state in which the other end of the third resistor is connected to a second power supply terminal via the third current path; and a first state in which the one end of the third resistor is connected to a fourth current path based on the control signal. And a second state in which the other end of the third resistor is connected to the second power supply terminal via the second current path. It is characterized by being switched.
［実施例］ 以下、本発明について実施例に基づき詳細に説明す
る。EXAMPLES Hereinafter, the present invention will be described in detail based on examples.
第１図は本発明の画像表示回路に使用するA/D変換器
の回路図であり、第２図は画像信号をA/D変換する際の
参照電圧の説明図である。FIG. 1 is a circuit diagram of an A / D converter used in an image display circuit of the present invention, and FIG. 2 is an explanatory diagram of a reference voltage when A / D converting an image signal.
抵抗R2〜R7は直列接続され、抵抗R2の片側には抵抗R
1a及びR1bが、抵抗R7の片側には抵抗R8a及びR8bがそれ
ぞれ接続されている。更に、抵抗R1a及びR1bの片側には
それぞれゲート１及び２が、抵抗R8a及びR8bの片側には
それぞれゲート３及び４が接続されている。更に、ゲー
ト１及び２の片側は基準電源VLに、ゲート３及び４の片
側は基準電源VHに接続されている。そして、これらのゲ
ート１〜４は１フィールド毎に反転するフレーム信号Ｆ
及びインバータ５による反転信号によりオン／オフさ
れる。Resistor R 2 to R 7 are serially connected, on one side of the resistor R 2 resistor R
1a and R 1b are, on one side of the resistor R 7 resistor R 8a and R 8b are connected. Furthermore, the resistor R 1a and gates 1 and 2 are on one side of the R 1b is, the resistance R 8a and each of the side gates 3 and 4 of the R 8b are connected. Further, one side of the gate 1 and 2 to the reference power supply V L, one side of the gate 3 and 4 are connected to the reference power supply V H. These gates 1 to 4 are connected to a frame signal F which is inverted every field.
And turned on / off by an inverted signal from the inverter 5.
また、抵抗R1〜R8の各接続点電位Vmin,V1〜V5,Vmaxは
参照電圧としてコンパレータ群６の−端子に入力され、
＋端子には画像信号VDが入力される。即ち、この画像信
号VDの電圧が各参照電圧と比較されてコンパレータ群６
から比較結果が出力され、更にエンコーダ７により３ビ
ットの画像データD1〜D3に変換される。Further, the connection point potential Vmin of the resistors R 1 ~R 8, V 1 ~V 5, Vmax is the comparators 6 as the reference voltage - is input to the terminal,
The image signal VD is input to the + terminal. That is, the voltage of the image signal VD is compared with each reference voltage, and
And outputs a comparison result, which is further converted by the encoder 7 into 3-bit image data D1 to D3.
ここで、抵抗R1a,R8bは抵抗値R/2,抵抗R1b,R8a,R2〜R
7は抵抗値Ｒに設定されている。そして、前記フレーム
信号ＦがＬレベルの状態では、ゲート1,3がオン、ゲー
ト2,4がオフとなるため、抵抗R1aが基準電源VLに、抵抗
R8aが基準電源VHに接続される。一方、前記フレーム信
号ＦがＨレベルの状態では、ゲート1,3がオフ、ゲート
2,4がオンとなるため、抵抗R1bが基準電源VLに、抵抗R
8bが基準電源VHに接続される。従って、基準電源VH〜VL
間の抵抗値は変わらないが、各抵抗接続点と基準電源VH
またはVL間の抵抗値はR/2変化する。即ち、前記フレー
ム信号Ｆのレベル変化に対する各参照電圧のシフト量VS
は となる。ただし、rLはゲート1,2、rHはゲート3,4のオン
抵抗を示す。Here, the resistors R 1a and R 8b have a resistance value R / 2, and the resistors R 1b , R 8a and R 2 to R
7 is set to the resistance value R. Then, in the frame signal F is L level, the gate 1,3 is on, the gate 2,4 is turned off, the resistor R 1a is a reference power supply V L, resistance
R 8a is connected to the reference power supply V H. On the other hand, when the frame signal F is at the H level, the gates 1 and 3 are off,
2 and 4 are turned on, the resistor R 1b is connected to the reference power supply VL ,
8b is connected to the reference power supply V H. Therefore, the reference power supply VH to VL
Although the resistance value between them does not change, each resistance connection point and the reference power supply V H
Alternatively, the resistance value between VL changes by R / 2. That is, the shift amount V S of each reference voltage with respect to the level change of the frame signal F
Is Becomes Here, r L indicates the ON resistance of the gates 1 and 2, and r H indicates the ON resistance of the gates 3 and 4.
一方、参照電圧の間隔Vdは となるから、VS＝Vd/2となる。On the other hand, the reference voltage interval Vd is Therefore, V S = Vd / 2.
これを図示したものが第２図であり、前記フレーム信
号ＦのＬレベルとＨレベルでの参照電圧を合わせると15
段階の画像信号レベルが識別可能となり、画像データ信
号は３ビットでありながら、４ビットに近い階調表示が
可能となる。また、上式よりVS＝Vd/2の関係はrH及びrL
に影響されないため、ゲート１〜４に抵抗値が存在して
も変換分解能は変わらない。そこで、第１図のA/D変換
器をIC化した場合、ゲート１と2,ゲート３と４のオン抵
抗の絶対値は変動しても、相対値は等しいから、前記VS
＝Vd/2の式が成立する。FIG. 2 shows this, and when the reference voltages at the L level and the H level of the frame signal F are combined, 15
The level of the image signal can be identified, and the gray scale display close to 4 bits can be performed while the image data signal is 3 bits. From the above equation, the relationship of V S = Vd / 2 is r H and r L
, The conversion resolution does not change even if the gates 1-4 have a resistance value. Therefore, when an IC the A / D converter of FIG. 1, the gate 1 and 2, the absolute value of the on resistance of the gate 3 and 4 vary, because relative values are equal, the V S
= Vd / 2 holds.
また、実施例では半導体スイッチとしてFETを用いた
が、トランジスタ，アナログスイッチ等スイッチング機
能を有する半導体は全て本発明に含まれる。In the embodiments, the FET is used as the semiconductor switch. However, the present invention includes all semiconductors having a switching function such as a transistor and an analog switch.
［発明の効果］ 本発明は以上説明したとおり、A/D変換に必要な参照
電圧を参照電圧間隔の1/2レベルシフトして、実際のビ
ット数よりも１段上の変換分解能を得る場合に、半導体
スイッチのオン抵抗がこの変換分解能に影響しない構成
となっている。従って、A/D変換器のIC化に適し、コス
トダウンが図れると共に、実装面積も縮少出来る。[Effect of the Invention] As described above, the present invention shifts the reference voltage required for A / D conversion by half the reference voltage interval to obtain a conversion resolution one stage higher than the actual number of bits. In addition, the configuration is such that the on-resistance of the semiconductor switch does not affect the conversion resolution. Therefore, the A / D converter is suitable for use as an IC, cost can be reduced, and the mounting area can be reduced.
第１図は本発明の画像表示回路に使用するA/D変換器の
回路図。 第２図は画像信号をA/D変換する際の参照電圧の説明
図。 第３図は従来のA/D変換器の回路図。 １〜４……ゲート ５……インバータ ６……コンパレータ ７……エンコーダFIG. 1 is a circuit diagram of an A / D converter used in the image display circuit of the present invention. FIG. 2 is an explanatory diagram of a reference voltage at the time of A / D conversion of an image signal. FIG. 3 is a circuit diagram of a conventional A / D converter. 1-4: Gate 5: Inverter 6: Comparator 7: Encoder
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H04N 5/66 - 5/74 H03M 1/00 - 1/88 G09G 3/36 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 7 , DB name) H04N 5/66-5/74 H03M 1/00-1/88 G09G 3/36
Claims (1)
像信号をＮビットのディジタル信号に変換するアナログ
−ディジタル変換器を備えた画像表示回路において、 第１のスイッチと直列に接続された抵抗値r/2の第１抵
抗を有する第１及び第２の電流経路と、第２のスイッチ
と直列に接続された抵抗値ｒの第２抵抗を有する第３及
び第４の電流経路と、2N−２個の等しい抵抗値ｒを有す
る直列接続された第３抵抗とを備え、 制御信号に基づき前記第３抵抗の一端を前記第１の電流
経路を介して第１の電源端子に接続し、前記第３抵抗の
他端を前記第３の電流経路を介して第２の電源端子に接
続する第１の状態と、 前記制御信号に基づき前記第３抵抗の前記一端を第４の
電流経路を介して前記第１の電源端子に接続し、前記第
３抵抗の前記他端を前記第２の電流経路を介して前記第
２の電源端子に接続する第２の状態とを所定の時間毎に
切替えてなることを特徴とする画像表示回路。An image display circuit provided with an analog-to-digital converter for converting an image signal into an N-bit digital signal based on a voltage defined by a resistor, wherein the resistor is connected in series with the first switch. First and second current paths having a first resistance of value r / 2, third and fourth current paths having a second resistance of resistance r connected in series with the second switch, 2 N- 2 third resistors connected in series having the same resistance value r, and one end of the third resistor is connected to a first power supply terminal via the first current path based on a control signal. A first state in which the other end of the third resistor is connected to a second power supply terminal via the third current path; and a fourth current path in which the one end of the third resistor is connected based on the control signal. Connected to the first power supply terminal via the An image display circuit characterized by switching between a predetermined state and a second state in which an end is connected to the second power supply terminal via the second current path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1316216A JP3035940B2 (en) | 1989-12-05 | 1989-12-05 | Image display circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1316216A JP3035940B2 (en) | 1989-12-05 | 1989-12-05 | Image display circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03175887A JPH03175887A (en) | 1991-07-30 |
| JP3035940B2 true JP3035940B2 (en) | 2000-04-24 |
Family
ID=18074596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1316216A Expired - Lifetime JP3035940B2 (en) | 1989-12-05 | 1989-12-05 | Image display circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3035940B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010061723A (en) * | 2008-09-02 | 2010-03-18 | Toppan Printing Co Ltd | Semiconductor memory device |
-
1989
- 1989-12-05 JP JP1316216A patent/JP3035940B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03175887A (en) | 1991-07-30 |
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