JP2625757B2 - Image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly, to an analog-digital converter (A / D converter) for converting an image signal from analog to digital.

[Conventional technology]

2. Description of the Related Art In the field of image devices such as televisions, devices using a liquid crystal or the like for a display unit are increasing. For example, in a liquid crystal television using a liquid crystal display, as a method of transferring an image signal to a liquid crystal display unit, a method of converting an image signal, which is an analog value, into an N-bit digital value via an A / D converter and transferring the converted signal. There is. In this method, the number of data lines of the image data is increased N times as compared with the case where the image signal is transferred in an analog value. Therefore, there has been a problem that the wiring area of the data line becomes large, and the shift register on the segment side for driving the liquid crystal display is required for the number of N bits × horizontal pixels, thereby increasing the circuit scale. In order to reduce these problems, for example, Japanese Patent Application Laid-Open No. Sho 61-234673 discloses the following technology.

In this technology example, the number of scanning electrodes of the display unit is smaller than the number of effective scanning lines in the field period (for example, when receiving and displaying an image of Japanese television broadcasting, the number of scanning electrodes is 220
~ 240 lines). When such display is performed, two fields are considered as a pair by utilizing the fact that the video information of each field is almost the same, and the image information of the scanning line in the same order in each field is considered. It is common to output to the same scanning side electrode in the display unit.

The circuit configuration of the image display device for realizing such a display method is as follows.

FIG. 4 shows a block diagram of the image display device. 401 is A / D
A converter converts an image signal that is an analog value into a digital value. The image signal converted to digital value is
The data is transferred to the SEG drive circuit 402. Numeral 402 denotes a segment side (SEG) drive circuit for generating a display section drive signal based on an image signal to the column direction electrode of the display section 404. A common side (COM) drive circuit 403 generates a display section drive signal for driving the scan side electrodes of the display section 404. A timing generator 405 generates various timing signals based on the input synchronization signal. A frame signal F that repeats “1” and “0” every field is output from the timing generator to the A / D converter 401.

The A / D converter 401 will be described in detail below. In FIG. 5, r _{1 to} r ₁₆ are resistors having the same value and connected in series. With respect to the series circuit of the resistors r _{1 to} r ₁₅ , reference power supplies _VH and _VL are applied to both ends thereof through gate circuits 501A and 501B, and for the series circuit of the resistors r _{2 to} r _16. Reference power sources _VH and _VL are supplied to both ends thereof through gate circuits 502A and 502B. The gate circuits 501A and 501B are gate-controlled by the frame signal F from the above-described timing generator 405, and the gate circuits 502A and 502B are gate-controlled by inversion of the frame signal. And each connection point of r _{1 to} r ₁₆ is
The reference voltage is input to one terminal of the comparator 503. The + terminal of the comparator 503 has an image signal VD
Is input. The comparator 503 compares the reference voltage generated from each connection point of r _{1 to} r ₁₆ with the image signal VD, and outputs the comparison result to the encoder 504. This encoder 5
04 encodes the output of the comparator 503, converts it into 3-bit data D1, D2, D3, and outputs it to the SEG drive circuit 402.

By the way, since the frame signal F is a signal that repeats "0" and "1" for each field, the output data D1 to D3 of the A / D converter 401 are changed to two values by this signal. . That is, as shown in FIG. 3, when the frame signal F changes to “1” or “0”, the A1D converter 401 changes the r ₁ to r ₁₅ or r _{2 to} r _{16 of the} series resistance circuit.
One of the comparators 503
Is changed to obtain two types of data D1 to D2 having different values.
D3 is output.

As a result, in one frame (consisting of two field periods), the image signal is identified as a digital value of 15 steps, so that although the image data signal is 3 bits, the gradation display is close to that of 4 bits. Becomes possible.

[Problems to be solved by the invention]

However, the above prior art has the following problems. That is, although the image data signal is 3 bits, the number of resistors for generating the reference voltage is 16 in total, and the number of comparators is 15 in total, which is the number required for A / D conversion of the image signal to 4 bits. Almost the same. Therefore, the circuit scale of the A / D converter is almost the same as that of the 4-bit conversion, and is large. (For example, since this A / D converter performs A / D conversion of an image band signal, a high conversion speed is required. For high-speed operation, the values of the resistors r _{1 to} r ₁₆ must be set low. However, the size of the resistors is increased when the circuit is formed into an IC, etc.) The present invention has been made in view of such a problem of the related art, and is an N-bit image signal data. However, it is an object of the present invention to provide an image display apparatus having an A / D converter capable of performing gradation display substantially similar to N + 1-bit image signal data and having a reduced circuit scale.

[Means for solving the problem]

In order to achieve the above object, the present invention firstly provides an image display device having an analog-digital converter for converting an image signal into an N-bit digital signal, wherein the analog-digital converter is 2 ^N -1 pieces of the 2 ^N pieces of resistance group connected in series to each other for generating a reference voltage from the connection point, the 2 ^N -1 pieces of reference voltage and means for converting by comparing the image signal into a digital signal of the N-bit The resistor group includes 2 ^N- 2 first resistors connected in series having the same resistance value r, and second resistors connected in series at both ends of the resistor and having a resistance value r / 2. Wherein the two second resistors are alternately short-circuited every predetermined period of display.

Alternatively, in an image display device having an analog-to-digital converter for converting an image signal into an N-bit digital signal, the analog-to-digital converter has a maximum reference voltage.
V _+, the lowest reference voltage V _- and a resistor group connected in series to each other divided and generates 2 ^N -1 pieces of reference voltages, compares the 2 ^N -1 pieces of reference voltage and the image signal and means for converting the digital signal of the N bits, in a predetermined period T in the image signal, the first predetermined time period _{T1, V + = VU, V} - = and VD, the second predetermined time period T2 , V ₊ = VU ± (VU−VD) / (2
_{^{(2 N -2)) V -}} = VD ± (VU-VD) / (2 (2 N -2)) and then, alternately repeating a first of said a predetermined period T1 a second predetermined time period T2 It is characterized by.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an A / D converter in an image display device according to the present invention. (The overall configuration of the image display device is the same as that of FIG. 4.) In FIG. 1, resistors r _{1 to} r ₈ are series resistor circuits connected in series with each other, and both ends thereof are provided with reference power sources V _H and V _{H. L} (V _H >
_VL ). The gate circuit 10 is further resistor r ₈
1, the gate circuit 102 is connected in parallel to the resistor r _1. The gate circuit 102 is a timing generator 05
, And the gate circuit 101 performs gating by inversion of the frame signal. Therefore, when the frame signal F is “1”, r ₁ is short-circuited, and when the frame signal F is “0”, r ₈ is short-circuited. Also, resistors r _{1 to} r ₈
Are set to r ₁ = r ₈ = r / 2 and r _{2 to} r ₇ = r.

Each connection point potential V of the series resistor circuits _{r 1 ~r 8 -, V 1} ~V 5, V + is the comparator 103 as a reference voltage - is input to the terminal. An image signal VD is input to the + terminal of the comparator 103. That is, the comparator 103 outputs the image signal VD
Voltage level and the reference voltage V _-, the voltage comparison with V ₁ ~V _5, V ₊ is made. The output of the comparator 103 is input to the encoder 104 and outputs 3-bit image data D1, D2, D3.

When the frame signal F is “1”, the resistance r ₁ is short-circuited, so that the reference potentials V ₋ and V ₊ are When the frame signal F is “0”, the resistance r ₈ is short-circuited, so that the reference potentials V ₋ and V ₊ are Becomes This will be described with reference to FIG. 2, where V ₋ , V _{1 to} V ₅ ,
Each reference voltage of V ₊ is 1 / when the frame signal F is "0" and "1".
There is an offset of 13 ( _VH - _VL ). Therefore,
As shown in FIG. 2, according to the reference voltages when the frame signal F is "0" and "1", 15 levels of image signal levels can be identified. Accordingly, the A / D converted image data D1, D2, and D3 have two types of codes having different values when the frame signal F is "0" and "1", as shown in FIG.

As a result, in one frame period, the image signal is identified as a digital value of 15 levels, so that the image data signal has three levels.
Although it is a bit, a gradation display close to the case of 4 bits is possible.

In the above description, the frame signal is used as the reference voltage switching signal. However, the same operation can be performed even at an integral frequency of the frame signal.

〔The invention's effect〕

As described above, according to the present invention, the reference voltage of the N-bit A / D converter is increased or decreased by the voltage value obtained by dividing the difference between the two voltages by the predetermined value based on N in each cycle. By doing so, it is possible to realize an image display device capable of displaying a gray scale that is close to the gray scale obtained with N + 1-bit image data, and to compare the circuit scale of the A / D converter between FIG. 1 and FIG. As you know, it can be realized in about 1/2. Therefore, the circuit can be easily made into an IC, which leads to a reduction in circuit cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an A / D converter in an image display device according to the present invention. FIG. 2 is an explanatory diagram of voltage level division of an image signal. FIG. 3 is a code of image data D1 to D3 of the A / D converter. Table 4 is a block diagram of the image display device. Fig. 5 is an A / D converter circuit diagram in the conventional image display device.

Claims (2)

(57) [Claims] 1. An image display device having an analog-to-digital converter for converting an image signal into an N-bit digital signal, wherein the analog-to-digital converter generates 2 ^N -1 reference voltages from a connection point. ^2N resistor groups connected in series to each other, and means for comparing the ^2N- 1 reference voltages and the image signal and converting the image signals into the N-bit digital signal, wherein the resistor group includes: 2 ^N- 2 first resistors connected in series having the same resistance value r, and second resistors connected in series at both ends of the resistor and having a resistance value r / 2, wherein the two second resistors are provided. Is an image display device, wherein the short circuit is alternately short-circuited every predetermined period of display. 2. An image display device having an analog-to-digital converter for converting an image signal into an N-bit digital signal, wherein the analog-to-digital converter comprises a maximum reference voltage V ₊ ,
A resistor group connected in series to generate the 2 ^N -1 reference voltages by dividing the lowest reference voltage V _- and the N bit by comparing the 2 ^N -1 reference voltages with the image signal and means for converting into a digital signal at a predetermined period T in the image signal, the first predetermined time period _{T1, V + = VU, V} - in = the VD, the second predetermined time period T2, V ₊ = VU ± (VU-VD) / (2 ( ^2N
-2)) V ₋ = VD ± (VU−VD) / (2 ( ^2N− 2)), and the first predetermined period T1 and the second predetermined period T2 are alternately repeated. Image display device.