JP3024900B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP3024900B2
JP3024900B2 JP6106548A JP10654894A JP3024900B2 JP 3024900 B2 JP3024900 B2 JP 3024900B2 JP 6106548 A JP6106548 A JP 6106548A JP 10654894 A JP10654894 A JP 10654894A JP 3024900 B2 JP3024900 B2 JP 3024900B2
Authority
JP
Japan
Prior art keywords
electronic component
wiring board
capacitance
semiconductor device
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6106548A
Other languages
Japanese (ja)
Other versions
JPH07321149A (en
Inventor
隆幸 吉田
賢造 畑田
順道 太田
啓之 酒井
薫 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP6106548A priority Critical patent/JP3024900B2/en
Publication of JPH07321149A publication Critical patent/JPH07321149A/en
Application granted granted Critical
Publication of JP3024900B2 publication Critical patent/JP3024900B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874Ultraviolet [UV] curing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、電子部品を実装した半
導体装置に係り、特に使用周波数の高いハイブリッドI
C等に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on which electronic components are mounted, and more particularly to a hybrid device having a high operating frequency.
C and the like.

【0002】[0002]

【従来の技術】近年、電子機器は益々小型、高機能化、
動作速度の高速化し、モジュール化が進行している。
2. Description of the Related Art In recent years, electronic devices have become increasingly smaller and more sophisticated.
The operating speed has been increased, and modularization is in progress.

【0003】以下に、従来のハイブリッドIC等の半導
体装置について図面を参照しながら説明する。
Hereinafter, a conventional semiconductor device such as a hybrid IC will be described with reference to the drawings.

【0004】図5はワイヤボンデイング法を用いた第1
の従来例のハイブリッドICを真上から見た正面図を示
したものである。図5において、51は絶縁基板上に配
線を形成した配線基板、52は半導体素子、53はディ
スクリート部品、54はワイヤボンディングのワイヤ、
55は配線基板の配線を表しており、半導体素子52は
フェースアップでワイヤボンディング法により電気的に
配線55に接続されている。
FIG. 5 shows a first example using a wire bonding method.
1 is a front view of the conventional hybrid IC as viewed from directly above. In FIG. 5, reference numeral 51 denotes a wiring board in which wiring is formed on an insulating substrate; 52, a semiconductor element; 53, a discrete component;
Reference numeral 55 denotes a wiring of the wiring board, and the semiconductor element 52 is electrically connected to the wiring 55 by a wire bonding method in a face-up manner.

【0005】また図6は、図5に示した第1の従来例の
ワイヤボンディング法を用いたハイブリッドICの製造
工程の1例を示したものである。
FIG. 6 shows an example of a manufacturing process of a hybrid IC using the wire bonding method of the first conventional example shown in FIG.

【0006】図6においてまず、配線55を形成した配
線基板51(図6(a))上にディスクリート部品53
をはんだリフロー法により配線55に搭載する(図6
(b))。次に、半導体素子52を導電性接着剤56に
より配線基板51に対してダイボンディングを行う(図
6(c))。さらに半導体素子52の電極パッド57と
この電極パッド57に対応する配線基板51とをワイヤ
54によりワイヤボンディング法により電気的に接続す
る(図6(d))。
In FIG. 6, a discrete component 53 is first placed on a wiring board 51 (FIG. 6A) on which a wiring 55 is formed.
Is mounted on the wiring 55 by the solder reflow method (FIG. 6).
(B)). Next, the semiconductor element 52 is die-bonded to the wiring board 51 with the conductive adhesive 56 (FIG. 6C). Further, the electrode pads 57 of the semiconductor element 52 and the wiring board 51 corresponding to the electrode pads 57 are electrically connected by wires 54 by a wire bonding method (FIG. 6D).

【0007】次に、図7はフリップチップ法を用いた第
2の従来例のハイブリッドICの断面図を示したもので
ある。図7において、71は絶縁基板上に配線を形成し
た配線基板、72は半導体素子、73はディスクリート
部品、74はフリップチップ法におけるはんだバンプ、
75は配線基板の配線を表している。
FIG. 7 is a cross-sectional view of a second conventional hybrid IC using the flip-chip method. In FIG. 7, reference numeral 71 denotes a wiring board having wiring formed on an insulating substrate, 72 denotes a semiconductor element, 73 denotes a discrete component, 74 denotes a solder bump in a flip chip method,
Reference numeral 75 denotes wiring on the wiring board.

【0008】また図8は、図7に示した第2の従来例の
フリップチップ法を用いたハイブリッドICの製造工程
の1例を示したものである。
FIG. 8 shows an example of a manufacturing process of a hybrid IC using the flip chip method of the second conventional example shown in FIG.

【0009】図8において、配線75を形成した配線基
板71(図8(a))上に半導体素子72とディスクリ
ート部品73をソルダーペースト76等と共に載置する
(図8(b))。次にはんだリフロー法により半導体素
子72、ディスクリート部品73を配線基板71に搭載
する(図8(c))。
Referring to FIG. 8, a semiconductor element 72 and a discrete component 73 are placed together with a solder paste 76 and the like on a wiring board 71 (FIG. 8A) on which a wiring 75 is formed (FIG. 8B). Next, the semiconductor element 72 and the discrete component 73 are mounted on the wiring board 71 by a solder reflow method (FIG. 8C).

【0010】[0010]

【発明が解決しようとする課題】しかしながら上記の第
1及び第2の従来の半導体装置の製造方法では、特に半
導体装置が高速動作を要求されるハイブリッドICの場
合において以下のような問題点が生じる。
However, the first and second conventional methods for manufacturing a semiconductor device have the following problems particularly in the case of a hybrid IC that requires a high-speed operation of the semiconductor device. .

【0011】上記した従来の半導体装置を例えば20〜
60GHZのような高周波動作させた場合、ディスクリー
ト部品の容量のばらつき、ワイヤボンディングのワイヤ
54の浮遊容量やインダクタンス、及び、フリップチッ
プ実装時にバンプ74高さの制御ができないことや比較
的大きなボンディングパッドを必要とする等のために半
導体素子と配線基板間に生じる不必要な浮遊容量等が、
回線基板の配線の伝送特性に大きく影響してしまい、設
計通りの性能を引き出すことができない。すなわち、従
来の半導体装置は、高周波動作させた際に、ばらつきの
ある浮遊容量がハイブリッドIC等の半導体装置の正確
な動作を妨げるという問題点を有していた。
The above-described conventional semiconductor device is, for example, 20 to
When operated at a high frequency such as 60 GHZ, the dispersion of the capacitance of the discrete components, the stray capacitance and inductance of the wire 54 for wire bonding, and the inability to control the height of the bump 74 during flip chip mounting and the use of relatively large bonding pads Unnecessary stray capacitance generated between the semiconductor element and the wiring board due to
The transmission characteristics of the wiring on the circuit board are greatly affected, and the performance as designed cannot be obtained. That is, the conventional semiconductor device has a problem that when operated at a high frequency, the stray capacitance with variation hinders the accurate operation of a semiconductor device such as a hybrid IC.

【0012】本発明は上記問題点に鑑みてなされたもの
であり、従来の半導体装置において存在してた浮遊容量
を最小限にし、かつ、この最小限の浮遊容量を逆に利用
して種々の容量を制御できる半導体装置を提供すること
を目的としている。また本発明は、上記したように浮遊
容量を制御することにより正確な受動回路を有し、伝送
される信号の損失を低減し、消費電力を低減する半導体
装置を提供することを目的としている。さらに本発明
は、容量の測定を行って半導体素子等の電子部品と基板
間の正確な距離の制御を行うことができる半導体装置を
提供することを目的としている。
The present invention has been made in view of the above-mentioned problems, and minimizes the stray capacitance existing in a conventional semiconductor device, and variously utilizes the minimum stray capacitance in reverse. It is an object to provide a semiconductor device whose capacity can be controlled. Another object of the present invention is to provide a semiconductor device which has an accurate passive circuit by controlling the stray capacitance as described above, reduces loss of a transmitted signal, and reduces power consumption. A further object of the present invention is to provide a semiconductor device capable of measuring a capacitance and accurately controlling a distance between an electronic component such as a semiconductor element and a substrate.

【0013】[0013]

【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体装置は、ボンディングパッドを有す
る配線基板と、金属突起を介して前記ボンディングパッ
ドに接続された電子部品と、前記配線基板と前記電子部
品との間に形成され前記電子部品を前記配線基板に固定
する樹脂と、前記配線基板と前記電子部品間の容量を測
定する手段とを備えた構成を有している。
In order to solve the above problems, a semiconductor device according to the present invention comprises: a wiring board having a bonding pad; an electronic component connected to the bonding pad via a metal projection; It has a configuration provided with a resin formed between the substrate and the electronic component and for fixing the electronic component to the wiring substrate, and a unit for measuring a capacitance between the wiring substrate and the electronic component.

【0014】また本発明の半導体装置の製造方法として
は、電子部品を搭載する配線基板上に前記電子部品を固
定する樹脂を塗布する樹脂塗布工程と、前記配線基板上
のボンディングパッドと前記電子部品の金属突起とを位
置合わせする電子部品位置合わせ工程と、前記電子部品
を加圧して前記金属突起を介して前記ボンディングパッ
ドに接続する電子部品加圧工程と、前記配線基板と前記
電子部品間の容量を測定する容量測定工程と、前記容量
測定工程により得られた情報を基にして前記電子部品の
前記ボンディングパッドへの加圧量を調整する電子部品
加圧調整工程と、前記樹脂を硬化させる樹脂硬化工程と
を備えた構成を有している。
The method of manufacturing a semiconductor device according to the present invention includes a resin application step of applying a resin for fixing the electronic component on a wiring board on which the electronic component is mounted, a bonding pad on the wiring board and the electronic component. An electronic component alignment step of aligning the metal projection with the electronic component; an electronic component pressing step of pressing the electronic component to connect to the bonding pad via the metal projection; A capacitance measuring step of measuring a capacitance, an electronic component pressure adjusting step of adjusting a pressing amount of the electronic component to the bonding pad based on information obtained in the capacitance measuring step, and curing the resin And a resin curing step.

【0015】[0015]

【作用】上記した構成により、電子部品と配線基板間の
間隔を正確に制御しすることにより、浮遊容量を出来る
だけ小さくし、かつ従来浮遊容量であったものを利用し
て所望の容量を形成することができる。
With the above arrangement, the stray capacitance can be reduced as much as possible by precisely controlling the distance between the electronic component and the wiring board, and a desired capacitance can be formed by using a conventional stray capacitance. can do.

【0016】[0016]

【実施例】以下に本発明の実施例における半導体装置お
よびその製造方法について図面を参照しながら説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to the drawings.

【0017】図1は本発明の実施例における半導体装置
の真上から見た正面図を示したものである。
FIG. 1 is a front view of a semiconductor device according to an embodiment of the present invention as viewed from directly above.

【0018】また、図2は本発明の実施例における半導
体装置の断面図を示したものであり、図2(a)は図1
内のA−A’ライン部分の断面図、図2(b)はB−
B’ライン部分の断面図を示したものである。
FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
FIG. 2B is a cross-sectional view taken along the line AA ′ in FIG.
FIG. 3 shows a cross-sectional view of a B ′ line portion.

【0019】図1及び図2において、1はマイクロスト
リップ線路等の配線を形成した配線基板、2はフェース
ダウンで搭載された半導体素子等の電子部品、3は配
線、4は容量を測定するためのプロービングパッド、5
はグランドパッド、6はグランド面、7は電子部品2と
配線基板1との接続を行うための金属突起(以下、単に
バンプと呼ぶ)、8はボンディングパッド、9はバンプ
7による電子部品2と配線基板1との接続を固定する光
硬化性絶縁樹脂、15は絶縁膜を示したものである。
In FIGS. 1 and 2, 1 is a wiring board on which wiring such as a microstrip line is formed, 2 is an electronic component such as a semiconductor element mounted face-down, 3 is a wiring, and 4 is a capacitor for measuring capacitance. Probing pads, 5
Is a ground pad, 6 is a ground plane, 7 is a metal projection (hereinafter simply referred to as a bump) for connecting the electronic component 2 and the wiring board 1, 8 is a bonding pad, and 9 is the electronic component 2 by the bump 7. A photo-curing insulating resin 15 for fixing the connection with the wiring board 1, and 15 denotes an insulating film.

【0020】次に、図3は上記した本発明の実施例にお
ける半導体装置の製造方法工程を示したものである。
FIG. 3 shows the steps of a method for manufacturing a semiconductor device according to the embodiment of the present invention.

【0021】まず、マイクロストリップ線路等の配線3
を形成した配線基板1上に、光硬化性絶縁樹脂9を塗布
し、バンプ7を形成した電子部品2を配線基板1上の対
応したボンディングディングパッド8に位置合わせする
(図3(a))。
First, wiring 3 such as a microstrip line
A photocurable insulating resin 9 is applied on the wiring board 1 on which the wiring board 1 is formed, and the electronic component 2 on which the bumps 7 are formed is aligned with the corresponding bonding pad 8 on the wiring board 1 (FIG. 3A). .

【0022】次に加圧ツール11により光硬化性樹脂を
介して、電子部品2を加圧する。本発明では、図3
(b)に示すように、加圧ツール11により電子部品2
を加圧しているときその加圧状態を測定し、電子部品2
と配線基板1との間隔(すなわちバンプ7の高さ)を正
確に制御して、浮遊容量を制御する。具体的には、図3
(b)に示すように、プロービングパッド4にネットワ
ークアナライザのプローブ10を接触させ、これにより
例えばSパラメータを測定して、電子部品2と配線基板
1間の浮遊容量を制御する。測定したSパラメータは図
4に示すようにスミスチャート上等に表示し、シミュレ
ーション値または他の試料の実測値12と搭載中の測定
値13が一致するように加圧ツール11の加圧量を調節
する。
Next, the electronic component 2 is pressed by the pressing tool 11 via the photocurable resin. In the present invention, FIG.
As shown in (b), the electronic component 2 is
When the electronic component 2 is being pressed,
The stray capacitance is controlled by accurately controlling the distance between the wiring board 1 and the wiring board 1 (that is, the height of the bump 7). Specifically, FIG.
As shown in (b), the probe 10 of the network analyzer is brought into contact with the probing pad 4, thereby measuring, for example, the S parameter to control the stray capacitance between the electronic component 2 and the wiring board 1. The measured S-parameters are displayed on a Smith chart or the like as shown in FIG. 4, and the amount of pressurization of the pressurizing tool 11 is adjusted so that the simulated value or the actually measured value 12 of another sample matches the measured value 13 during mounting. Adjust.

【0023】この時、高周波領域ではSパラメータを測
定したが、低周波領域では直接L,C,Rメーター等で
容量値を測定することも可能である。高周波領域の場合
はグランドが必要となるため、プロービングパッド4の
近傍にはグランドパッド5が形成されているが、低周波
の場合、プロービングパッド横のグランドパッド5は形
成する必要はない。
At this time, the S parameter was measured in the high frequency region, but the capacitance value can be directly measured by an L, C, R meter or the like in the low frequency region. The ground pad is formed near the probing pad 4 because a ground is required in the high frequency region, but the ground pad 5 beside the probing pad need not be formed in the low frequency region.

【0024】さらに加圧ツール11の加圧量を最適と
し、その荷重を保った状態で紫外線光14を照射し光硬
化性絶縁樹脂9を硬化する(図3(c))。その後、加
圧ツール11を取り除き電子部品2の配線基板1への搭
載を終了する。
Further, the amount of pressurization of the pressurizing tool 11 is optimized, and the photocurable insulating resin 9 is cured by irradiating ultraviolet light 14 while maintaining the load (FIG. 3C). Thereafter, the pressing tool 11 is removed, and the mounting of the electronic component 2 on the wiring board 1 is completed.

【0025】上記の実施例では測定されたSパラメータ
を所望の値に一致させることにより、加圧ツール11の
加圧量を調整して、電子部品2と配線基板1の間の容量
を最適にしたが、Sパラメータを測定することにより電
子部品2と配線基板1の間隔を正確に知ることも可能で
ある。
In the above embodiment, by adjusting the measured S parameter to a desired value, the amount of pressure applied by the pressing tool 11 is adjusted to optimize the capacity between the electronic component 2 and the wiring board 1. However, the distance between the electronic component 2 and the wiring board 1 can be accurately known by measuring the S parameter.

【0026】本実施例において加圧ツール11の加圧量
の調整に基づく電子部品2と配線基板1間の距離以外
に、光硬化性絶縁樹脂9の誘電率を変化させてやって
も、種々の所望の容量、損失等を得ることができる。
In the present embodiment, even if the dielectric constant of the photocurable insulating resin 9 is changed in addition to the distance between the electronic component 2 and the wiring board 1 based on the adjustment of the amount of pressing of the pressing tool 11, Desired capacity, loss, etc. can be obtained.

【0027】また、本実施例では光硬化性絶縁樹脂9を
用いたが、接着性を有する樹脂である熱硬化性、熱可塑
性等の樹脂に置き換えることも可能である。
In this embodiment, the photocurable insulating resin 9 is used. However, the photocurable insulating resin 9 may be replaced with a resin having adhesive properties such as thermosetting resin or thermoplastic resin.

【0028】[0028]

【発明の効果】以上の説明から明らかなように、本発明
は配線基板と配線基板に実装される電子部品の容量を測
定する手段を備え、この手段からの出力により電子部品
を実装する際の加圧ツールによる加圧量を調整するた
め、電子部品と配線基板間の間隔を正確に制御すること
ができる。従って、浮遊容量を最小限に抑制し、かつ従
来浮遊容量であったものを利用して所望の容量を形成す
ることができる。また、絶縁樹脂の誘電率を変化させて
種々の容量を設定してやれば、高速動作するハイブリッ
ドICにおいて正確な受動回路を形成することができ、
伝送される信号の損失を低減し、消費電力を低減するこ
ともできる。さらに、容量を測定することにより正確な
半導体素子等の電子部品と基板間の距離の制御を行うこ
とを可能とする。
As is apparent from the above description, the present invention comprises a wiring board and a means for measuring the capacitance of the electronic component mounted on the wiring board. Since the amount of pressurization by the pressurizing tool is adjusted, the distance between the electronic component and the wiring board can be accurately controlled. Therefore, the stray capacitance can be suppressed to a minimum, and a desired capacitance can be formed using a stray capacitance that has been conventionally used. Further, if various capacitances are set by changing the dielectric constant of the insulating resin, an accurate passive circuit can be formed in a hybrid IC operating at high speed.
Loss of a transmitted signal can be reduced, and power consumption can be reduced. Further, it is possible to accurately control the distance between an electronic component such as a semiconductor element and a substrate by measuring the capacitance.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例における半導体装置の正面図FIG. 1 is a front view of a semiconductor device according to an embodiment of the present invention.

【図2】本発明の実施例における半導体装置の断面図FIG. 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

【図3】本発明の実施例における半導体装置の製造工程
FIG. 3 is a manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

【図4】本発明の実施例における配線基板と電子部品間
の容量を測定する手段により測定されたSパラメータを
表示したスミスチャート
FIG. 4 is a Smith chart displaying S-parameters measured by a unit for measuring a capacitance between a wiring board and an electronic component according to the embodiment of the present invention.

【図5】第1の従来例におけるワイヤボンディング法を
用いたハイブリッドICの正面図
FIG. 5 is a front view of a hybrid IC using a wire bonding method in a first conventional example.

【図6】第1の従来例におけるワイヤボンディング法を
用いたハイブリッドICの製造工程図
FIG. 6 is a manufacturing process diagram of a hybrid IC using a wire bonding method in a first conventional example.

【図7】第2の従来例におけるフリップチップ法を用い
たハイブリッドICの正面図
FIG. 7 is a front view of a hybrid IC using a flip chip method in a second conventional example.

【図8】第2の従来例におけるフリップチップ法を用い
たハイブリッドICの製造工程図
FIG. 8 is a manufacturing process diagram of a hybrid IC using a flip chip method in a second conventional example.

【符号の説明】[Explanation of symbols]

1 マイクロストリップ線路等の配線を形成した配線基
板 2 半導体素子等の電子部品 3 配線 4 プロービングパッド 5 グランドパッド 6 グランド面 7 バンプ 8 ボンディングパッド 9 光硬化性絶縁樹脂 10 プローブ 11 加圧ツール 12 Sパラメータのシュミレーション値 13 Sパラメータの実測値 14 紫外光 15 絶縁膜 51 配線基板 52 半導体素子 53 ディスクリート部品 54 ワイヤ 55 配線 56 導電性接着剤 57 電極パッド 71 半導体基板 72 半導体素子 73 ディスクリート部品 74 はんだバンプ 75 配線 76 ソルダペースト
Reference Signs List 1 Wiring board on which wiring such as microstrip line is formed 2 Electronic component such as semiconductor element 3 Wiring 4 Probing pad 5 Ground pad 6 Ground plane 7 Bump 8 Bonding pad 9 Photocurable insulating resin 10 Probe 11 Pressure tool 12 S parameter Simulation value of 13 S-parameter measured value 14 Ultraviolet light 15 Insulating film 51 Wiring board 52 Semiconductor element 53 Discrete part 54 Wire 55 Wiring 56 Conductive adhesive 57 Electrode pad 71 Semiconductor substrate 72 Semiconductor element 73 Discrete part 74 Solder bump 75 Wiring 76 Solder paste

───────────────────────────────────────────────────── フロントページの続き (72)発明者 酒井 啓之 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 井上 薫 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 311 H01L 25/04 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroyuki Sakai 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Kaoru 1006 Kadoma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/60 311 H01L 25/04

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ボンディングパッドを有する配線基板と、
金属突起を介して前記ボンディングパッドに接続された
電子部品と、前記配線基板と前記電子部品との間に形成
され前記電子部品を前記配線基板に固定する樹脂と、前
記配線基板と前記電子部品間の容量を測定する手段とを
備えた半導体装置。
A wiring board having a bonding pad;
An electronic component connected to the bonding pad via a metal protrusion; a resin formed between the wiring board and the electronic component for fixing the electronic component to the wiring board; and a resin between the wiring board and the electronic component. Means for measuring the capacitance of the semiconductor device.
【請求項2】配線基板と電子部品間の距離を測定する手
段として、プロービングパッドが配線基板上に設けられ
たことを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a probing pad is provided on the wiring board as means for measuring a distance between the wiring board and the electronic component.
【請求項3】電子部品を搭載する配線基板上に前記電子
部品を固定する樹脂を塗布する樹脂塗布工程と、前記配
線基板上のボンディングパッドと前記電子部品の金属突
起とを位置合わせする電子部品位置合わせ工程と、前記
電子部品を加圧して前記金属突起を介して前記ボンディ
ングパッドに接続する電子部品加圧工程と、前記配線基
板と前記電子部品間の容量を測定する容量測定工程と、
前記容量測定工程により得られた情報を基にして前記電
子部品の前記ボンディングパッドへの加圧量を調整する
電子部品加圧調整工程と、前記樹脂を硬化させる樹脂硬
化工程とを備えた半導体装置の製造方法。
3. A resin coating step of coating a resin fixing the electronic component on a wiring board on which the electronic component is mounted, and positioning the bonding pad on the wiring board with a metal projection of the electronic component. An alignment step, an electronic component pressing step of pressing the electronic component to connect to the bonding pad via the metal protrusion, and a capacitance measuring step of measuring a capacitance between the wiring board and the electronic component,
A semiconductor device comprising: an electronic component pressure adjusting step of adjusting an amount of pressure applied to the bonding pad of the electronic component based on information obtained in the capacitance measuring step; and a resin curing step of curing the resin. Manufacturing method.
【請求項4】容量測定工程において、前記加圧工程中に
配線基板上に設けられたプロービングパッドからSパラ
メータ、容量を測定し、容量の最適値を決定することを
特徴とする請求項3記載の半導体装置の製造方法。
4. The capacitance measuring step, wherein an S-parameter and a capacitance are measured from a probing pad provided on the wiring board during the pressing step, and an optimum value of the capacitance is determined. Of manufacturing a semiconductor device.
【請求項5】配線基板上に前記電子部品を固定する樹脂
に、異なった誘電率の樹脂を用いて容量を調整を行うこ
とを特徴とする請求項3記載の半導体装置の製造方法。
5. The method for manufacturing a semiconductor device according to claim 3, wherein the capacitance is adjusted by using resins having different dielectric constants as a resin for fixing the electronic component on the wiring board.
JP6106548A 1994-05-20 1994-05-20 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3024900B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6106548A JP3024900B2 (en) 1994-05-20 1994-05-20 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6106548A JP3024900B2 (en) 1994-05-20 1994-05-20 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH07321149A JPH07321149A (en) 1995-12-08
JP3024900B2 true JP3024900B2 (en) 2000-03-27

Family

ID=14436416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6106548A Expired - Fee Related JP3024900B2 (en) 1994-05-20 1994-05-20 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3024900B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100331553B1 (en) * 1999-09-16 2002-04-06 윤종용 Integrated circuit device having a pad which allows for multiple probing and reliable bonding
JP2013102356A (en) * 2011-11-08 2013-05-23 Panasonic Corp Wireless unit and manufacturing method thereof
US11849545B2 (en) * 2018-10-16 2023-12-19 Fuji Corporation Circuit formation method

Also Published As

Publication number Publication date
JPH07321149A (en) 1995-12-08

Similar Documents

Publication Publication Date Title
US5594358A (en) Radio frequency probe and probe card including a signal needle and grounding needle coupled to a microstrip transmission line
US20090050887A1 (en) Chip on film (cof) package having test pad for testing electrical function of chip and method for manufacturing same
JPH05283487A (en) Wiring for high-frequency signal and bonding device therefor
US7988059B2 (en) Method for connecting an electronic chip to a radiofrequency identification device
US6507118B1 (en) Multi-metal layer circuit
US6475824B1 (en) X-ray detector and method of fabricating the same
JP3024900B2 (en) Semiconductor device and manufacturing method thereof
US20030151113A1 (en) Semiconductor device
KR100973268B1 (en) Printed circuit board and method of fabricating the same
US5767569A (en) Tab tape and semiconductor chip mounted on tab tape
JPH0936617A (en) High frequency module
JP3319269B2 (en) Electronic component joining method
JP3517701B2 (en) IC mounting method
US20050275099A1 (en) Semiconductor apparatus and method of manufacturing semiconductor apparatus
JPH06275675A (en) Tab package and its connection
KR20000046722A (en) Method for direct attachment bonding semiconductor chips
JP3779504B2 (en) Manufacturing method of semiconductor module
JP2712654B2 (en) Electronic component mounting structure and manufacturing method
JP3279461B2 (en) Semiconductor device, wiring board, and manufacturing method thereof
KR20030048691A (en) low value, low variation high frequency inductor and method for manufacturing the same
JPH11204572A (en) Mounting structure of semiconductor device and manufacture thereof
JP2004327946A (en) High frequency inductor having low inductance and low inductance variation and its manufacturing method
JPH10289929A (en) Mounting method of surface mount part
JPH07283269A (en) Bonding method between electrode pattern and bump electrode pattern on circuit substrate
JP2001217647A (en) Adjustment of automatic voltage-controlled oscillator

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080121

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090121

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090121

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100121

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110121

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110121

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120121

Year of fee payment: 12

LAPS Cancellation because of no payment of annual fees