JP3019525B2 - Digital PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL circuit used for receiving and demodulating an AES / EBU digital audio signal or the like.

[0002]

2. Description of the Related Art Digital PLL used for receiving and demodulating AES / EBU digital audio signals and the like.
Conventionally, a circuit shown in FIG. 3 is known. The digital PLL circuit shown in the figure includes a differentiating circuit 101, a synchronization target extracting circuit 102, a frequency comparing circuit 103, a low-pass filter circuit 104, a VCO circuit 105,
And a T measurement circuit 106. When an input signal is supplied, a portion to be synchronized in the input signal is extracted, and a clock signal of a predetermined frequency synchronized with the portion to be synchronized, for example, a clock signal of 128 fs And outputs it to the next stage circuit (not shown).

When an input signal as shown in FIG. 4A is supplied, a differentiating circuit 101 digitally differentiates the input signal to obtain a transient signal (showing an edge of the input signal) shown in FIG. Signal) and supplies it to the synchronization target extraction circuit 102 and the VCO circuit 105. The synchronization target extraction circuit 102 measures the length between the transients based on the transient signal output from the differentiating circuit 101, and the length obtained by this measurement operation is the preamble Y shown in FIG. Part 3T
Section (longest section between transients)
, A reference signal is generated and supplied to the frequency comparison circuit 103. As shown in FIG. 4 (c), the frequency comparison circuit 103 performs the above-described operation based on the reference signal output from the synchronization target extraction circuit 102 and the 3T detection signal output from the 3T measurement circuit 106.
A frequency control signal having a value necessary to insert three periods of the 128 fs clock signal during the T section is generated and supplied to the low-pass filter circuit 104.

[0004] The low-pass filter circuit 104 cuts off the high-frequency component of the frequency control signal output from the frequency comparison circuit 103 and supplies it to the VCO circuit 105. VCO
The circuit 105 oscillates at a frequency corresponding to the frequency control signal output from the low-pass filter circuit 104 to generate a 128 fs clock signal synchronized with the transient signal output from the differentiating circuit 101, and sends the clock signal to the next-stage circuit. The signal is output and supplied to the 3T measurement circuit 106. The 3T measurement circuit 106 generates a 3T detection signal when the length becomes three cycles based on the 128 fs clock signal output from the VCO circuit 105 and supplies this to the frequency comparison circuit 103.

As described above, in this digital PLL circuit, when an input signal is supplied, the 3T section of the pre-ambro Y section to be synchronized in the input signal is extracted, and A synchronized 128 fs clock signal is generated and output to the next stage circuit.

[0006]

However, in the above-described conventional digital PLL circuit, the master clock signal obtained by the timer (not shown) is supplied to the synchronization target extraction circuit 102, and the master clock signal is counted. Since the length between transients is measured and a reference signal is generated based on the measurement result, when the frequency of the master clock signal is low, sufficient synchronization accuracy cannot be secured, and There is a problem that it is not possible to cope with a frequency shift of a signal or the like.

The present invention has been made in view of the above circumstances, and provides a digital PLL circuit capable of ensuring sufficient synchronization accuracy and coping with a frequency shift of an input signal even when the frequency of a master clock signal is low. It is an object.

[0008]

In order to achieve the above object, a digital PLL circuit according to the present invention extracts a portion to be synchronized of an input signal, controls an oscillation frequency of a VCO circuit, and responds to the portion to be synchronized. A digital PLL circuit that generates a clock signal obtained by extracting a coarse synchronization target portion from a synchronization target portion of the input signal and controls an oscillation frequency of the VCO circuit to generate a clock signal corresponding to the coarse synchronization target portion A coarse synchronization loop circuit for extracting a precise synchronization target portion in the synchronization target portion of the input signal and controlling the oscillation frequency of the VCO circuit to generate a clock signal corresponding to the precision synchronization target portion And when the VCO circuit is not locked to the input signal, the coarse synchronous loop circuit is selected to perform a sweep operation. After coarse synchronization loop circuit is locked by the sweep operation, it is characterized by having a loop and switching circuit for locking the VCO circuit to the input signal by selecting the fine synchronization loop circuit.

[0009]

In the above configuration, the VCO is applied to the input signal.
When the circuit is not locked, a coarse synchronization loop circuit is selected by the loop switching circuit to extract a coarse synchronization target portion in the synchronization target portion of the input signal, and the VCO circuit oscillates based on the coarse synchronization target portion. The frequency is controlled to perform a sweeping operation.
After the coarse lock of the CO circuit is completed, the precision switching loop circuit is selected by the loop switching circuit to extract the precision synchronization target portion in the synchronization target portion of the input signal, and the VCO circuit is selected based on the precision synchronization target portion. Is controlled to lock the VCO circuit with respect to the input signal.

[0010]

FIG. 1 is a block diagram showing an embodiment of a digital PLL circuit according to the present invention. The digital PLL circuit shown in this figure includes a differentiating circuit 1, a coarse synchronization object extracting circuit 2,
It includes a precise synchronization target extraction circuit 3, a switch circuit 4, a frequency comparison circuit 5, a low-pass filter circuit 6, a VCO circuit 7, a 3T measurement circuit 8, a 6T measurement circuit 9, and a lock determination circuit 10. When an input signal is supplied, first, a 3T section of the pre-ambro Y section to be synchronized in the input signal is extracted, and the 3T section is extracted.
The loop is synchronized based on the T section, and after this synchronization processing is completed, a 6T section of the pre-ambro Y section to be synchronized in the input signal is extracted, and a loop is formed based on the 6T section. , A clock signal of a preset frequency, for example, a clock signal of 128 fs is generated, and this is supplied to a next-stage circuit (not shown).
Output to

When an input signal as shown in FIG. 2A is supplied, the differentiating circuit 1 digitally differentiates the input signal to obtain a transient signal (showing an edge of the input signal) shown in FIG. 2B. Signal, and supplies it to the coarse synchronization target extraction circuit 2, the fine synchronization target extraction circuit 3, and the VCO circuit 7. The coarse synchronization object extraction circuit 2 measures the length between the transients based on the transient signal output from the differentiating circuit 1, and the length obtained by this measurement operation is the pre-ambro shown in FIG. When the length of the section 3T coincides with the length of the 3T section (the longest section between transients), a coarse reference signal is generated and supplied to the switch circuit 4.

The precise synchronization object extraction circuit 3 determines the length between the transients based on the transient signal output from the differentiating circuit 1, the input signal, and the clock signal of 128 fs output from the VCO circuit 7. When a 6T section of the preamble Y section shown in FIG. 2A is detected by this measuring operation, a precise reference signal is generated and supplied to the switch circuit 4. The switch circuit 4 selects one of a coarse reference signal output from the coarse synchronization target extraction circuit 2 and a precision reference signal output from the fine synchronization target extraction circuit 3 based on the output of the lock determination circuit 10. And a switch 12 for selecting one of a 3T detection signal output from the 3T measurement circuit 8 and a 6T detection signal output from the 6T measurement circuit 9 in conjunction with the switch 11. 10 is a pair of the coarse reference signal output from the coarse synchronization target extraction circuit 2 and the 3T detection signal output from the 3T measurement circuit 8 or the precision reference signal output from the fine synchronization target extraction circuit 3 And a 6T detection signal output from the 6T measurement circuit 9, and supplies it to the frequency comparison circuit 5. To.

When a coarse reference signal and a 3T detection signal are output from the switch circuit 4, the frequency comparison circuit 5 outputs the 3T signal based on the coarse reference signal and the 3T detection signal as shown in FIG. 1 during section
A frequency control signal having a value necessary for inserting three periods of the 28 fs clock signal is generated, and this is
When the precision reference signal and the 6T detection signal are output from the switch circuit 4, based on the precision reference signal and the 6T detection signal, during the 6T section as shown in FIG. A frequency control signal having a value necessary to input six periods of the 128 fs clock signal is generated and supplied to the low-pass filter circuit 6.

The low-pass filter circuit 6 cuts off the high-frequency component of the frequency control signal output from the frequency comparison circuit 5 and supplies it to the VCO circuit 7. The VCO circuit 7 oscillates at a frequency corresponding to the frequency control signal output from the low-pass filter circuit 6 to generate a 128 fs clock signal synchronized with the transient signal output from the differentiating circuit 1, And output to 3
T measurement circuit 8, 6T measurement circuit 9, lock determination circuit 1
0 and supply. When detecting the length of three periods based on the 128 fs clock signal output from the VCO circuit 7, the 3T measurement circuit 8 generates a 3T detection signal and supplies it to the switch circuit 4.

The 6T measuring circuit 9 is provided by the VCO circuit 7.
6 based on the 128 fs clock signal output from
When the length of the cycle is detected, a 6T detection signal is generated and supplied to the switch circuit 4. Further, the lock determination circuit 10 outputs 128 fs output from the VCO circuit 7.
And determining whether the clock signal is in a locked state based on the clock signal and the input signal. If the clock signal is not in a locked state, a coarse synchronization command signal is generated to generate the switch signal. Each switch 1 of 4
1 and 12 to select a coarse reference signal output from the coarse synchronization target extraction circuit 2 and a 3T detection signal output from the 3T measurement circuit 8 and supply them to the frequency comparison circuit 5 to perform coarse synchronization. Perform the operation. Thereafter, when the clock signal is in a locked state, a precise synchronization command signal is generated and each switch 11, 1
2 to select the precision reference signal output from the precision synchronization object extraction circuit 3 and the 6T detection signal output from the 6T measurement circuit 9 and supply them to the frequency comparison circuit 5 to perform the precision synchronization operation. Let

As described above, in this digital PLL circuit, when an input signal is supplied, first, the pre-amplifier Y section in the input signal, which is a synchronization target, has a 3
The synchronization operation is performed based on the T section, and after the completion of the synchronization operation, the synchronization operation is performed based on the 6T section of the preamble Y section. Even when a signal is used, the synchronization accuracy can be doubled, and thereby sufficient synchronization accuracy can be ensured even for a frequency shift (vari speed) required for professional audio equipment and the like. .

[0017]

As described above, according to the present invention, even when the frequency of the master clock signal is low, sufficient synchronization accuracy can be ensured to cope with the frequency shift of the input signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a digital PLL circuit according to the present invention.

FIG. 2 is a timing chart showing an operation example of the digital PLL circuit shown in FIG.

FIG. 3 is a block diagram showing an example of a conventionally known digital PLL circuit.

FIG. 4 is a timing chart showing an operation example of the digital PLL circuit shown in FIG. 3;

[Description of Signs] 2 Coarse Synchronous Symmetry Extraction Circuit (Coarse Synchronous Loop Circuit) 3 Precise Synchronous Symmetry Extraction Circuit (Precision Synchronous Loop Circuit) 4 Switch Circuit (Loop Switching Circuit) 7 VCO Circuit 8 3T Measurement Circuit (Coarse Synchronous Loop Circuit) 9 6T measurement circuit (precision synchronous loop circuit) 10 Lock judgment circuit (loop switching circuit)

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 7/033 H03L 7/08

Claims (1)

(57) [Claims] 1. A synchronization target portion of an input signal is extracted and VC
In a digital PLL circuit that controls an oscillation frequency of an O circuit and generates a clock signal corresponding to the synchronization target portion, a coarse synchronization target portion in a synchronization target portion of the input signal is extracted to set an oscillation frequency of the VCO circuit. A coarse synchronization loop circuit for controlling and generating a clock signal corresponding to the coarse synchronization target portion; extracting a fine synchronization target portion in the synchronization target portion of the input signal and controlling an oscillation frequency of the VCO circuit; A precision synchronization loop circuit for generating a clock signal corresponding to a precision synchronization target portion; and when the VCO circuit is not locked to the input signal, selecting the coarse synchronization loop circuit to perform a sweep operation. After the coarse synchronous loop circuit is locked by the sweep operation, the fine synchronous loop circuit is selected to lock the VCO circuit with respect to the input signal. Digital PLL circuit, characterized in that it includes loops and switching circuit to click, the.