JP3016293B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for driving a solid-state imaging device having a transfer-type solid-state imaging device such as a charge-coupled device (CCD).
The present invention relates to a solid- state imaging device in which power consumption in a solid-state imaging device at a transfer frequency is reduced , frequency characteristics are further improved, and transfer clock modulation is ensured even at a low frequency.

[0002]

2. Description of the Related Art Conventionally, when driving a solid-state image pickup device, a chip is used.
A solid-state imaging device such as a large couple device is a driving circuit
From the viewpoint of capacitance (capacitor) load
Because, although small driving circuit output impedance have been used, the output impedance of the actual driving circuit is not a 0 .OMEGA, actual power consumption P defined by the following equation occurs in.

[0003]

(Equation 1)

[0004] However, C _D represents the capacitance of the solid-state imaging device, V is represents the amplitude voltage of the drive clock applied to the solid-state imaging device, f is shows a driving frequency of the solid-state imaging device.

[0005] In particular, in recent years , high precision display devices have been developed.
When a solid-state imaging device is used for a display device,
As the number of pixels in the image element increases, a large amount of
The driving frequency of the solid-state imaging device has also been increased to transfer charges.
You. As a result, as is apparent from Equation 1, the power consumption increases, and the increase in power consumption accompanying the increase in the number of pixels has become a problem.

Therefore, one of the above-described methods for reducing power consumption is described below .
As a method , a switching resonance method using a resonance circuit and a switching element has been proposed (for example, “High-speed driving method of solid-state imaging device for Hi-Vision”, Ide et al.,
1988 IEICE Spring National Convention, D-136
reference).

FIG. 5 shows an equivalent circuit of the horizontal transfer CCD section 10 and a switching resonance drive circuit for driving the CCD section . As described in the above document, horizontal transfer C
The CD unit 10 includes a plurality of CCs arranged in a vertical and horizontal matrix.
D, and the horizontal transfer CCD is CC in the horizontal direction (horizontal direction).
The charge stored in D is transferred. Figure 5 is a simplified illustration
Therefore, a typical CCD and its driving circuit are illustrated.
ing. Each CCD of the CCD section 10 has a gate resistor R
_G1, R _G2, substrate resistance R _S1, R _S2, electrode capacitance CC _1, CC
_2, and an equivalent circuit in which the coupling capacitance C _C is connected as shown in the figure. Note that such individual C
An outline of the impedance of the CD is as shown in Expression 1,
It can be represented as a capacitor C _D. in this way,
Each CCD is equivalently shown as a capacitor component.
Is, for example, Japanese Unexamined Patent Publication No.
FIG. 4 to FIG. 4, JP-A-1-303758, FIG.
It is disclosed in FIG. 3 and the like.

The switching resonance drive circuit for driving the CCD unit 10 includes a driver circuit 22, a capacitor 23,
A first resistor 24, a second resistor 25, a transistor 2
6 and the variable inductance element 27 are connected as shown. Also on the right side of the node Nb of the CCD unit 10,
A circuit similar to the first switching resonance drive circuit on the left side of the illustrated node Na and a second switching resonance circuit are provided.
But illustration is omitted. The first switch
6A is connected to the input terminal 21 of the resonance circuit.
The transmission driving pulse voltage V is applied, but the second switching
Input terminal (terminal corresponding to terminal 21) of the resonance circuit
A voltage having a polarity opposite to that of the voltage illustrated in FIG.
Therefore, the first switching resonance circuit and the second switching
The operation is opposite to that of the resonance circuit. Hereinafter, the first switch
The following describes mainly the resonance circuit.

The collector of transistor 26 is connected to node Na
It is connected to the variable inductor and through the node Na
And the CCD of the CCD section 10 are connected.
You. The transfer drive pulse voltage V illustrated in FIG. 6A is applied to the terminal 21. When the voltage V is at a high level, the transistor 26 is turned on, and when the voltage V is at a low level, the transistor 26 is turned off. FIG.
The voltage V2 at the node Na is shown. The first switch illustrated
A second switch (not shown) at a symmetrical position on the node Nb side with the first transistor 26 in the switching driver circuit
Transistor (not shown) in the resonance driving circuit
Means , for example, pulsed power during periods other than the horizontal blanking period.
The pressure V is turned on / off at a high driving frequency of about several MHz to several tens MHz .

A high-level voltage V is applied to a terminal 21.
When the transistor 26 is turned on (not shown).
The second transistor is turned off), the voltage +5
V passes through the variable inductance element 27 to ground (large
And the current flows into the variable inductance element 27,
The electromagnetic energy flows into the variable inductance element 27
Stored.

Next, a low-level voltage V is applied to the terminal 21.
To turn off the transistor 26 (not shown).
The second transistor is turned on) and the node N
a becomes a high level, the electromagnetic energy stored in the variable inductance element 27 flows into the CCD unit 10 and C
The CD unit 10 is driven. In a state where the variable inductance element 27 and the CCD unit 10 are connected in series, CC
To minimize the power consumption of the D portion 10, a variable inductance element 27 and the variable inductance element 27 and the CCD electrodeposition
The inductance value of the variable inductance element 27 is defined so that the pole capacitance (capacitor component) forms a series resonance circuit . That is, the variable inductance element
The value of the child 27 is set to a value which constitutes the electrode capacitance and series LC resonant circuit of the CCD unit 10 in the charge transfer driving frequency of the CCD unit 10. When the transistor 26 is off, the current of the inductance element 27 flows through the capacitances CC ₁ and C _C in the CCD as a resonance current, and the node Na
Voltage V2 rises to a high voltage, for example, about 10V.

[0012] again when the voltage V of a high level is applied to the terminal 21 the transistor 26 is turned on (second transistor is turned off), the capacitance of the CCD unit 10 C
The energy stored in C ₁ and C _C is discharged to the ground side and a variable inductance from + 5V
A current flows through the element 27 again, and electromagnetic energy is stored in the variable inductance 27 .

Hereinafter, similarly, the transfer drive pulse voltage V is applied.
The above operation is repeated according to the
Is accumulated in the horizontal direction. This
A variable inductance element that constitutes a series resonance circuit
Node which is a connection point between 27 and the CCD in the CCD unit 10
The potential of Na is the pulse voltage V (the
6 (A).

[0014]

The switching resonance type driving circuit described above comprises a variable inductance element 27 and a CC.
Although there is an advantage that power consumption is reduced by forming a series resonance circuit with D, it is considered that practical use is difficult if it is used as it is. For example, Japanese Patent Laid-Open No. 2-274
No. 076, CCD as illustrated in FIG.
With respect to the horizontal transfer of charges in order recently to reduce the number <br/> transfer driving frequency, a plurality of sequences of transfer registers frequently, for example, two series (first horizontal register and the second water
(A flat register) may be provided, but the transfer clock for the transfer between the two series of registers is shown in FIG.
In the low frequency pulse signal, such as illustrated, a horizontal TV signals
(H) It is necessary to perform modulation during the blanking period.

That is, as a modulation operation in the blanking period , for example, at time t1, the data is transferred from the vertical register to the horizontal register, and the first operation is performed at time t2 to t3.
From the horizontal register to the second horizontal register. However, blanking period t1~t4,
When the transistor 26 is turned on / off at a low frequency , as shown in FIG. 6B, the low-frequency component in the time t2 to t3 is cut off, so that desired modulation in the low-frequency region can be performed. Can not. Blanking
Explain why low frequency components are cut during the period
You. The pulse voltage V illustrated in FIG.
As a result, the transistor 26 is turned on as described above.
/ Off operation, the voltage V2 of the node Na is basically
Then, the polarity becomes opposite to the applied voltage V. However, the variable
Responsiveness of inductance component to the conductance element 27
Delay and the charge / discharge characteristics of the CCD unit 10
Due to the delayed response, the voltage V2 of the node NA is reduced as shown in FIG.
A pulse signal whose waveform is blunted as illustrated in FIG.
You. During the horizontal transfer period other than the ranking period t1 to t4
In other words, the frequency of the pulse voltage V is several MHz to several tens MH.
z, the waveform of the voltage V2 at the node Na was distorted.
It becomes the pulse waveform of the state. However, blanking
FIG. 6A shows a pulse signal of a low frequency during the period.
As can be seen, the pulse voltage V having a long high level
When applied to the transistor 26, the transistor 26
The node is turned on and the node Na is also at ground level for a long time.
, Ie, 0V. As a result, the period t2 to t3
During this period, as illustrated in FIG.
2 becomes 0 V and is used as a modulation signal during the blanking period.
I can't use it. Thus, the variable inductance element 27
And a CCD unit 10 to form a series resonance circuit.
When the modulation operation is performed by using the
Encounter problems during the working period. To solve this problem, a complicated circuit is required.

The switching resonance drive circuit illustrated in FIG. 5 includes a variable inductance element 27 and a CCD unit.
If the frequency deviates from the series resonance frequency constituted by the electrode capacitance of the CCD 10, the transfer operation of the CCD unit 10 is not performed. A solid-state imaging device as an object in the present invention is assumed to be operated at frequencies as high as several 10 MH _Z, but transient
In the above-described switching resonance drive method in which the star 26 is turned on / off at a high frequency , the variable inductance element 27
Deviation of the inductance value, a plurality of CC in the CCD unit 10
Consider variations in the capacitance value of D and changes from the design value.
From Erareru, exactly it is difficult to maintain the resonant frequency, problems remain in the stability of operation of the switching resonant circuit described above.

As described above, the driving circuit of the switching resonance type solid-state imaging device has a problem in practicality.

[0018] Having described the case where a CCD is used as the solid-state imaging device having a capacitive load, also encounter the same problems with other solid-state imaging device.

Accordingly, the present invention reduces power consumption in the above-described solid-state imaging device with a simple circuit configuration,
It is another object of the present invention to provide a driving circuit for a solid-state imaging device that enables a stable modulation operation even in a low frequency region.

[0020]

According to the present invention, an electrostatic capacitor is provided.
Construct a parallel resonance circuit with a solid-state image sensor having a quantity component
It has a series circuit of an inductance element and a capacitor,
The resonance frequency of the resonance circuit is equal to the frequency of the drive signal.
The inductance of the above inductance element
The value L ₁ and the capacitance value C ₁ of the capacitor, the co
Solid-state imaging in which the resonance frequency f _T of the oscillation circuit is defined by the following equation
A drive circuit for the device is provided.

[0021]

[Number 2] f _T = _{[(C 1 + C D) /} ((2π) 2 L 1 C 1 C D) ] ^1/2, however, C _D is the value of the capacitance of the solid-state imaging device.

Preferably, the capacitance value C of the capacitor
To ₁ greater than the capacitance value C _D of the solid-state imaging device
You.

Preferably, the solid-state imaging device is a video display.
Is used as shown device, the from the drive signal applying circuit
The voltage applied to the solid-state image sensor is horizontal during the horizontal scanning period.
Change at a first frequency to transfer charge in the
During the ranking period, the charges transferred in the horizontal direction are
Change at a second frequency lower than the first frequency to be transferred
I do .

[0024]

In the transfer type solid-state imaging device having a capacitance component,
Applying a drive signal to the solid-state imaging device and the solid-state imaging device
Inductor provided between the circuit connection point and the power supply
It has a series circuit of an inductance element and a capacitor.
The series circuit of the capacitance element and the capacitor
By configuring a parallel resonance circuit with a solid-state imaging device having a capacitance component, power consumption in the solid-state imaging device is minimized. Parallel of normal inductance element and solid-state image sensor
In addition to the resonance circuit, connected in series with the inductance element
A capacitor is provided so that the resonance frequency of the resonance circuit
Match the frequency of the
The conductance L ₁ and the capacitance C _{1 of the} above capacitor
And the resonance frequency f _T of the resonance circuit is set to the value specified by the above equation.
As a result, the driving voltage characteristic maintains the flatness at this resonance frequency, and cutoff at a low frequency does not occur as in the switching resonance driving method described above.

The capacitance value C ₁ of the capacitor is fixed as
By larger than the capacitance value C _D body image pickup device, power consumption can be separated by either resonant frequency critical frequency that maximizes the stability of the driving circuit of the solid-state imaging device is increased.

The driving circuit of the solid-state imaging device according to the present invention has a low
Since the solid-state imaging device operates stably even in waves,
When used as an image display device, the above drive signal application
The voltage applied from the circuit to the solid-state imaging device is
The scanning period is the first frequency for transferring charges in the horizontal direction.
The charge transferred in the horizontal direction during the blanking period
In the vertical direction, the second frequency being lower than the first frequency.
It can be varied with frequency.

[0027]

As a first embodiment of a drive circuit of the solid-state imaging device of the present invention DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1, a circuit diagram of a drive circuit when using a charge couple device (CCD) 10 as a solid-state image pickup element having a capacitive load Is shown. Diagram of CCD unit 10
5 as an equivalent circuit similar to the CCD unit 10 in FIG.
The circuit is the same as that shown in FIG. 1, but is simplified in FIG.
It is illustrated as the electrode capacitance (capacitor) C _D. In this drive circuit , a drive pulse is applied to the CCD unit 10.
A terminal 11, a driver circuit 12 for driving pulses applied to the terminal 11 , a resistor 13, an inductance element 15, and a capacitor 16 are connected as shown in the figure. In addition,
As described with reference to FIG.
The same drive circuit as that on the left is connected. The drive circuit on the right
This is shown as a block with a simplified broken line. Right drive circuit
Is the same as that of the illustrated left driving circuit. Inductor
Element 15 and inductance 16 constitute a series circuit
One end of this series circuit is applied to the terminal 11.
The transfer drive pulse voltage V is applied to the driver circuit 12 and the resistor.
A node N1 applied to the CCD unit 10 via the anti-armor 13
Connected and the other end of the series circuit is grounded.
You. The drive circuit shown in FIG. 1 includes the transformer illustrated in FIG.
There is no resistor 26 and no capacitor 23.

An inductor is connected between the node N1 and the ground.
A series circuit composed of a capacitance element 15 and a capacitor 16 and C
The CD unit 10 is connected in parallel. Here, as a series circuit composed of the inductance element 15 and the capacitor 16 constitute a CCD and parallel resonant circuit in the CCD unit 10, the capacitance value C ₁ of the inductance value L ₁ and the capacitor 16 of the inductance element 15 is set Have been. The input signal terminal 11 input drive signal V is applied which is illustrated in FIG. 3 (A), the inductance element 15 and the capacitor
Common connection point between the series circuit of the sensor 16 and the CCD unit 10.
The terminal 14 connected to that node N1, FIG. 3 (B)
The illustrated drive voltage V actually applied to the CCD unit 10
1 occurs.

The analysis and operation of the circuit shown in FIG.
Give an explanation . As described above, for simplicity, the CCD in the CCD unit 10 loads a simple capacitance value C _D, such as illustrated pattern resistor 5 is neglected. The resistance value of the resistor 13 R1, L ₁ the inductance value of the inductance element 15, the capacitance value of the capacitor 16 C
_When it is set to ₁ , the current I flowing through this drive circuit is expressed by the following equation 3.
It is represented by

[0030]

(Equation 3)

The power P consumed by the CCD unit 10 is expressed by the following equation (4).

[0032]

(Equation 4)

From the above, the actual driving voltage V1 at the terminal 14 (node N1) is expressed by the following equation (5 ) .

[0034]

(Equation 5)

The absolute value of the voltage V1 is expressed by the following equation (6).

[0036]

(Equation 6)

[0037] Here, the CCD circuit of the CCD unit _10, Lee
The series circuit of the conductance element 15 and the capacitor 16
The resonance frequency f _T of the configured parallel resonance circuit is expressed by the following equation.

[0038]

(Equation 7)

FIGS. 2A and 2B are graphs showing the contents of the above equations 3 and 7. FIG. 2A is a graph showing characteristics of power consumption of the CCD unit 10 with the frequency f as a variable, and FIG. 2B is a graph showing the absolute value of the actual drive voltage V1 at the node N1 with the frequency f as a variable. FIG. As apparent from FIG. 2 (A), the it is understood that the power consumption P when driving frequency f is equal to the resonance frequency f _T is minimized zero (0). C CD unit 10 for HDTV
When used, such as ra, the drive frequency is about 10MHz
About. This drive frequency f matches the resonance frequency f _T
By doing so _, the power consumption in _the CCD unit 10 is minimized.
You. Therefore, the inductance of the inductance element 15
Value L ₁ and the capacitance value C ₁ of the capacitor 16 at the resonance frequency.
In order to make the number f _T equal to the drive frequency f,
Can be determined. If the inductance value L ₁ of the inductance element 15 and the capacitance value C ₁ of the capacitor 16 are selected in this manner, the signal applied to the terminal 11 is
The power consumption of the CCD unit 10 can be greatly reduced even at a driving frequency at which the signal is considerably high. Equation 7
In satisfactory condition, it is generated from Equation 6 to the terminal 14
It can be seen that the absolute value of the driving voltage V1 of the CCD unit 10 and the input driving voltage V become equal. As a result, the terminal 11 is marked.
The transfer clock pulse voltage illustrated in FIG.
The amplitude of V is not attenuated, and the voltage V1
The voltage is applied to the CCD unit 10 from N1 .

In FIGS. 2A and 2B, there is a critical frequency f _{C at} which the power consumption has a maximum value near the resonance frequency f _T. This critical frequency f _C is defined by the following equation.

[0041]

(Equation 8)

The power consumption of the CCD unit 10 increases.
From the viewpoint of the stability of the resonance type driving circuit , it is preferable that the resonance frequency f _T is apart from the critical frequency f _C. it is preferable to increase the capacitance value C _1. That is, the critical frequency f _C by increasing the capacitance value C ₁ of the capacitor 16 is because smaller than the resonance frequency f _T.

FIG. 3A shows the waveform of the transfer clock pulse voltage V applied to the input signal terminal 11, and FIG. 3B shows the waveform of the actual transfer clock voltage V1 at the node N1. The transfer clock pulse voltage V illustrated in FIG.
Is similar to that illustrated in FIG. Horizontal transfer
The operation will be described. Transfer clock pulse voltage V is high
At the level, the electromagnetic energy is in the inductance 15
Stored. At this time, the voltage V1 of the node N1 is
Defined by the time constant of the capacitance element 15 and the capacitor 16.
It falls to the ground level with a time delay. Then transfer
When the clock pulse voltage V becomes low level,
The electromagnetic energy stored in the case 15 is transferred to the CCD unit 10.
Flow into At this time, the voltage V1 of the node N1 is
Defined by the time constant of the capacitance element 15 and the capacitor 16.
High level with a time delay. Hereinafter, this operation is repeated
Will be done.

The low frequency pulse during the blanking period is applied.
The following describes the case in which The capacitor 16 is a high-frequency pulse
It has the characteristic of passing high-frequency pulses to
The DC component or the low frequency component has a characteristic of blocking. I
Therefore, during the blanking period t1 to t4, the low frequency
When a pulse is applied, the applied pulse voltage V becomes high level.
The capacitor 16 is the inductance element 15
Do not connect to ground. As a result, the period t2 to t3
The transfer clock pulse voltage V at high level is
Even if it is applied, the pulse voltage does not disappear. That
As a result, as shown in FIG.
The frequency of the transfer clock voltage between
However, the frequency characteristic is flat, and the time t shown in FIG.
When the signal between 2 and t3 is generated using the drive circuit according to FIG.
As shown as a waveform in FIG.
They are not turned off and disappear. As a result,
According to the present embodiment, modulation at a low frequency of a transfer clock for performing frame, interline, and transfer (FIT) of a plurality of streams, for example, two streams, is stably performed. The low-level potential LL of the voltage V1 at the terminal 14 illustrated in FIG. 3B is almost 0 V, and the high level HL.
Is approximately 5 V, and the voltage substantially equal to the input voltage V is maintained.

[0045] According to the driving circuit of this embodiment, thus, do not characteristic deterioration occurs in the frequency full range, it is possible to apply a signal having other frequency bands in addition to the transfer clock, various Can be performed.

The expansion of the pulse passage width in the drive circuit of the solid-state imaging device according to the present invention described above is particularly caused by the capacitor 16.
The frequency characteristic in the low frequency region is improved because the capacitor 16 is used. In the present embodiment, the truck illustrated in FIG.
No switching element such as transistor 26 is used.
Thus, the circuit configuration is simple. As described above, this embodiment
According to this embodiment, it is possible to modulate a transfer clock at a low frequency, which has been a problem in the past and has hindered practical use. The resonant circuit shown in FIG. 1 is essentially resistor 1
3 is a circuit configuration in which no current flows, that is, a voltage drive circuit, so that the problem of power consumption in the resistor 13 does not occur.

The resonant circuit shown in FIG. 1 is a very simple circuit configuration. Therefore, it is easy to incorporate this drive circuit into a solid-state imaging device. Although the above embodiment has exemplified the transfer in the horizontal blanking period, the present invention is also applicable to the vertical blanking period.

FIG. 4 shows a circuit configuration as a second embodiment of the drive circuit of the solid-state imaging device according to the present invention. This circuit configuration is
The CCD unit 10 is connected between the node N1 and the ground (earth).
Resonance relationship is inductor 15 and a capacitor 16
There instead to the circuit configuration are connected in the same manner as described above between the power supply voltage V _CC and node N1, it is obtained by connecting a resonant circuit Ru inductor 15 and the capacitor 16 Tona. Series of inductance element 15 and capacitor 16
One end of the circuit is similar to the circuit illustrated in FIG.
0 is connected to the connection point and the other end is grounded
Instead, the only difference is that it is connected to the supply voltage V _CC.
Therefore , the operation principle is the same as that of the first embodiment. That is, the ground in the circuit illustrated in FIG.
It can be considered as a 0V power supply, and the circuit illustrated in FIG.
Power supply voltage V _CC can be considered as the power supply of voltage V _CC.
Therefore, the circuit of FIG. 1 and the circuit of FIG.
A series circuit of an element 15 and a capacitor 16;
0 between the common connection point (node N1) and the power supply
It can be considered as a connected parallel resonance circuit.

In the above description, a charge-coupled device is exemplified as the transfer-type solid-state image pickup device. However, the present invention uses a transfer clock, and similarly applies to other solid-state image pickup devices whose load is represented by a capacitance component. Applicable.

[0050]

As described above, according to the present invention, the resonant circuit of the present invention is very simple circuit configuration, it can be easily incorporated into the conventional solid-state imaging device. Further, according to the drive circuit of the solid-state imaging device of the present invention, the power consumption of the solid-state image sensor at the drive frequency can be significantly reduced. Further, in the drive circuit of the solid-state imaging device according to the present invention, the transfer clock can be stably modulated even at a low frequency without a decrease in frequency characteristics at a low frequency. In addition, since signals other than the driving frequency band can be applied in the low frequency region without causing characteristic deterioration, various modulations can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of a drive circuit of a solid-state imaging device according to the present invention.

FIG. 2 is a graph showing power consumption characteristics and voltage characteristics obtained in the drive circuit of the solid-state imaging device shown in FIG.

3 is a diagram showing a waveform of an input drive signal applied in the circuit shown in FIG. 1 and a waveform of a CCD drive voltage generated based on the application of the drive signal.

FIG. 4 is a circuit configuration diagram of a second embodiment of the drive circuit of the solid-state imaging device according to the present invention.

FIG. 5 is a circuit configuration diagram of a drive circuit of a conventional solid-state imaging device.

6 is a drive signal waveform diagram in the drive circuit of the solid-state imaging device shown in FIG.

[Explanation of symbols]

11 ... input signal terminal, 12 ... inverting driver circuit, 13 ... resistor, 14 ... drive voltage terminal, 15 ... inductance element 16 ... capacitor, 10 ... CCD section.

Continuation of the front page (56) References JP-A-1-303757 (JP, A) JP-A-2-274076 (JP, A) JP-A-1-303758 (JP, A) JP-A-63-265467 (JP) , A) JP-A-63-117574 (JP, A) JP-A-4-337984 (JP, A) JP-A-4-320172 (JP, A) Yuji Ide et al. 1988 IEICE Spring National Convention D-136 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/30-5/335 H01L 21/339 H01L 29/762

Claims (3)

(57) [Claims] 1. A parallel arrangement with a solid-state imaging device having a capacitance component
The inductance element and the capacitor that constitute the resonance circuit
And the resonance frequency of the resonance circuit is equal to the frequency of the drive signal.
We, the inductance value L ₁ and above of the inductance element
The capacitance value C _{1 of the} capacitor is defined as the resonance of the resonance circuit.
F _T = the frequency f _T is defined by the following formula _{[(C 1 + C D) /} ((2π) 2 L 1 C 1 C D) ] ^1/2, however, C _D is the capacitance of the solid-state imaging device Value, solid-state imaging device. 2. The method according to claim 1, wherein the capacitance value C ₁ of the capacitor is fixed.
2. The device according to claim 1, wherein the capacitance is larger than a capacitance value C _{D of the} body imaging device.
The solid-state imaging device according to claim 1. 3. The solid-state imaging device is used as an image display device.
Is use, is applied to the solid-state imaging device from said driving signal applying circuit
Voltage to transfer charges in the horizontal direction during the horizontal scanning period.
At the first frequency, and the blanking period is horizontal.
The first frequency for vertically transferring the charges transferred in the vertical direction.
3. The method according to claim 1 , wherein the frequency changes at a second frequency lower than the number.
Mounted solid-state imaging device.