KR100206584B1 - Gate on voltage generation circuit for compensating data signal delay - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate on voltage generator for compensating for data signal delay in a thin film transistor liquid crystal display (TFT LCD).

A voltage generation circuit for generating a gate-on voltage that sequentially increases during one frame and a voltage generator circuit for generating a gate-on voltage that sequentially decreases for one frame are provided. As the scanning progresses when the data input order is the same and vice versa, the charging characteristic can be prevented from being degraded due to the signal delay in the data line.

Description

Gate-on voltage generator circuit to compensate for data signal delay

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate on voltage generator for compensating for data signal delay in a thin film transistor liquid crystal display (TFT LCD). It relates to a gate-on voltage generation circuit with improved charging characteristics.

In a thin film transistor liquid crystal display device, as a liquid crystal panel becomes larger and higher in resolution, data lines and gate lines in the panel become longer, and crossover points between the lines increase, thereby increasing parasitic capacitance. In particular, in high-aperture panel designs, overlap between pixels and lines increases, resulting in severe signal delay.

1 shows a signal delay in a liquid crystal panel. Referring to FIG. 1, a data signal and a gate signal are square waves at an input point, but the square waves are distorted due to line resistance and capacitance while being transmitted to a corresponding line on a panel. As shown in Fig. 1, the gate signal and the data signal opposite the panel have a waveform delayed due to distortion, and this signal delay worsens the charging characteristics at each pixel in the liquid crystal panel. More specifically, the higher the signal delay, the shorter the high level period in the data signal and the gate signal, thereby charging each pixel less. Therefore, not only the contrast ratio of the liquid crystal display device is lowered, but also the display uniformity is poor, especially when the amplitude of the data signal is large, such as high voltage driving.

In order to solve the problem of deterioration in image quality due to such a signal delay, a driving method for applying a signal from both a data line and a gate line in a liquid crystal panel is mainly used. However, this method reduces the product's price competitiveness because it doubles the number of driver ICs. In particular, since a source driver IC is more expensive than a gate driver IC, the cost of the product is greatly affected.

The graph of FIG. 2 shows the current-voltage characteristics of a typical thin film transistor.

2, the horizontal axis represents the gate voltage and the vertical axis represents the drain current. As is known, in the thin film transistor, as the gate voltage increases until the saturation region is reached, the drain current increases in proportion to the gate voltage.

The inventors of the present application have found that the gate-on voltage, which is gradually increasing, can be used for driving the liquid crystal panel in view of these characteristics of the thin film transistor.

3A shows a waveform of a conventional gate signal, and FIG. 3B shows a waveform of a gate signal according to the present invention.

Conventionally, the liquid crystal panel is driven by a gate signal having a constant gate on voltage regardless of the gate line of the liquid crystal panel. However, in the present invention, the liquid crystal panel is driven using a gradually increasing gate on voltage. In this way, even if the gate signal is delayed due to the high resolution of the liquid crystal panel and the increase in the gate line length, sufficient drain current can flow in each thin film transistor in the liquid crystal panel due to the gradually increasing gate-on voltage. For this reason, the charging characteristic of each pixel in a liquid crystal panel can be improved.

SUMMARY OF THE INVENTION The present invention is derived from the above technical background, and has a first object to provide a voltage generating circuit for generating a gate-on voltage which is sequentially increased for application when the scanning order and data input order coincide.

A second object of the present invention is to provide a voltage generating circuit for generating a gate-on voltage which is sequentially reduced for application when the scanning order and the data input order are reversed.

1 is a configuration diagram illustrating a signal delay in a liquid crystal panel.

2 is a graph showing current-voltage characteristics of a general thin film transistor.

3A and 3B are waveforms comparing a conventional gate signal with a gate signal according to the present invention.

4A to 4C are configuration diagrams showing a scanning sequence to which the first embodiment of the present invention is applied, and waveforms of a gate on voltage generation circuit and a gate on voltage;

5A to 5C are configuration diagrams showing a scanning sequence to which the second embodiment of the present invention is applied, and waveforms of a gate on voltage generation circuit and a gate on voltage;

In order to achieve the first object described above, the gate-on voltage generation circuit according to the present invention,

A first RC circuit comprising a first resistor and a first capacitor connected in series, wherein a first reference voltage is applied to the first resistor, and the first capacitor is grounded;

A second RC circuit having a second resistor and a second capacitor connected in series, wherein the second resistor is connected to the first resistor of the first RC circuit and the second capacitor is supplied with a second reference voltage;

A first switching element for turning on or off both ends of the first capacitor of the first RC circuit in response to a discharge signal having a predetermined high level section every one frame period;

A second switching element for turning on or off both ends of the second capacitor of the second RC circuit according to the potential of the first resistor of the first RC circuit and the contact point of the first capacitor; And

And a buffer configured to amplify and output the potential of the second resistor of the second RC circuit and the contact point of the second capacitor.

According to the present invention, the first reference voltage is the maximum value of the gate on level, and the second reference voltage is the minimum value of the gate on level. When both ends of the first capacitor are turned off by the first switching element and the first capacitor is charged, the potential of the contact between the first resistor and the first capacitor is increased, thereby causing the second switching element to turn both ends of the second capacitor. Turn it off. The second capacitor also starts charging by the turn-off, and the potential of the contact between the second resistor and the second capacitor rises from the second reference voltage to the first reference voltage by charging the second capacitor. In the buffer, a voltage rising from the second reference voltage to the first reference voltage in one frame period is obtained, and the gate-on voltage may be used to improve charging characteristics in the liquid crystal display device having the same data input order and scanning order. have.

In order to achieve the above second object, the gate-on voltage generation circuit according to the present invention,

A first RC circuit comprising a first resistor and a first capacitor connected in series, wherein a first reference voltage is applied to the first resistor, and the first capacitor is grounded;

A second RC circuit comprising a second capacitor connected in series and a second resistor, wherein the second capacitor is connected to a first resistor of the first RC circuit and a second reference voltage is applied to the second resistor;

A first switching element for turning on or off both ends of the first capacitor of the first RC circuit in response to a discharge signal having a predetermined high level section every one frame period;

A second switching element for turning on or off both ends of the second capacitor of the second RC circuit according to the potential of the first resistor of the first RC circuit and the contact point of the first capacitor; And

And a buffer configured to amplify and output the potentials of the contacts of the second capacitor and the second resistor of the second RC circuit by unit gain.

According to the present invention, the first reference voltage is the maximum value of the gate on level, and the second reference voltage is the minimum value of the gate on level. When both ends of the first capacitor are turned off by the first switching element and the first capacitor is charged, the potential of the contact between the first resistor and the first capacitor is increased, thereby causing the second switching element to turn both ends of the second capacitor. Turn it off. The second capacitor also starts charging by the turn-off, and the potential of the contact point of the second capacitor and the second resistor decreases from the first reference voltage to the second reference voltage by charging the second capacitor. In the buffer, a voltage rising from the first reference voltage to the second reference voltage in one frame period is obtained, and the gate-on voltage may be used to improve charging characteristics in the liquid crystal display device in which the data input order and the scanning order are reversed. have.

The objects, features and advantages of this invention described above will become more apparent from the following detailed description of the embodiments with reference to the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a first embodiment of the present invention will be described with reference to the attached FIGS. 4A to 4C.

FIG. 4A is a block diagram showing a scanning sequence to which the first embodiment of the present invention is applied, FIG. 4B is a gate-on voltage generation circuit according to the first embodiment of the present invention, and FIG. 4C is generated in the circuit of FIG. 4B. This is the waveform of the gate-on voltage.

Referring to FIG. 4A, the input order of data signals in the liquid crystal panel is the same as the scanning order. Here, scanning means driving the gate lines sequentially by the gate signal, and is realized by applying the gate-on voltage to each gate line in turn.

When the input order and the scanning order of the data signal match, the delay of the data signal gradually increases as each gate line is scanned, so that a gradually increasing gate-on voltage is required.

Next, a voltage generation circuit for generating a gate on voltage that gradually increases will be described with reference to FIG. 4B.

Referring to FIG. 4B, the resistor R1 and the capacitor C1 connected in series constitute an RC circuit, and the resistor R2 and the capacitor C2 also constitute an RC circuit. The two resistors R1 and R2 are connected to each other, and a first reference voltage Va is applied to the contacts thereof. The capacitor C1 is grounded, and a second reference voltage Vb is applied to the capacitor C2. An operational amplifier 4 operating as a unit-gain buffer is connected to the contact of the resistor R2 and the capacitor C2, and a gate-on voltage is generated at an output terminal of the operational amplifier 4. The contact of the resistor R2 and the capacitor C2 is connected to the non-inverting input terminal of the operational amplifier 4, the inverting input terminal and the output terminal of the operational amplifier 4 are connected to each other. Both ends of the capacitor C1 are connected to the drain and the source of the transistor M1, and both ends of the capacitor C2 are connected to the drain and the source of the transistor M2. The discharge signal Vdis is applied to the gate of the transistor M1, and the gate of the transistor M2 is connected to a contact of the resistor R1 and the capacitor C1. Transistor M1 is an NMOS transistor NMOS, and transistor M2 is a PMOS transistor PMOS. The first reference voltage Va is a maximum value of the gate-on voltage, and the second reference voltage Vb is a minimum value of the gate-on voltage.

The discharge signal Vdis has a high level pulse at the start of every frame, as shown in FIG. 4C.

When the discharge signal Vdis is at the high level, the transistor M1 is turned on, and the transistor M2 is also turned on because the drain potential becomes the same as the ground by turning on the transistor M1. Under these bias conditions, a current path consisting of the first reference voltage Va, resistor R2, transistor M1, and ground is formed, and the first reference voltage Va, resistor R2, M2, A current path consisting of the second reference voltage Vb is formed. Accordingly, the voltages at both ends of the two capacitors C1 and C2 are rapidly discharged, and the second reference voltage Vb is input to the non-inverting input terminal of the operational amplifier 4, and the voltage Vb is gated on without a gain change. It is output as a voltage. As shown in FIG. 4C, when the discharge signal Vdis is at a high level, the gate-on voltage is the second reference voltage Vb.

When the discharge signal Vdis falls to a low level as shown in FIG. 4C, the transistor M1 is turned off and the capacitor C1 is charged by the first reference voltage Va. The charge on the capacitor C1 causes the gate voltage of the transistor M2 to increase, which causes the transistor M2 to turn off. Charging of the capacitor C2 by the first reference voltage Va is started by turning off the transistor M2, and the potential of the contact between the resistor R2 and the capacitor C2 is the second reference voltage Vb. Gradually increases from to the first reference voltage Va. At this time, the time constant is determined by the product of the device value of the resistor R2 and the capacitor C2. Therefore, if the device value is properly adjusted, the charge of the capacitor C2 is maintained for about one frame. The potential of may be increased sequentially during one frame. The potential of the contact is output as a gate-on voltage via the operational amplifier 4. As shown in FIG. 4C, it can be seen that the gate-on voltage increases from the second reference voltage Vb to the first reference voltage Va during the low level period of the discharge signal Vdis. In FIG. 4C, T1 is an effective display period, and the gate-on voltage during the T1 period is provided to a source driver IC of the liquid crystal display, and the source driver IC selects the gate-on voltage every one horizontal period. To the liquid crystal panel. Since one horizontal period is usually much smaller than one frame period, the gate-on voltage may gradually increase as scanning progresses.

Next, a second embodiment of the present invention will be described with reference to the accompanying drawings.

Fig. 5A is a block diagram showing a scanning sequence to which the second embodiment of the present invention is applied, Fig. 5B is a gate-on voltage generation circuit according to the second embodiment of the present invention, and Fig. 5C is generated in the circuit of Fig. 5B. This is the waveform of the gate-on voltage.

Referring to FIG. 5A, an input order of data signals in a liquid crystal panel is opposite to a scanning order. When the input order of the data signal and the scanning order are reversed, the delay of the data signal gradually decreases as each gate line is scanned, so that a gradually decreasing gate-on voltage is required.

Next, a voltage generation circuit for generating a gate on voltage that gradually decreases will be described with reference to FIG. 5B.

Referring to FIG. 5B, the series-connected resistor R3 and the capacitor C3 form an RC circuit, and the series-connected capacitor C4 and the resistor R4 also form an RC circuit. The resistor R3 and the capacitor C4 are connected to each other, and a first reference voltage Va is applied to the contact point. The capacitor C3 is grounded, and a second reference voltage Vb is applied to the resistor R4. An operational amplifier 5 that operates as a unit-gain buffer is connected to the contact point of the capacitor C4 and the resistor R4, and a gate-on voltage is generated at an output terminal of the operational amplifier 5. The contact point of the capacitor C4 and the resistor R4 is connected to the non-inverting input terminal of the operational amplifier 5, and the inverting input terminal and the output terminal of the operational amplifier 5 are connected to each other. Both ends of the capacitor C3 are connected to the drain and the source of the transistor M3, and both ends of the capacitor C4 are connected to the drain and the source of the transistor M4. The discharge signal Vdis is applied to the gate of the transistor M3, and the gate of the transistor M4 is connected to a contact of the resistor R3 and the capacitor C3.

Transistor M3 is an NMOS transistor NMOS, and transistor M4 is a PMOS transistor PMOS. The first reference voltage Va is a maximum value of the gate-on voltage, and the second reference voltage Vb is a minimum value of the gate-on voltage.

The discharge signal Vdis has a high level pulse at the start of every frame, as shown in FIG. 5C.

When the discharge signal Vdis is at the high level, the transistor M3 is turned on, and the transistor M4 is also turned on because the drain potential becomes the same as the ground by turning on the transistor M3. Under this bias condition, a current path consisting of the first reference voltage Va, resistor R3, transistor M3, and ground is formed, and the first reference voltage Va, transistor M4, resistor R4, A current path consisting of the second reference voltage Vb is formed. Accordingly, the voltages at both ends of the two capacitors C3 and C4 are rapidly discharged, and the first reference voltage Vb is input to the non-inverting input terminal of the operational amplifier 5, and the voltage Vb is gated on without a gain change. It is output as a voltage. As shown in FIG. 5C, when the discharge signal Vdis is at the high level, the gate-on voltage is the first reference voltage Va.

When the discharge signal Vdis falls to a low level as shown in FIG. 5C, the transistor M3 is turned off and the capacitor C3 is charged by the first reference voltage Va. The charging of the capacitor C3 causes the gate voltage of the transistor M4 to increase, thereby turning off the transistor M4. Charging of the capacitor C4 by the first reference voltage Va is started by turning off the transistor M4, and charging of the capacitor C4 causes the contact of the contact of the capacitor C4 and the resistor R4. The potential gradually falls. The potential of the contact point of the capacitor C4 and the resistor R4 drops to the second reference voltage Vb. At this time, the time constant is determined by the product of the device value of the resistor R4 and the capacitor C4. Therefore, if the device value is properly adjusted, the contact of the contact point is maintained for about one frame. The potential of may be increased sequentially during one frame. The potential of the contact is output as a gate-on voltage via the operational amplifier 5. As shown in FIG. 5C, it can be seen that the gate-on voltage increases from the first reference voltage Va to the first reference voltage Va during the low level period of the discharge signal Vdis. In FIG. 5C, T1 is an effective display period, and the gate-on voltage during the T1 period is provided to a source driver IC of the liquid crystal display, and the source driving IC selects the gate-on voltage every one horizontal period. To the liquid crystal panel. Since one horizontal period is usually much smaller than one frame period, the gate-on voltage may gradually decrease as scanning progresses.

As described above, the present invention provides a voltage generation circuit for generating a gate on voltage that sequentially increases during one frame and a voltage generator circuit for generating a gate on voltage that sequentially decreases during one frame. Each of the voltage generation circuits can prevent the charging characteristic from dropping due to signal delay in the data line as the scanning proceeds when the scanning order and the data input order in the liquid crystal panel are the same and vice versa.

Although this invention has been described with reference to the most practical and preferred embodiments, the invention is not limited to the embodiments disclosed above, but also includes various modifications and equivalents which fall within the scope of the following claims.

Claims (6)

A first RC circuit comprising a first resistor and a first capacitor connected in series, wherein a first reference voltage is applied to the first resistor, and the first capacitor is grounded; A second RC circuit having a second resistor and a second capacitor connected in series, wherein the second resistor is connected to the first resistor of the first RC circuit and the second capacitor is supplied with a second reference voltage; A first switching element for turning on or off both ends of the first capacitor of the first RC circuit in response to a discharge signal having a predetermined high level section every one frame period; A second switching element for turning on or off both ends of the second capacitor of the second RC circuit according to the potential of the first resistor of the first RC circuit and the contact point of the first capacitor; And And a buffer for amplifying and outputting the potential of the second resistor of the second RC circuit and the contact point of the second capacitor by unit gain. Gate-on voltage generator circuit for liquid crystal display device. The NMOS transistor of claim 1, wherein the first switching device is an NMOS transistor having a discharge signal applied to a gate, and a drain and a source connected to both ends of the first capacitor. The second switching element is a PMOS transistor whose gate is connected to the contact of the first resistor and the first capacitor, the drain and the source are connected to both ends of the second capacitor, Gate-on voltage generator circuit for liquid crystal display device. The method of claim 1, wherein the time constant determined by the element value of the second resistor and the second capacitor is determined so that the charging of the second capacitor is continued for one frame. Gate-on voltage generator circuit for liquid crystal display device. A first RC circuit comprising a first resistor and a first capacitor connected in series, wherein a first reference voltage is applied to the first resistor, and the first capacitor is grounded; A second RC circuit comprising a second capacitor connected in series and a second resistor, wherein the second capacitor is connected to a first resistor of the first RC circuit and a second reference voltage is applied to the second resistor; A first switching element for turning on or off both ends of the first capacitor of the first RC circuit in response to a discharge signal having a predetermined high level section every one frame period; A second switching element for turning on or off both ends of the second capacitor of the second RC circuit according to the potential of the first resistor of the first RC circuit and the contact point of the first capacitor; And And a buffer configured to amplify and output the potentials of the contacts of the second capacitor and the second resistor of the second RC circuit by unit gain. Gate-on voltage generator circuit for liquid crystal display device. The NMOS transistor of claim 4, wherein the first switching element is an NMOS transistor having a discharge signal applied to a gate, and a drain and a source connected to both ends of the first capacitor. The second switching element is a PMOS transistor whose gate is connected to the contact of the first resistor and the first capacitor, the drain and the source are connected to both ends of the second capacitor, Gate-on voltage generator circuit for liquid crystal display device. The method of claim 4, wherein the time constant determined as the product of the second resistance and the device value of the second capacitor is determined such that the charging of the second capacitor is continued for one frame. Gate-on voltage generator circuit for liquid crystal display device.

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