JP3012444B2 - Process dispatch method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a process dispatching method, and more particularly to a process dispatching method in a multiprocessor system in which each of a plurality of CPUs has a cache memory.

[0002]

[Prior art]

[Definition of terms] Before describing the related art, terms used in the present specification are defined.

A process control block (PCB) is information necessary for executing a process, and is stored in a main storage device. The information stored in the PCB includes the priority of the process. The detailed structure of the PCB will be described later.

[0004] The running state is one state of a process, that is, a state in which the process is being executed on a processor.

[0005] The executable state is one state of the process, and is a state in which the process can be executed immediately. The ready process waits in the execution queue for a processor to be free.

[0006] The execution waiting state is a state of the process, in which the process is waiting for the occurrence of some event.

[0007] Re-dispatching means that a process in a running state is temporarily placed in an execution waiting state and then dispatched to any processor again.

[0008] The process swap is a process in which a process being executed by a processor is put into an executable state or an execution waiting state, and another process is dispatched to this processor. [Prior Art] Next, characteristics of a multiprocessor system in which a cache memory is mounted on each processor will be described. In a multiprocessor system, one cache memory is provided for each processor. This is because if a cache memory is provided near the processor, high-speed access is possible. However, such a cache memory causes the following problems.

The above problem will be described with reference to a virtual multiprocessor system and its processing. This virtual multiprocessor system includes processors X to
Z. The processors X to Z include a cache memory x
To z. In the first step of the process, process A is being executed by processor X. Second
In the step, the process A is put into an execution waiting state. In the third step, in process X, process A
Other processes are executed. In the fourth step,
Process A is re-dispatched to processor Z.
At this time, the data a used in the process of the process A remains in the cache memory x of the processor X.

[0010] The above process has the following two problems.

First, in the fourth step, since the re-dispatch destination of the process A is the processor Z, the data a in the cache memory x is not used. The processor Z executing the process A in the fourth step needs to read necessary data from the main memory. For this reason, the processing of the process A becomes slow. Hereinafter, this problem is referred to as a decrease in the hit rate.

Second, cache cancellation may occur. In the fourth step, when the processor Z reads the same data as the data a from the main memory,
The same data exists in the cache memories x and z at the same time. The data a in the cache memory x is
Canceled when the processor Z changes the contents of the data a in the cache memory z. This is to avoid inconsistency between data. When cache cancellation occurs, the processing capacity of the system decreases.

The above two problems have been avoided if the redispatch destination of the processor A is the processor X, which is the processor that was being executed immediately before. Thus, in a multiprocessor system in which each processor has a cache memory, the method of determining a dispatch destination in redispatching affects the performance of the system.

Next, the prior art will be described. An example of a dispatch method for dispatching a process based on the characteristics of a multiprocessor system as described above is described in U.S. Pat.
S. PAT. No. No. 5,193,172. Referring to the same publication, column 2, lines 52 to 53, it is an object of the prior art to reduce the occurrence of cache cancellation due to dispatch.

In this prior art, real pages in main memory are divided into a plurality of groups. Each group is assigned one processor at a time. Processors assigned to one group preferentially use real pages belonging to this group. Each processor is assigned a task that is preferentially executed by this processor.
Each task is assigned a real page used during the processing of this task.

Referring to column 8, lines 3 to 13 of the publication, redispatching in the prior art is as follows.
It is performed in the following procedure. The number of real pages assigned to the task to be dispatched is measured for each group. As a result of the measurement, the group to which the most real pages are assigned is determined. Then, this task is dispatched to the processor having the priority use right for this group.

According to the above-described dispatch method, when there is no change in the actual page assigned to each task,
This task is re-dispatched to a previously running processor. Therefore, the probability of cache cancellation decreases.

[0018]

However, this prior art has the following problems.

The problem is that many procedures need to be performed to manage the groups described above. In this prior art, the above-mentioned group must be changed during processing. This is to allocate an appropriate number of memory pages to each processor. However, referring to the publication, column 6, line 20 to column 7, line 35, a complicated and large number of procedures must be executed to change the group. In addition, this procedure needs to be performed repeatedly.

[0020]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a process dispatching method which can improve the hit rate of a cache memory and reduce the rate of occurrence of cache cancellation with fewer procedures. In particular,
A process dispatching method is provided using the following three strategies.

(First Strategy) The processor executing the process with the lowest priority is the dispatch destination.

(Second Strategy) When there are a plurality of processes with the lowest priority, and a processor executing these processes includes a processor in which a process to be dispatched is executed last. , This processor is the dispatch destination.

(Third Strategy) If the dispatch destination is not determined by the second strategy, and the processor executing the lowest priority process includes the processor executing the dispatch process, the third strategy The processor is the dispatch destination.

[0024] In the preferred implementation of the present invention, the dispatch method using the strategy described above, the a number of processors the a priority of the first process the first process has been executed immediately before A first step of reading from the process control block of the first process, and a second step of selecting all of the running processes having the lowest priority.
And the priority of the process selected in the second step is compared with the priority of the first process, and the priority of the process selected in the second step is determined by the first process. A third step of interrupting the dispatch process when the priority is higher than the priority order of the first process, and when only one process is selected in the second step, the processor executing the process is provided with the first process. And when there are a plurality of processes selected in the second step, the first process is further included in a processor executing the process selected in the second step. If there is a match for the number of the previously executed processor,
A fifth step of dispatching said first process to said processor, said fourth step and said fifth step.
In the step, the first process is executed by any processor.
Was not dispatched, and the second
Dispatch processing among the processors selected in the step
This processor when there is a processor
A sixth dispatching said first process to a processor;
And the fourth, fifth and sixth steps
The first process is dispatched to any processor
If not, the first process is terminated by the second process.
The processor running the process selected in step
A seventh step of dispatching to any gap, and either
The second process running on the processor of
When the executable or waiting state is entered,
Stored in the process control block of the second process.
Of the processor in which the second process was executed immediately before
Number of the processor on which the second process is running
A first PCB update processing step of changing to a number,
When a new process is created, the third process
The third process stored in the process control block of the process.
The number of the processor on which the process was
And a second PCB update processing step of setting a suitable value .

[0025]

【Example】

[Configuration] First, the configuration of the present embodiment will be described. Referring to FIG. 1, the multiprocessor system of the present embodiment includes a CP
U # 0 to CPU # 3 are included. C
PU # 0-CPU # 3 are cache memories 6-9,
Include each. The CPUs # 0 to # 3 access the common main storage device 5.

The main storage device 5 has a CPU execution state management table 3
00, a process control block area 200 and a queue header 20.

In the process control block area 200, process control blocks (PCBs) 14 to 15 are stored.

Executable process names 31 to 33 are linked to the queue header 20 by pointers. The process names 31 to 33 linked by the pointer form an execution queue. In the following, for convenience, the process name 31
To 33 are referred to as processes 31 to 33, respectively. The processes 31 to 33 are arranged in accordance with the priority order described later. The process 31, which is the head of the execution queue 30,
This is the highest priority process in the queue.

Referring to FIG. 2, the PCB 14 includes the process specific information 214, the priority order 210, and the immediately preceding execution CP.
U number 212 is included. The process specific information 214 stores information included in a normal PCB, excluding the process priority. For example, the execution condition of the process is included in the process specific information 214. Priority 2
Reference numeral 10 denotes a priority order for determining the execution order of the process.
The immediately preceding CPU number 212 is the number of the CPU that executed the process immediately before. When the process is in the execution waiting state or the executable state, the immediately preceding execution CPU number 212 matches the number of the CPU in which the process was executed last. The procedure for updating the immediately preceding execution CPU number 212 will be described later.

Referring to FIG. 3, the CPU execution state management table 300 contains process names of processes being executed by CPUs # 0 to # 3 and their priorities 301 to 30.
4 is stored. Next, the process dispatch method of the present embodiment will be described. In the dispatch method of this embodiment, two types of dispatch processing and two types of PCB update processing are executed. In these two types of PCB update processing, the immediately preceding CPU number 212 is updated. [First Dispatch Process] Referring to FIG. 4, the first dispatch process 61 is executed when the execution of a process is completed in any of the CPUs # 0 to # 3.
In the first dispatching process, the CPU that has completed the execution of the process is given the process 3
1 is dispatched. The first dispatch process is
Since it is the same as the dispatch processing that is usually performed, detailed description is omitted. [First PCB Update Process] Referring to FIG. 5 and FIG. 6, the first PCB update process 62
This is executed when an event wait occurs in the running process in any of # 3. An event is the completion of input / output, synchronization with another process, or the like.

Referring to FIG. 6, the first PCB update process 62 includes steps 401 and 402. In FIG. 6, the process in which the event wait has occurred is called process A. In step 401, the number of the CPU executing the process A is
The PU number 212 is set in the PCB of the process A.

In step 402, process A is enqueued in wait queue 40. Referring to FIG. 5, processes 41 to 43 waiting for execution are arranged in the wait queue 40. By being enqueued in the wait queue 40, the process A enters an execution waiting state. Upon completion of step 402, the first PCB update process ends.

After the first PCB update process is completed, in step 403, the event that the process A has been waiting for is completed. As a result, the process A is enqueued in the execution queue 30. As mentioned above, the processes in the execution queue 30 are ordered according to priority. Process A is also inserted at a location corresponding to the priority. By being enqueued in the execution queue 30, the process A becomes executable. [Second PCB Update Process] Referring to FIGS. 5 and 7, the second PCB update process 63 is executed when a new process is created. Referring to FIG. 7, the second PCB update process 63 includes Step 405.

In step 404, a new process is created. This process is called process A for convenience.

In step 405, a random number R is set in the CPU number 212 immediately before the process A. Random number R
Indicates one of the numbers of CPUs included in the system. In the system of the present embodiment, R is 0, 1, 2, or 3.
Is one of

At step 406, process A is enqueued into execution queue 30. As in step 403, process A is inserted at a location corresponding to its priority. [Second Dispatch Process] Referring to FIGS. 5 and 8, the second dispatch process 64 is executed when one of the processes is enqueued in the execution queue 30.

Referring to FIG. 8, the second dispatch processing 64 includes steps 407 to 409. Here, the process enqueued in the execution queue 30 is called a process A.

In step 407, it is determined whether or not the process A has been enqueued at the head of the execution queue 30. When the process A is enqueued at a place other than the head of the execution queue 30, step 409 is executed. In step 409, CPU # 0 to CPU #
In step 3, the process being executed is continuously executed.

On the other hand, if the process A is enqueued at the head of the execution queue 30, step 408 is executed. The fact that the process A is enqueued at the head of the execution queue 30 indicates that the priority of the process A is higher than the priority of other processes in the execution queue 30. Therefore, the priority of process A is CP
There is a possibility that the priority is higher than the priority of the process being executed by U # 0 to CPU # 3. Therefore, CPU # 0-CPU #
When there is a process having a lower priority than the process A among the processes running in the process 3, it is necessary to dispatch the process A to the CPU preferentially. Step 408
Performs this processing.

In step 408, the dispatch destination of the process A is determined based on the above-described first to third strategies. The dispatch of the process A based on the first to third strategies is realized in principle by the following five steps.

(Step 1) A step of selecting all of the running processes having the lowest priority.

(Step 2) The priority of the process selected in step 1 is compared with the priority of process A,
A step of stopping dispatch processing when the priority of the process selected in step 1 is higher than the priority of process A.

(Step 3) The step of dispatching the process A to the processor executing the process when only one process is selected in the step 1.

(Step 4) When there are a plurality of processes selected in step 1, the process A is further included in the processor executing the process selected in step 1.
A step of dispatching the process A to the processor when there is a CPU that matches the immediately preceding execution CPU number 212;

(Step 5) When the process A is not dispatched to any of the processors in the steps 3 and 4, there is a processor executing the dispatch process among the processors selected in the step 1. Sometimes dispatching process A to this processor.

Of the above steps, steps 3 to 5 correspond to the first to third strategies.

However, in step 408 of the present embodiment,
Then, the processes corresponding to steps 3 to 5 are executed simultaneously. [Step 408] In the following description, the following notation is used. PA indicates process A. #I is the i-th C
This shows a process being executed by the CPU #i that is a PU. Cn
t indicates the number of the processor executing step 408. PCB (X) indicates the PCB of process X.
PRI (X) indicates the priority of the process X. LCP
U # (X) is the CPU number 212 immediately before the process X
Is shown.

Next, the variables used in step 408 will be described. i, j, and k are variables having no special meaning. minpn is the number of the CPU executing the process with the lowest priority. minpn is determined in consideration of the above-described first to third strategies. M is the maximum value of the processor number. In the case of the present embodiment, it is 3.

Referring to FIG. 9 and FIG. 10, step 408 includes steps 502 to 528. Step 502 can be roughly divided into two parts. The first part consists of steps 502 to 526
It consists of. In the first part, minpn is defined. The second part consists of steps 526 and 52
8. In the second part, dispatch is performed.

In step 502, variables i, j, k
And 0, 1, and 2 are respectively substituted for.

In step 504, the PRI (PA)
And LCPU # (PA) are read from PCB (PA). According to the above notation, PRI (PA), LCP
U # (PA) and PCB (PA) indicate the priority of the process A, the CPU number immediately before the process A, and the PCB of the process A, respectively.

In step 506, the PRI (#i)
And PRI (#j) are stored in the CPU execution state management table 300.
Is read from. According to the above notation, PRI (#
i) and PRI (#j) indicate the priority of the process running on the CPU #i and the priority of the process running on the CPU #j, respectively.

Step 508 is a step for realizing the first strategy described above. In step 508, the CP
The priority of the process being executed by U # i is compared with the priority of the process being executed by CPU # j. Using the notation described above, the magnitude relationship between PRI (#i) and PRI (#j) is compared. PRI (#i) <PRI (#j)
, Ie, when the priority of the process being executed by the CPU #i is lower than the priority of the process being executed by the CPU #j, Step 518 is executed. PRI
When (#i) = PRI (#j), step 510 is executed. When PRI (#i)> PRI (#j), step 520 is executed.

Step 510 is a step for realizing the above-mentioned second strategy. In step 510, the number L of the CPU on which the process A was last executed
It is determined whether or not CPU # (PA) matches i. When LCPU # (PA) = i, that is, when the CPU that executed process A last is CPU # i, step 518 is executed. If LCPU # (PA) and i are not equal, step 512 is executed.

Step 512 is a step for realizing the above-mentioned second strategy. In step 512, the number L of the CPU on which the process A was last executed
It is determined whether or not CPU # (PA) matches j. When LCPU # (PA) = i, that is, when the CPU that executed process A last is CPU # j, step 520 is executed. When LCPU # (PA) and j are not equal, step 514 is executed.

Step 514 is a step for realizing the third strategy described above. At step 514, i and Cnt are compared. That is, CPU #i
Is determined to be the CPU itself executing this process. When i = Cnt, that is, when CPU # i is the CPU executing this process, step 518 is executed. If i and Cnt are not equal, step 520 is executed.

Step 518 is performed when PRI (#i) <PRI (#j) in step 508.
When LCPU # (PA) = i in 10, or
This is executed when i = Cnt in step 514. In step 518, i is substituted for minpn and k is substituted for j. When step 518 ends, step 522 is executed.

Step 520 is performed when PRI (#i)> PRI (#j) in step 508.
10 when LCPU # (PA) = j, or
This is executed when i and Cnt are not equal in step 514. In step 520, minpn is set to j.
, And k for i. When step 522 ends, step 522 is executed.

In step 522, k is incremented.

In step 524, it is compared whether k = M + 1. When k and M + 1 are not equal,
Steps after step 506 are executed again. K =
If M + 1, step 526 is executed. At the end of step 524, the CPU number of the dispatch destination of the process A, which is determined based on the above-described first to third strategies, is substituted for the variable minpn.

At step 526, the PRI (CPU
#Minpn) and PRI (PA) are determined. That is, the priority of the process being executed by the CPU #minpn is compared with the priority of the process A. P
If RI (CPU # minpn) is greater than or equal to PRI (PA), step 408 ends. This is a case where the priority of the process A is lower than the lowest priority of the process currently being executed by each processor. Therefore, process A is not dispatched. PRI
When (CPU # minpn) <PRI (PA), step 528 is executed.

At step 528, the process A
Dispatched to PU # minpn. Step 52
Upon completion of step 8, step 408 is completed.

Upon completion of step 408, the second dispatch processing is completed. The first dispatch process, the second dispatch process, the first PCB update process, and the second PCB update process described above are each executed independently. [Effect] As described above, in the present invention, the dispatch destination in the second dispatch processing is determined according to the above-described first to third strategies.

Since the second strategy is taken into account in determining the dispatch destination, with very high probability, the process is dispatched again to the CPU that was executing immediately before.
Therefore, the cache hit rate is improved. Also, the rate of occurrence of cache cancellation is reduced.

Since the third strategy is considered in determining the dispatch destination, the execution speed of the process is improved.
This is because the processor executing the dispatch process has already accessed the PCB (PA) of the process A, and thus can start the process of the process A relatively earlier than other processors.

When a new process is created, the immediately preceding CPU number 212 is randomly determined by the second PCB update process. Therefore, in the second dispatch process, the dispatch destination of the newly created process does not concentrate on a specific processor.

As described above, according to the present invention, an improvement in the cache hit rate and a reduction in the cache cancel rate are achieved at the same time. Therefore, the processing efficiency of a multiprocessor system in which each processor has a cache memory can be improved. Furthermore, according to the present invention, there is no need to divide the memory into groups nor to manage these groups. [Other Embodiments] The present invention can be implemented in various other embodiments without departing from the spirit or main features thereof.

For example, in the above embodiment, the number of CPUs is four, but the number of CPUs may be any number.
However, it is necessary to change the value of the variable M according to the change in the number of CPUs.

The second PCB change processing need not be performed. In this case, it is necessary to perform a conventional dispatch process on the newly generated process instead of the second dispatch process.

As described above, this embodiment is merely an example in every aspect and should not be construed as limiting. The scope of the present invention is defined by the appended claims, and is not limited by the specification. further,
All modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.

[0071]

As described above, according to the present invention,
The improvement of the cache hit rate and the reduction of the cache cancellation rate are achieved at the same time. Therefore, the processing efficiency of a multiprocessor system in which each processor has a cache memory can be improved. Furthermore, according to the present invention, there is no need to divide the memory into groups nor to manage these groups.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a view showing data stored in a PCB 14;

FIG. 3 is a diagram showing data stored in a CPU execution state management table 300.

FIG. 4 is a diagram showing an operation of a first dispatch processing 61.

FIG. 5 is a diagram showing operations of a first PCB update process 62, a second PCB update process 63, and a second dispatch process 64.

FIG. 6 is a flowchart showing an operation of a first PCB update process.

FIG. 7 is a flowchart showing an operation of a second PCB update process.

FIG. 8 is a flowchart showing an operation of a second dispatch process.

FIG. 9 is a flowchart showing the detailed operation of step 408.

FIG. 10 is a flowchart showing the detailed operation of step 408.

[Explanation of symbols]

 CPU # 0 to CPU # 3 CPU 5 Main storage device 6 to 9 Cache memory 6 to 914 14 to 15 Process control block (PCB) 20 Queue header 214 Process specific information 210 Priority 212 Last execution CPU number 30 Execution queue 31 to 31 33 Process name 40 Wait queue 61 First dispatch process 62 First PCB update process 63 Second PCB update process 64 Second dispatch process 200 Process control block area 300 CPU execution state management table

Claims (1)

(57) [Claims] 1. A cache memory is provided in each processor.
Process disperser of the multiprocessor system
In the switching method, the priority of the first process and the first process
The number of the executed processor and the first process
First step of reading from the process control block of
And all running processes with the lowest priority
And the priority of the process selected in the second step.
Comparing the priority of the first process with the priority of the second process;
The priority of the process selected in the step is the first
Dispatch when higher than process priority
A third step to abort, and only one process selected in the second step
At this time, the processor executing this process is given the first
A fourth step of dispatching the process of the second step; and a plurality of processes selected in the second step.
And the process selected in the second step
Said first process in a processor executing
There is a match with the number of the previously executed processor.
When present, the processor has the first process
A fifth step of dispatching;In the fourth step and the fifth step, the first
Process is not dispatched to any processor
Was selected in the second step
Pro executing dispatch processing in the processor
When the processor is present, the first
A sixth step of dispatching the process; The first process in the fourth, fifth and sixth steps
Is not dispatched to any processor
The first process is selected in the second step
Process is running on one of the running processors.
A seventh step of patching; A second program running on any processor
When a process is placed in an executable or waiting state
In the process control block of the second process,
The stored second process is the process executed immediately before.
Assign the number of the processor to the process where the second process is running.
First PCB update processing step to change to Sessa number
And when the third process is newly created, the third process
The third stored in the process control block of the process
The number of the processor on which the process
A second PCB update processing step for setting random values;
A process dispatching method comprising: