JPS62115567A - Multiplex processor system - Google Patents

Abstract

PURPOSE:To improve the cache hit rate by applying process dispatching processing so that a CPU executing the own process finally causes the execution state as much as possible so long as control based on the priority is not disturbed. CONSTITUTION:When no process under execution exists in CPUs 200-203 or a new process is enqueued in an executable process quene, the process dispatching processing is started. Then the process dispatching processing is informed to the CPU 200, and whether or not a VACANT flag (a flag representing the absence of a process under execution) is logical 1 is decided, and when the flag is 1, the head of the executionable process queue is dequeued. Then PCB (a process control block having an identification name of a CPU executing the process finally) information of the process is fetched in the inside of the CPU 200 and required flag is reset. Thus, the cache hit rate after the process dispatching processing is improved.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a multiprocessor system comprising a plurality of central processing units each having an internal cache and a main memory shared by these central processing units. Regarding
% relates to the dispatching control of processes in such systems.

(Prior Art) Most of the central processing units of current medium-sized computer systems are designed to reduce access time to the main memory.
It has an internal buffer memory called cache memory. The ninth step to improving the processing speed of the central processing unit and the entire computer system is to increase the probability that the above entry can be accessed on the cache memory without accessing the memory contents up to the main memory, that is, the hit rate of the cache memory. This is very important.

Various methods have been devised to meet this requirement and to make frequently accessed entries resident by discharging unnecessary entries from the cache memory early in the morning.

On the other hand, a normal medium-sized computer system is equipped with a process function for changing the process executed on each central processing unit in the system. If there is only one runnable process queue and some event occurs that gives rise to the possibility of a process switch, the dispatching facility will operate on the central processing unit of The execution priorities are compared between the process and the process at the head of the runnable process queue (to be dequeued next), and the process with the higher priority is set to the running state.

That is, if the currently executing process has a higher priority, the dispatching operation is terminated without performing any operation, and in the opposite case, the process is switched (or switched). The dispatching function also operates when the currently running process cannot continue running due to reasons such as waiting for resources to arrive or being allocated, or when there are no processes running on the central processing unit. Then, the first process in the executable process queue on the central processing unit is called and placed in an execution state.

When a friend process is enqueued to a runnable process queue that is neither running nor runnable, a process with a higher priority than the currently running process in the system is enqueued to the runnable process queue (logically). It may be in the lead. Therefore, the priorities of all processes currently being executed must be compared with the priority of the first process in the queue. Before that, check the status of each central processing unit, and if there is one that is functionally normal and has no executing process, the first process in the queue is unconditionally sent to that central processing unit as shown in Figure 5. Roll in.

Normally, this process priority comparison process is performed by performing an operation that triggers an event that causes the possibility of switching execution processes, such as a V-operation on a semaphore where a process queue exists, so that the process can be executed. It continues to be executed on the central processing unit that performed the enqueue to the process's queue. Assuming that all central processing units in the system are in a process execution state at the time of comparison processing, the following four cases are possible as a result of comparison processing.

The first is a case where the process being executed on the own central processing unit that performed the comparison process has the lowest execution priority among all the processes on the central processing unit and the top process in the executable process queue. It is.

The second case is that A, which is the lowest process being executed in its own central processing unit among all comparison target processes, has a lower execution priority than the first process in the executable process queue.

Third, a process running on its own central processing unit has a higher execution priority than the first process in the executable process queue, but a process on another central processing unit has a lower priority than the first process in the queue. This is a case where something with a ranking exists.

The fourth case is a case in which all the running processes have a higher execution priority than the first process in the process queue that can be executed.

According to the above conventional method, compared to the case of a single processing device in the cache memory, which is a vestige of the old days, the control is significantly changed (8).From this point of view, the first and second cases are In the third case, the process running on the central processing unit is exchanged with the top process in the executable process queue (5WAP).In the third case, the process running on the central processing unit executing the process with the lowest execution priority is In,
Swap this process with the top process in the runnable process queue. In the fourth case, no operation is performed.

Now, let's change our perspective and consider the cache memory inside the nine central processing units when a new process is rolled in.

Cache memory typically consists of several compartments to store a copy of a contiguous area of main memory of fixed size.

When the central processing unit accesses a main memory entry t, if a copy of the entry exists in the memory and is not cached, the LRU algorithm is used to discharge the contents of the most recently accessed compartment. , as well as a block load of the compartment containing the entry to be accessed.

Main memory (main memory accessed by different processes)
IJ is usually configured to a fairly exclusive extent, so
Immediately after a process is dispatched, there are many compartments in the cache memory that were currently being executed and are related to the next process. These are rarely accessed by currently running processes.

(Problems to be Solved by the Invention) According to the process dispatching method adopted in the above-mentioned multi-processor system,
The existence of a compartment in the cache memory related to the process being executed immediately after the dispatching process is because ratio control is not performed in consideration of the cache hit rate. There is a drawback that you cannot expect l1.

The purpose of the present invention is to execute the corresponding process last, to reduce the identification name of the friend central processing unit, and to set the priority in the process dispatching process. It is an object of the present invention to provide a multi-processor system having a structure that can eliminate the above-mentioned drawbacks and improve the cash hit rate by controlling the execution state to be executed by a companion central processing unit.

(Next means for solving the problem) The multiprocessor system according to the present invention each has a cache memory and processes as a unit of process! Consists of multiple central processing units to be executed, each process has a process control block 'ft, and each link contains the name of the process waiting for its turn to be executed on the central processing unit and the execution priority of the process. A dispatching system that is uniquely equipped with an executable process queue in the system, and in which each of the plurality of central processing units controls the execution of processes according to the priority of the process being executed and the priority within the link of the queue. Each of the plurality of central processing units is provided with first and second execution control means.

The first execution control means links the process to the inside of the processor control block? This is to store the identification name of the central processing unit that is executed last.

The second execution control means is for causing the dispatching means to determine the execution priority of the process as well as the identification name within the link.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating one embodiment of a central processing unit used in a multiprocessor system according to the invention.

FIG. 1 shows an embodiment of a portion related to dispatching control. In FIG. 1, xooo is a control storage unit, 100 is an instruction register, and 101 is an operation f145 of the instruction register 100. 102 is an address field of the instruction register 100, 103 is a decoder, 104 is a decoder, 1
10 is a control memory address register, 120 is a control memory,
130 is a control storage data register; 131 is an address section of the control storage data register 130; 132 is a control operation section of the control storage data register 130; 140 is an arithmetic unit;
41 is a comparator, 142 is a decoder, 143 is an arithmetic unit, 1
50 to 154 are first to fifth registers, 160
is the instruction counter %, 170 is the main memory address register,
181 is a status flag, 182 is a communication reception register, 18
10, 1811.1812 are VACANT, respectively.
0ONTEST, IPSRY flag. .

FIG. 2 is a block diagram illustrating one embodiment of a multiprocessor system according to the present invention. In Figure 2, 200~
203 is a central processing unit, 210 and 211 are system control units, 220 and 221 are main memories fc@, and 250 to 253 are input/output processing units.

In FIGS. 1 and 2, for example, the central processing unit 20
0 is signal line 191~194y! - communicates with other central processing units 201 to 203, input/output processing units [250 to 253, or main storage units [220, 221],
Send and receive data. The status flag 181 is a collection of various status flags (indicating the status of the central processing unit) that can be accessed from other devices, and is VACANT7-yf 1s1.
o, OONTg8T flag 811, and IPSR
Flag 1812 is used in process dispatching control as described below. Communication reception register 18
Reference numeral 2 is a sophisticated device that receives and stores communication data (particularly communication codes) from other central processing units 201 to 203 and input/output processing units 250 to 253.

FIG. 3 is an explanatory diagram showing a system common area on the main storage device used for process dispatching.

Figure 4 shows the friend central processing unit that finally executes the relevant process! This is an explanatory diagram showing an image of a process control block (PCB) having an identification name LAST OPU #1 (OPU). In Fig. 4, the "status display" is "Executing", "Executable", Waiting for 6 events, or other indications such as "Holding status", "Illegal status", and "LAST OP".
U#J has recently executed such a process and has a central processing unit number (OPU#).

5 and 6 show process dispatching processing and process exchange (5WAP
) is a flowchart describing the instruction communication receiving process.

Cross dispatching processing in a multiprocessor system according to the present invention will be described below with reference to these flowcharts.

Process dispatching is activated when there are no more processes running on a central processing unit in the system, or when a new process is enqueued into a runnable process queue. These events are VACANT 1810 or 0ONTES'l respectively.
' tsxxl- to the central processing unit (for example, 200) that performs the dispatching process.

For example, because the processing of a process that is progressing in cooperation with other processes is too far ahead, the system enters a synchronization wait state and spontaneously abandons the CP.
J combination becomes 1cIdVACANT-"1". However, the process that is waiting for a message to arrive from the input/output processing unit (for example, 250), which is waiting on the semaphore, receives the message with the V-operation of another process that is running, and executes it. When enqueued to a possible process queue, it becomes OONTgST-1''.

When the process dispatching process shown in FIG. 5 is started as described above, the VAOAN of the own central processing unit 200
Determine whether T ('%, when there is no process in progress) is "1" or not, and if VAOANT - "1", the process is placed at the head of the executable process queue (with the highest priority and The oldest enqueued process in the FIFO method)
(PCB information) is taken into the central processing unit 200, necessary flags are reset, and the process is completed.

Other CPU information (DPW#.

~DPW$3), first VACA
NT7. Is yg181o set? Is there n*OPU? investigate. However, this means that ``OPEN occurs before the cache hit rate''.
The system throughput will be greatly reduced unless the time that U is in the process non-execution state is reduced as much as possible.''If it is judged as ``VACANT-1'', the cash hit rate (i.e. In the present invention, a configuration is adopted in which the first process in the executable process queue is loaded into the OPU as soon as possible, without taking into account information about the OPU that last executed the relevant process.

Determine 0ONTE8T flag 1811 and set 0ONTES
T-0'', both the VAOANT flags 1810 become O'', and the process ends without any action. Thereafter, other OPU information DPW-$0-DPW#3 on the main storage device R220°221 is read. Here, VAO
ANT Maro"1" OOP U Ka existence f Shiba corresponding 0 PUl
c" Send '5WAP' communication. Upon receiving the "5WAP" communication, the OPU executes the communication reception identification process shown in FIG. 6 at an appropriate timing, decodes the 9 communication code "xx" set in the communication reception register 182 of FIG. '
5WAP". If it is VAOANT-1111, the corresponding process is taken into the own CPU of the first process in the executable process queue, and VACANT
The flag 1810 is reset and the process ends.

Again in FIG. 5, VACANT-”1 is in the system.
'', the head process in the executable process queue I, AS'l'
Read the DPW (DPW#2 or DPW#3) of the OPU corresponding to OPU$. Therefore, the priority of the process currently being executed is compared with the priority of the first process. 5! ``If the priority of the running process is lower than the priority of the first process, LAST
If the OPU# is the own OPU#, the exchange is performed by the own CPU. LAST OPU$) LA if not own OPU#
ST Exchanging the running process and the process at the head of the queue using the OPU corresponding to OPU#? conduct. In the case of the own CPU, processes are exchanged according to the description in the middle lower part of Figure 5, and in the case of other OPUs, "5WAP" communication is sent to the aOPU as described in the right column of Figure 5. do. “5
The corresponding OPU that received the “WAP” communication is
c Therefore, the process is replaced 0 As mentioned above and as follows, in the present invention, the LAS of the first process in the executable process queue
The leading process is loaded into the OPU corresponding to T CPU#.

LAST 0PU44-1c If the priority of the process being executed by the corresponding CPU is higher than the priority of the process at the head of the queue, if there is any other OPU that is executing a process with a lower priority than the process at the head of the queue. Ba,
Process exchange is realized on that CPU. in this case,
First, the possibility of exchange on the own OPU is determined, and if possible, the process is executed again without checking the possibility of exchange on other CPUs. In this way, execution efficiency can be improved. If you are unable to replace it on another CPU,
Similarly to the other embodiments described above, from the "5WAP" communication to the 6th
Replace the process according to the description in the middle of the diagram. If the priority of the first process in the executable process queue is lower than the priorities of all running processes, Process Z ends without any action.

Based on the above tank bottom, the first process in the executable process queue has the highest probability of being executed last.
jOPU, ie, the OPUVc process that is most likely to have remaining cache memory compartments associated with the process will be captured.

(Effects of the Invention) As described above, the present invention provides process correspondence with the identification name of the central processing unit executed last,
In the process dispatching process, the priority 111 is controlled as quickly as possible. Unless it interferes with this, by controlling the process so that it is executed in the central processing unit that last executed it as much as possible, after the process dispatching process is executed. This has the effect of improving the catch rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating one embodiment of a central processing unit used in a multiprocessor system according to the present invention. FIG. 2 is a block diagram illustrating one embodiment of a multiprocessor system according to the present invention. FIG. 3 is an explanatory diagram showing the system common area 7 on the main storage device used for process dispatching. FIG. 4 is an explanatory diagram showing the flow of the control block that last executed the corresponding process and has the identification name of the central processing unit LAST CPU@"f. FIG. 5 and FIG. 100 is a flowchart describing a process dispatching process that mainly operates on the control storage section surrounded by a broken line, and a process exchange instruction communication reception process. 100...Instruction register 101.102...Instruction register part 103 .10
4,142...Decoder 110.170 l-kai address register 120...Control memory 130...Data register 131, 132...Data register part 140.143・Fist・Arithmetic unit 141...Comparison Devices 150 to 154...Register 160...Instruction unit 181...Status flags 1810 to 1812...Status flag part 182...
-Communication reception register 1000...Control storage units 200-203...Central processing unit 210.211...System control unit 220.221
... Main storage devices 250 to 253 ... Input/output processing devices 191 to 194 ... Signal line patent applicant NEC Corporation representative Patent attorney Noro Ii Jusai 1 Figure 4 Figure 25 Figure 6

Claims (1)

[Claims] It consists of a plurality of central processing units each having a cache memory and executing processing in units of processes, has a process control block corresponding to the process, and waits for its turn to be executed on the central processing unit. The system has only one executable process queue having the name of the process and the execution priority of the process in each link, and each of the plurality of central processing units In the multi-processor system, each of the plurality of central processing units is provided with a dispatching means for controlling the execution of the process according to the priority within the link of the matrix. a first execution control means for storing therein an identification name of a central processing unit that last executed the process; and a first execution control means for determining the execution priority of the process and the identification name in the link by the dispatching means. 1. A multiprocessor system comprising a second execution control means for controlling the execution of the multiprocessor system.