JP3010820B2 - Printed board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board suitable for appropriately discharging and protecting static electricity charged on a block mounted on the printed circuit board.

[0002]

2. Description of the Related Art Conventionally, in electronic equipment and the like, a component for a so-called spark gap and a component such as a neon tube are connected between blocks of a printed circuit board in order to prevent malfunction due to static electricity.

[0003] By connecting these components between the blocks, for example, if static electricity falls on one of the blocks, the discharge components connected between the one block and the other block cause the one block to discharge. The discharged static electricity can be discharged, and malfunction of one block caused by the dropped static electricity can be prevented.

[0004]

By the way, as described above, a printed circuit board in which components for electrostatic discharge are connected between one block and the other block has a small mounting area for the main components on the printed circuit board. In addition, there was a disadvantage that prices increased.

Further, in the above-mentioned printed circuit board, since the earth pattern and the like are connected in a DC manner,
There is an inconvenience that affects measures against beats caused by feedback of harmonics and the like.

[0006] Further, when a component for electrostatic discharge is connected between one block and the other block, the discharge path of the static electricity becomes long, which causes a disadvantage that a semiconductor or the like is destroyed by the static electricity.

The present invention has been made in view of the above circumstances, and a pattern for discharging static electricity in a circuit block provided on a printed circuit board is provided independently of the ground of the circuit block. An object of the present invention is to provide a printed circuit board capable of reliably reducing beats generated in the circuit.

[0008]

According to the present invention, there is provided a printed circuit board having a plurality of blocks mounted thereon and a grounding means for connecting each of the plurality of blocks to a ground, wherein at least one of the plurality of blocks and the A first conductor having a first end and a second conductor having a second end are connected between the first end and the second end with a ground. It is disposed so as to be opposed with a gap left between it, and at least one of the plurality of blocks is connected to the ground independently of the grounding means, and the static electricity generated in the at least one block is discharged. It is possible to discharge to the earth side without passing through the earth means.

[0009]

According to the present invention, beats generated due to the discharge of the static electricity can be reliably reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a printed circuit board according to the present invention will be described below with reference to FIGS.

In FIG. 1, reference numeral 1 denotes a pattern formed on a substrate by, for example, a photographic method. An insulating material called a resist is applied to the surface of the pattern 1 (not shown).

At the end of the pattern 1, a solder portion 1a is formed.

An arbitrary number of peaks t and troughs b are formed at the tip of the solder portion 1a as shown in the figure.

The resist is not applied to the solder portion 1a (or the resist is peeled off), but the solder is fused by a so-called reflow soldering method using cream solder, for example.

Reference numeral 2 denotes a pattern formed on a substrate by, for example, a photographic method in the same manner as described above, and an insulating material called a resist is applied to the surface of the pattern 2 (not shown).

At the end of the pattern 2, a solder portion 2a is formed.

An arbitrary number of peaks t and troughs b are formed at the tip of the solder portion 2a as shown in the figure.

Without applying a resist to the solder portion 2a (or removing the resist), the solder is fused by a so-called reflow soldering method using cream solder, for example.

In the present embodiment, the gap g between these two patterns 1 and 2 is selected to be, for example, 0.15 mm, which is the minimum value of pattern formation by the photographic method.

There is a method called "dip" other than the above-mentioned reflow soldering method. When the above-mentioned solder is fused to one of the patterns 1 or 2 by this dipping method,
The solder is fused to the other pattern 2 or 1,
A so-called solder bridge may be caused.

Further, as shown in the figure, the crest t of the solder portion 1a of the pattern 1 and the crest t of the solder portion 2a of the pattern 2 are made to contact each other.

The static electricity has a characteristic of escaping to a low impedance pattern and a narrow gap.

That is, in the example of FIG. 1 described above, the solder portions 1a and 2a to which no resist is applied are formed on the patterns 1 and 2 and the solder is fused to these solder portions 1a and 2a, respectively. Impedance is realized.

Further, by setting the gap g between the peak portion t of the solder portion 1a formed on the pattern 1 and the peak portion t of the solder portion 2a formed on the pattern 2 to the minimum value in the photographic method, a narrow gap can be obtained. Has formed.

That is, for example, even if static electricity drops on the pattern 1 side, this static electricity is discharged from the peak part t of the solder part 1a formed on the pattern 1 to the peak part t of the solder part 2a formed on the pattern 2.

Therefore, if the pattern 2 side is connected to the base ground side, static electricity escapes to the base ground side (and vice versa), and the block on the pattern 1 side may malfunction. The semiconductor of this block is not destroyed.

Next, an example of an embodiment of a printed wiring board will be described with reference to FIG. 2 and the same parts as in FIG.

In FIG. 2, each of blocks 10, 20, 30, and 40 is a block composed of a circuit.
A power supply line 80 ′ from the DC / DC converter 50 and a ground line 90 ′ are connected to each of 0, 20, 30, and 40. The connection ends of the ground wire connected to the block 10 and the ground wire connected to the block 20 are connected to the connection ends of the ground wires connected to the block 30 and the block 40.
Is connected to the ground line 90 'from the DC / DC converter 50, and the blocks 10, 20, 30, and 40 are connected to the ground line 90'. .

A power terminal of the DC / DC converter 50 is connected to a power supply terminal 60 of an AC adapter (not shown), and a ground terminal of the DC / DC converter 50 is connected to a ground terminal of the AC adapter. I have.

Each of the blocks 10, 20, 30 and 40 is operated by the power supplied from the DC / DC converter 50.

Since the ground connection of each of the blocks 10, 20, 30 and 40 is configured in this manner, interference between these blocks 10, 20, 30 and 40 can be prevented, and The number of beats to be performed can be reliably reduced.

However, as shown in the figure, for example, when static electricity falls on the block 20, not only the circuit in the block 20 is destroyed, but also the other blocks 10, 30
And 40 are also affected.

In this case, as shown by the thick arrow in the drawing, the static electricity dropped on the block 20 should just fall on the ground wire 90 with the shortest distance.

However, considering only the countermeasures against static electricity,
Shortest and thick pattern (like the thick arrow shown in the figure)
May be formed, but in that case, the whole ground balance on the printed circuit board is disturbed, and a beat is generated.

Therefore, in this embodiment, as shown by a dashed line in the figure, for example, one of the pattern 1 shown in FIG. 1 is connected to the ground side of the block 20, and the pattern 2 is connected to the ground line 90 of the AC adapter. .

The other of the patterns 1 and 2 is made to contact each other as in FIG.

Similarly, one of the patterns 1 and 2 is connected to the block 10 and the ground line 90, the block 30 and the ground line, and the block 40 and the ground line, respectively, and the other of the connected patterns 1 and 2 is connected. As shown in FIG. 1, in the case of contact with a gap g, various obstacles due to static electricity can be further effectively prevented.

With this configuration, which block 1
Even if the static electricity falls on 0, 20, 30, or 40, the static electricity is discharged from the pattern 1 to the pattern 2 or from the pattern 2 to the pattern 1 without directly escaping to the ground wire 90 '. Since the static electricity escapes, the semiconductor elements of the blocks 10, 20, 30, and 40 are not broken.

The pattern 1 and the pattern 2 are not connected in a DC manner with a gap g. Therefore, since the ground balance is not lost due to the provision of the pattern 1 and the pattern 2, beats generated in the circuits constituting the block can be reliably reduced.

Next, referring to FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. Another example of the pattern 1 and the pattern 2 will be described.

In FIG. 3, reference numeral 101 denotes a pattern formed on a substrate by, for example, a photographic method.
For example, a resist is applied to the surface of No. 1 (not shown).

The solder portion 101 is attached to the end of the pattern 101.
a is formed.

An arbitrary number of peaks t and troughs b are formed at the tip of the solder portion 101a as shown in the figure.

The resist is not applied to the solder portion 101a (or the resist is removed), but the solder is fused by a so-called reflow soldering method using cream solder, for example.

Reference numeral 102 denotes a pattern formed on a substrate by, for example, a photographic method in the same manner as described above, and a resist is applied to the surface of the pattern 102 (not shown).

The solder portion 102 is attached to the end of the pattern 102.
a is formed.

An arbitrary number of peaks t and troughs b are formed at the tip of the solder portion 102a as shown in FIG.

The solder is not applied to the solder portion 102a (or the resist is removed), but the solder is fused by a so-called reflow soldering method using cream solder, for example.

Then, these two patterns 101 and 1
In this example, the gap g between 02 is selected to be, for example, 0.15 mm, which is the minimum value of pattern forming by the photographic method.

As shown in the figure, a peak t of the solder portion 101a of the pattern 101 and a solder portion 102 of the pattern 102 are formed.
The peaks t of a are made to contact each other.

The static electricity has a characteristic of escaping to a low impedance pattern and a narrow gap.

That is, in the example of FIG. 3 described above, the solder portions 101a and 102a on which the resist is not applied are formed on the patterns 101 and 102, and these solder portions 101a and 102a are formed.
A low impedance is realized by fusing solder to each of a and 102a.

Further, by setting the gap g between the peak portion t of the solder portion 101a formed on the pattern 101 and the peak portion t of the solder portion 102a formed on the pattern 102 to the minimum value in the photographic method, a narrow gap can be obtained. Has formed.

That is, for example, even if static electricity drops on the pattern 101 side, this static electricity is discharged from the peak part t of the solder part 101a formed on the pattern 101 to the peak part t of the solder part 102a formed on the pattern 102.

Therefore, if the pattern 102 side is connected to the base ground side, static electricity escapes to the base ground side, so that the block on the pattern 101 side malfunctions or the semiconductor of this block is destroyed. Never do.

Next, referring to FIG. 4, the same parts as those in FIGS. 1, 2 and 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. An example of the mode will be described.

In FIG. 4, reference numeral 103 denotes a pattern formed on a substrate by, for example, a photographic method.
For example, a resist is applied to the surface of No. 3 (not shown).

At the end of the pattern 103, a solder portion 103
a is formed.

An arbitrary number of peaks t and troughs b are formed at the tip of the solder portion 103a as shown in FIG.

The crest t is made higher than the crest t described in FIGS. 1 and 3, and the valley b is made deeper than the valley b described in FIGS.

The resist is not applied to the solder portion 103a (or the resist is removed), but the solder is fused by a so-called reflow soldering method using, for example, cream solder.

Similarly to the above, a pattern 104 is formed on a substrate by, for example, a photographic method. A resist is applied to the surface of the pattern 104, for example (not shown).

At the end of the pattern 104, the solder portion 104
a is formed.

An arbitrary number of peaks t and troughs b are formed at the tip of the solder portion 104a as shown in FIG.

The crest t is made higher than the crest t described in FIGS. 1 and 3, and the valley b is made deeper than the valley b described in FIGS.

The resist is not applied (or the resist is stripped) to the solder portion 104a, but the solder is fused by a so-called reflow soldering method using cream solder, for example.

Then, these two patterns 103 and 1
In this example, the gap g between the gaps 04 is selected to be, for example, 0.15 mm, which is the minimum value of pattern forming by the photographic method.

Further, as shown in the figure, the peak portion t of the solder portion 103a of the pattern 103 and the solder portion 104 of the pattern 104
The peaks t of a are made to contact each other.

The static electricity has a characteristic of escaping to a low impedance pattern and a narrow gap.

That is, in the example of FIG. 4 described above, the solder portions 103a and 104a to which the resist is not applied are formed on the patterns 103 and 104, and these solder portions 103a and 104a are formed.
A low impedance is realized by fusing solder to each of a and 104a.

Further, by setting the gap g between the peak portion t of the solder portion 103a formed on the pattern 103 and the peak portion t of the solder portion 104a formed on the pattern 104 to the minimum value in the photographic method, a narrow gap can be obtained. Has formed.

That is, for example, even if the static electricity drops on the pattern 103 side, the static electricity is discharged from the peak part t of the solder part 103a formed on the pattern 103 to the peak part t of the solder part 104a formed on the pattern 104.

Therefore, if the pattern 104 is connected to the base ground side, static electricity escapes to the base ground side, so that the block on the pattern 103 side malfunctions or the semiconductor of this block is destroyed. Never do.

Next, referring to FIG. 5, FIGS.
The same reference numerals are given to the same parts as in FIG. 4 and detailed description is omitted, and an example of still another embodiment of the pattern 1 and the pattern 2 will be described.

In FIG. 5, reference numeral 105 denotes a pattern formed on a substrate by, for example, a photographic method.
For example, a resist is applied to the surface of No. 5 (not shown).

The solder 105 is attached to the end of the pattern 105.
a is formed.

An arbitrary number of peaks t and troughs b are formed at the tip of the solder portion 105a as shown in FIG.

Without applying a resist (or removing the resist) to the solder portion 105a, the solder is fused by, for example, a so-called reflow soldering method using cream solder.

Reference numeral 106 denotes a pattern formed on a substrate by, for example, a photographic method, as described above. A resist is applied to the surface of the pattern 106 (not shown).

The solder 106 is attached to the end of the pattern 106.
a is formed.

An arbitrary number of peaks t and troughs b are formed at the tip of the solder portion 106a as shown in FIG.

Without applying a resist to the solder portion 106a (or removing the resist), the solder is fused by, for example, a so-called reflow soldering method using cream solder.

Further, as shown in the figure, the peak portion t of the solder portion 105a of the pattern 105 and the solder portion 106 of the pattern 106
a so that the valleys b of a
Valley b of solder portion 105a and solder portion 1 of pattern 106
The peaks t of 06a are in contact with each other.

Then, these two patterns 105 and 1
In this example, the gap g between 06 (between the peak t and the valley b) is selected to be, for example, 0.15 mm, which is the minimum value of the pattern forming by the photographic method.

The static electricity has a characteristic of escaping to a low impedance pattern and a narrow gap.

That is, in the example of FIG. 5 described above, the solder portions 105a and 106a on which the resist is not applied are formed on the patterns 105 and 106, and these solder portions 105a and 106a are formed.
A low impedance is realized by fusing solder to each of a and 106a.

Further, the gap g between the ridge t of the solder portion 105a formed on the pattern 105 and the valley b of the solder portion 106a formed on the pattern 106, and the valley b of the solder portion 105a formed on the pattern 105 A narrow gap is formed by setting the gap g between the peaks t of the solder portions 106a formed in the pattern 106 to the minimum value in the photographic method.

That is, even if static electricity drops on the pattern 105 side, for example, the static electricity is discharged from the peak portion t of the solder portion 105a formed on the pattern 105 to the valley portion b of the solder portion 106a formed on the pattern 106, and Is discharged from the valley b of the solder portion 105a formed in the pattern 106 to the ridge t of the solder portion 106a formed in the pattern 106.

Therefore, if the pattern 106 side is connected to the base ground side, static electricity escapes to the base ground side, so that the block on the pattern 105 side malfunctions or the semiconductor of this block is destroyed. Never do.

Next, referring to FIG. 6, the same parts as those in FIGS. 1, 2, 3, 4 and 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. An example of still another embodiment will be described.

In FIG. 6, reference numeral 107 denotes a pattern formed on a substrate by, for example, a photographic method.
For example, a resist is applied to the surface of No. 7 (not shown).

A solder portion 107 is attached to the end of the pattern 107.
a is formed.

At the tip of the solder portion 107a, for example, one crest portion t is formed as shown in the figure.

The solder is not applied to the solder portion 107a (or the resist is peeled off), but the solder is fused by a so-called reflow soldering method using cream solder, for example.

Reference numeral 108 denotes a pattern formed on a substrate by, for example, a photographic method, as described above, and a resist is applied to the surface of the pattern 108 (not shown).

A solder portion 108 is attached to the end of the pattern 108.
a is formed.

As shown in the figure, only one crest portion t is formed at the tip of the solder portion 108a.

[0098] The resist is not applied to the solder portion 108a (or the resist is removed), but the solder is fused by a so-called reflow soldering method using, for example, cream solder.

Then, these two patterns 107 and 1
In this example, the gap g between the colors 08 is selected to be, for example, 0.15 mm, which is the minimum value of pattern forming by the photographic method.

Also, as shown in the figure, the peak portion t of the solder portion 107a of the pattern 107 and the solder portion 108 of the pattern 108
The peaks t of a are made to contact each other.

The static electricity has a characteristic of escaping to a low impedance pattern and a narrow gap.

That is, in the above-described example of FIG. 6, solder portions 107a and 108a to which no resist is applied are formed on the patterns 107 and 108, and these solder portions 107a and 108a are formed.
A low impedance is realized by fusing solder to a and 108a, respectively.

Further, by setting the gap g between the peak portion t of the solder portion 107a formed on the pattern 107 and the peak portion t of the solder portion 108a formed on the pattern 108 to the minimum value in the photographic method, a narrow gap can be obtained. Has formed.

That is, even if static electricity drops on the pattern 107 side, for example, the static electricity is discharged from the peak part t of the solder part 107a formed on the pattern 107 to the peak part t of the solder part 108a formed on the pattern 108.

Therefore, if the pattern 108 is connected to the base ground side, static electricity escapes to the base ground side, so that the block on the pattern 107 side malfunctions or the semiconductor of this block is destroyed. Nothing.

It is to be noted that the present invention is not limited to the above-described embodiment, but may take various other configurations without departing from the gist of the present invention.

[0107]

According to the present invention, the first conductor insulated by providing a gap between the static electricity generated in at least one block provided on the printed circuit board without passing through the ground means of this block. And can escape directly to this ground via the second conductor. Accordingly, since the earth balance of the block is not lost and the static electricity does not flow through the grounding means, there is an advantage that the beat generated in the circuit constituting the block can be reliably reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram for explaining an example of an embodiment of a first pattern and a second pattern of a printed board of the present invention.

FIG. 2 is a diagram for describing an example of an embodiment of a printed circuit board of the present invention.

FIG. 3 is a diagram for explaining another example of the first and second patterns of the printed circuit board according to another embodiment of the present invention;

FIG. 4 is a diagram for explaining a first pattern and a second pattern of a printed circuit board according to still another embodiment of the present invention;

FIG. 5 is a diagram for explaining a first pattern and a second pattern of a printed circuit board according to still another embodiment of the present invention;

FIG. 6 is a diagram for explaining a first pattern and a second pattern of a printed circuit board according to still another embodiment of the present invention;

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H05K 1/02

Claims (1)

(57) [Claims] 1. A printed circuit board having a plurality of blocks mounted thereon and comprising grounding means for connecting each of the plurality of blocks to ground, wherein a printed circuit board is provided between at least one of the plurality of blocks and the ground. A first conductor having a first end and a second conductor having a second end are opposed to each other with a small gap between the first end and the second end. The grounding means is connected to at least one of the plurality of blocks and the ground independently of the grounding means, and discharges static electricity generated in the at least one of the plurality of blocks. A printed circuit board, which is capable of discharging to the ground side without passing through the grounding means.