JP3009088B2 - Scan format converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan format converter for converting image data between a raster scan system and a block scan system in image data scanning, and more particularly to a pixel for one line of raster scan system image data. The present invention relates to a scan format conversion apparatus which can relatively easily cope with a case where the number is changed or a case where the number of horizontal or vertical pixels representing the size of a block of block scan image data is changed.

[0002]

2. Description of the Related Art A two-dimensional image handled by a television camera, a scanner, or the like is generally handled as raster scan type image data in which horizontal scanning is repeated and vertical scanning is performed. On the other hand, in recent image processing techniques, image processing is performed in blocks of a predetermined size due to the size of hardware, processing time, and the like. That is, block scan type image data for performing processing in units of blocks having the number of horizontal pixels Bx and the number of vertical pixels By is used.

FIG. 1 shows an example of raster scan image data.
FIG. 2 shows an example of block scan image data in which the number of block horizontal pixels Bx = M = 8 and the number of block vertical scans By = N = 8.

Conventionally, a method using a memory has been used as scan conversion between raster scan image data and block scan image data. That is, the writing operation of the raster scan image data is sequentially performed on the memory, and the reading of the block scan image data is performed in the scanning order of the block scan. In this case, the write address generator and the read address generator are configured by hardware such as a counter.

[0005]

However, as described above, conventionally, when the read address is constituted by hardware, the format of the block scan image data (M and N in FIG. 2) is changed by changing the encoding algorithm.
However, there is a problem in that when the number of pieces of data changes, hardware increases. That is, in the conventional configuration, counters are set for each of the block horizontal pixels and the block vertical pixels, but two counters are prepared and the frequency division value is determined for each of the counters, so that the hardware increases. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and is intended to solve the problem of changing the format of raster scan image data and block scan image data when the number of horizontal and vertical pixels is changed. It is another object of the present invention to provide a scan format conversion apparatus which can easily cope with the above.

[0007]

Means for Solving the Problems The present invention provides a scanning format conversion apparatus for converting image data of the raster scanning method and the block scanning method of the image data scanning, a memory for temporarily storing input image data, in the memory The first register for storing the temporarily stored number of pixels, the second register for storing the number of horizontal pixels of one block, and the read address for the memory are the same.
Write the amount of change to move to the beginning of the next line in one block.
The third register to remember and counts from 0 to 1 each,
One block in which the count value is stored in the second register
When the count becomes equal to the number of horizontal pixels, the count value is set to 0.
A first counter that resets and repeats this operation thereafter
And the read address on the same line in one block
In order to proceed one by one,
Fourth register for storing a number to advance by a predetermined number
And a third or fourth value according to the count value of the first counter.
Registers of the register, a selection circuit for selecting either an adder for adding the output of the fifth register infra an output of said <br/> selection circuit, the adder output and the first of comparing the values, if the output of the adder exceeds the value of the first register, a comparator adder adding a value obtained by subtracting the value of the first register from the value of the second register, the comparison added Output of the vessel
A second address stored as a read address for the memory.
The above object has been attained by providing the register No. 5 and a second counter for generating a write address for the memory. Also, the first register
The number to be stored is m × N and stored in the second register.
Let the number be M, and let the number stored in the third register be m−M
+1 and the number stored in the fourth register is 1.
Things. Here, m is one line of the raster scan.
Number of pixels, N is the vertical pixel of one block of block scan
The number M is the number of horizontal pixels in one block of the block scan.
is there.

[0008]

FIG. 1 shows a scan example of raster scan image data, and FIG. 2 shows a scan example of block scan image data.

As shown in FIG. 2, the number m of pixels in one line is m.
(For example, 64) The number of horizontal pixels in one block is M (for example, 8) and the number of vertical pixels is N (for example, 8).

The block scan is performed as shown in FIG.
It is performed by repeating the following three operations. That is, a first operation that moves right by one on the same line, a second operation that moves to the beginning of the next line when the end of the same line is reached within the same block, and a last data of the last line of the same block. Is reached, the third operation moves to the beginning of the next block.

According to the present invention, the above operation is realized as follows.

First, an input image is temporarily stored in a memory, the number of pixels (m × N) temporarily stored in the memory is stored in a first register, and the number of horizontal pixels (M) in one block is stored in a second register.
In the register. Further, the third register has a change amount (m) for moving to the head of the next line in the same block.
−M + 1) is stored. Next, the first operation is performed by adding the value of the fourth register by an adder and advancing one by one to the right on the same line in one block.

At this time, the number of pixels is counted up by the first counter. When one line (M) of one block is completed, the value of the third register is added to the adder by the selection circuit instead of the fourth register. To the next line, and the second operation is performed.

The above first and second operations are repeated, and the output of the adder is compared with the total number of pixels (m × N) stored in the first register to determine the end of reading of one block. Then, by adding a value (M−m × N) obtained by subtracting the value of the first register from the value of the second register by the adder, the block can be shifted to the head of the next block. Is performed.

An address for accessing the memory always enters the fifth register. The write address of the raster scan image data to the memory is generated by the second counter.

As described above, according to the present invention, two counters for the horizontal direction and the vertical direction are not required unlike the related art, and the change of the block size can be relatively easily performed only with the horizontal counter. Can also respond.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 3 is a block diagram showing a schematic configuration of the scan format conversion apparatus according to the present embodiment.

In FIG. 3, reference numeral 10 denotes a memory for storing an image, and 12 denotes the number of pixels (m.times.m ) temporarily stored in the memory.
N), a first register for storing the number of block horizontal pixels (M), 16 a first counter for counting the number of block horizontal pixels, 18
Is a third register for storing the amount of change for shifting the address to the beginning of the next line in the same block, 20 is a fourth register for advancing the address by one in the same line to the right, and 22 is The selection circuit 24 selects one of the registers 18 and 20 in accordance with the value of the counter 16 of 1, the fifth register 24 stores an address from which block scan image data is read, and the output circuit 26 selects the output of the selection circuit 22. 5
The adder 28 adds the value of the register 24, and the adder 28
If the output of 6 exceeds the total number of pixels, a value (−m × N + M) for shifting the address to the head of the next block is added,
If it does not exceed, it is a comparison adder that outputs the value as it is, and 30 is a second counter that generates a write address of raster scan image data.

Here, each of the registers 12, 14, 18, 2
The values of 0 and 24 can be arbitrarily set according to the number M of block horizontal pixels, the number N of block vertical pixels, and the number m of pixels in one line.

Hereinafter, as shown in FIG. 2, m = 64 and M =
A case will be described in which raster scan image data of 64 pixels per line is converted to an 8 × 8 block scan image format, where N = 8.

In FIG. 2, the first register 12 stores m
× N = 64 × 8 = 512, the second register 14 stores M =
8, the third register 18 is m−M + 1 = 64−8 + 1
= 57 is set. The raster scan image data is sequentially written in the memory 10 according to the address generated by the second counter 30.

The read address of the memory 10 is given by the output of the fifth register 24. Hereinafter, the updating operation of the fifth register 24 will be described.

First, the values of the fourth register 20 and the fifth register 24 are 0, indicating the head address of the first line. The first counter 16 is a divide-by-8 counter and repeats counting from 0 to 7, during which time the read address is incremented by one in the fourth register 20, and
From 7 to 7. The addition of 1 by the fourth register 20 represents the first operation 2 in FIG. 2 in which the address is advanced by one on the same line to the right. When the value of the counter 16 changes from 7 to 0, the selection circuit 22
The third register 18 is selected, the value 57 of the third register 18 is added to the address value 7 at that time, and 7 + 5
When 7 = 64, the address becomes 64, and the leading data of the second line is designated and read. The addition of the value m-M + 1 (57 in this embodiment) of the third register 18 represents the second operation 4 for advancing the address to the head of the next line.

When the same operation is repeated and the value 57 of the third register 18 is added to the last data address 455 of the eighth line, the result is 455 + 57 = 512. But,
Since the total number of data is 512 or more, the first register 12 and the second register 14 pass through the adder 28-
m × N + M = −512 + 8 is added to obtain 512 + (− 5
When (12 + 8) = 8, the address becomes 8, which indicates the address of the first data at the upper left of the next block as shown in FIG. This represents the third operation 6 in FIG.
In this way, the processing moves to the next block, and the same processing is repeated thereafter. It should be noted that even when the block scan image data is not 8 × 8 as in the present embodiment but another value M × N, it is easy to set a predetermined value in each of the registers 12, 14, 18, and 20. It is clear that the same process is performed in the same manner.

[0026]

As described above, according to the present invention, the generation of the read address of the block scan image data can be easily constituted by the counter, the register, the adder, and the comparator, and the counter of only the block horizontal image data is provided. Has the effect that a configuration is possible by determining the frequency division value of. The block scan data also has an excellent effect that it can be arbitrarily determined by determining the total number of images and the number of block horizontal pixels.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing the concept of raster scan image data.

FIG. 2 is an explanatory diagram showing the concept of block scan image data.

FIG. 3 is a block diagram showing a schematic configuration of a scan format conversion apparatus according to the embodiment;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Memory 12 ... 1st register 14 ... 2nd register 16 ... 1st counter 18 ... 3rd register 20 ... 4th register 22 ... Selection circuit 26 ... Adder 28 ... Comparison adder 30 ... 2nd Counter

Claims (2)

(57) [Claims] A scan format conversion apparatus for converting image data between a raster scan system and a block scan system in image data scanning, wherein a memory for temporarily storing input image data and a number of pixels temporarily stored in the memory are stored. A first register for storing the number of horizontal pixels of one block, and a read address for the memory in the same block.
To store the amount of change to move to the beginning of the next line
, And counts from 0 to 1 each time, and the count value is stored in the second register.
Equal to the number of horizontal pixels in one block stored in the
When the count value is reset to 0,
The first counter that repeats the above operation, and one read address on the same line in one block
Address in the raster scan system
A fourth register for storing the number to advance by several, a count value of said first counter, a third or fourth register, a selection circuit for selecting one, the output of said selection circuit An adder that adds the output of the fifth register described below; and compares the output of the adder with the value of the first register. If the output of the adder exceeds the value of the first register, 2
From the value of the register and comparator adder adding a value obtained by subtracting the value of the first register, the output of the comparator adder reads A to the memory
A scan format conversion apparatus , comprising: a fifth register for storing as a dress; and a second counter for generating a write address for the memory. (2) The scan format conversion device according to claim 1.
At The number stored in the first register is m × N (m is a raster
N is the number of pixels in one line of scan,
(The number of vertical pixels in one block) If the number stored in the second register is M (M is a block
The number of horizontal pixels in one block of can) The number stored in the third register is m-M + 1, The number stored in the fourth register is one.
Scan format converter.