JPH0691598B2 - Pattern recognition method and image reduction apparatus therefor - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an image reducing apparatus and a pattern recognition method using the image reducing function, and more specifically, an image used for preprocessing such as image data compression and noise removal. The present invention relates to a reduction device and a pattern recognition method which enables a high-speed pattern recognition device.

[Technical background of the invention and its problems]

Conventionally, a grayscale image pattern recognition system is mainly implemented by the following two methods. However, both methods require computer processing, and the calculation time is very long, which is an obstacle to industrial application. Therefore, there is a demand for improvement in a system that enables pattern recognition at high speed.

In the first conventional pattern recognition method, the video signal obtained by the scanning of the ITV camera is A / D converted, and the obtained conversion value is temporarily stored in the image buffer memory, and then the image area in the computer memory is stored. Was stored in another memory as image data and computer-processed by a program for pattern recognition. However, the image data input for pattern recognition is, for example, 128
It is huge, such as × 128 pixels or 256 × 256 pixels, and the recognition time by the computer for that is long, which is 2 seconds, and a high-speed computer with a high-speed and large-capacity image buffer memory and large-capacity memory is required. Then, the pattern recognition could not be performed at a practical cost.

In the second method, in consideration of the difficulty of digital processing of a multi-valued image in the practical application device as in the first method, the video signal is binarized and converted, and this binary image is reduced. And enlargement and pattern recognition.
However, in the recognition using a binarized image, whether proper binarization is possible has a great influence on obtaining a normal result. There are also problems such as changes over time in ITV cameras and lighting systems.

[Object of the Invention]

Therefore, an object of the present invention is to provide a method for obtaining a reduced image of a multi-valued image and performing high-speed pattern recognition using compressed image data, and a suitable apparatus used for the pattern recognition method. An object of the present invention is to provide an image reduction device for a multi-valued image that enables high-speed pattern recognition by calculating the conventional computer processing part with dedicated hardware.

[Outline of Invention]

The present invention provides at least an A / D converter as dedicated hardware for an image reduction device, two adders connected in series to share partial sums and partial sum additions, a memory, and an address to the memory. After the input video signal is converted from an analog signal into a two-dimensional digital signal P (M, N) by an A / D converter, it is at least based on a desired reduction ratio by using two counters that output signals. In order to obtain a reduced image of horizontal 2 pixels and vertical 2 pixels, for example, 1/16, when calculating the sum of the digital conversion values of horizontal 4 pixels and vertical 4 pixels, in the case of 1 / n reduction, P ( 0,0) + P (1,0) + ...
The partial sum of P (n-1,0) is stored in the memory address M (0), and the partial sum of P (n, 0) + P (n + 1,0) + ... P (2n-1,0) is stored in the memory. At the address M (1) of the memory, primary memory is sequentially stored in the memory, P (0,1) + P (1,1) ... P (n-1,1) is added to the memory address M (0) Stored in the memory address M (0), and P (n, 1) + P (n + 1,1) + P (2n-1,1)
Is added to the memory address M (1) and is added to the memory M (1).
It is a pattern recognition method characterized by storing in an address and sequentially repeating this to obtain a reduced image as a multi-valued image for pattern recognition. It is an image reduction device to obtain. According to the calculation of the hardware in the present invention, the total pattern recognition time can be shortened to 0.2 seconds instead of 2 seconds in the conventional first method.

Example of Invention

 An embodiment of the image reducing device of the present invention will be described below.

FIG. 1 shows a block diagram of this embodiment. First, a video signal obtained as an analog signal such as grayscale from the ITV camera is converted into a grayscale value of 8 bits (0 to 255 levels) by an A / D converter.

FIG. 2 shows an array of converted two-dimensional digital conversion values, the conversion values being symbols P (0,0), P (1,0), P.
(2,0) ... Represented by P (M, N). The conversion value of 4 × 4 pixels existing in the one-dot chain line is the two-dimensional 1/16 in this embodiment.
It shows one pixel after reduction.

FIG. 3 is a memory address array diagram for explaining the data storage and storage of the memory M.

Next, the operation of the hardware for the two-dimensional 1/16 reduction will be described with reference to FIGS. In FIG. 1, the outputs of the registers R1 and R3 are set to 0. now,
P (0,0) (see FIG. 2) is output from the A / D converter, but the input signal a ₁ of the adder A1, the output of the register R1 is 0
, The input signal b ₁ of the adder A1 is 0. Therefore, the adder A1 adds a ₁ and b ₁ , and the sum P (0,
0) is set in register R1. Next, as a ₁ , P (1,
0) (see FIG. 2) is input from the A / D converter, P (0,0) is input as b ₁ from the register R1, and P (1,0) and P (0,0) are input. It is added by the adder A1 and P (0,0) + P (1,
0) is set in register R1. Following the same manner as a ₁ P (2,0) and P (3, 0) is input P (0,0) + P
(1,0) + (2,0) + P (3,0) is calculated, and the result is the b ₂ input of the adder A2. Since the output of the register R3 is set to 0, the a ₂ input of the adder A2 is 0. Therefore, the adder A2 adds a ₂ and b ₂ , and the partial sum P (0,0)
+ P (1,0) + P (2,0) + P (3,0) is set in the register RS. Then the output d ₂ of the register R2 is (here Fig. 3 address 0) address of the specified memory M in the register R4 is written primary storage.

Similarly, P (4,0) + ... + P (7,0) to P (M-
3,0) + ... + P (M, 0) are added, and 1 to 1 of the memory M are respectively added.
It is temporarily stored at address i.

Next, when P (0,1) (see FIG. 2) is output from the A / D converter, the contents of address 0 of memory M P (0,0) + P (1,0) +
P (2,0) + P (3,0) is read and set in the register R3. By the adder A1 and the register R1, the partial sum P (0,
When the calculation of 1) + P (1,1) + P (2,1) + P (3,1) is completed, the contents of the register R1 and the contents of the register R3 are added by the adder A2, and the result is again stored in the memory M. It is temporarily stored at address 0. Similarly, P (0,2) + ... + P (3,
The partial sum of 2) and the partial sum of P (0,3) + ... + P (3,3) are also added, and 16 pixels [P (0,0) within the one-dot chain line in FIG. 2 are added.
The sum of + P (1,0) ... + P (3,3)] is stored in the address 0 of the memory M.

As described above, the sum of every 4 pixels in the horizontal direction and 4 pixels in the vertical direction and 16 pixels is stored in each of the addresses 1 to i of the memory M in FIG. 3, and then 16 addresses are stored in the addresses below i + 1 in FIG. The predetermined number of input pixels is repeated and the sum of them is stored. Thus, in the present invention, a 1/16 reduced image can be obtained in real time by hardware without performing computer processing. It should be noted that the average value of 16 pixels may be obtained by multiplying the sum value by 1/16. However, this can be achieved by performing a data shift operation, and the averaging process can be executed at the same time. Therefore, at the same time when the input of image data is completed, an averaged reduced image is obtained, which enables high-speed pattern recognition.

The counter CH and the counter CV in FIG. 1 become the address signal A of the memory M via the register R4. Signals controlled by another control circuit such as control of the number of input pixels (vertical × horizontal pixel), creation of a reduced image, start, end, etc. are input to φ _H and φ _V.

〔The invention's effect〕

According to the image reducing apparatus of the present invention, avoiding computer processing,
Since the summation and averaging process of the pixel group to be reduced by hardware is performed, it is 25
It took 1.7 seconds for the 2D 1/16 reduction of 6 × 240 pixels, but only 0.016 seconds, and a multi-value reduced image could be obtained at the same time when the input of the image data was completed.

Further, according to the pattern recognition method of the present invention, since a compressed reduced image is obtained by hardware, it takes about 2 seconds in the conventional computer pattern recognition, but only about 2 seconds.
We were able to reduce the time to 0.2 seconds. As a result, the industrial application of image processing could be expanded to various fields without impeding productivity.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an image reducing apparatus of the present invention, and FIGS. 2 and 3 are graphs for explaining the operation of the embodiment. A1, A2 ... Adder, M ... Memory.

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP 54-136135 (JP, A) JP 49-43537 (JP, A) JP 54-150933 (JP, A) JP 56- 79571 (JP, A) JP-A-56-90375 (JP, A)

Claims (2)

[Claims] 1. An A / D converter and at least two adders connected in series to share partial sum and partial sum addition.
The two-dimensional digital conversion value P (M, N) is obtained from the input video signal by the hardware consisting of the memory and the two counters that output the address signal to the memory, and the two-dimensional digital conversion value P (M, N) is obtained based on the desired reduction ratio. When calculating the sum of the digital conversion values for every two vertical pixels, in the case of reduction of 1 / n, the partial sum of P (0,0) + P (1,0) + ... P (n-1,0) Is stored in memory address M (0), and P (n, 0) +
The partial sum of P (n + 1,0) + ... P (2n−1,0) is stored in the address M (1) of the memory, and the primary storage is sequentially performed in the memory.
1) + P (1,1) + ... P (n-1,1) is the memory address M
(0) is added and stored in memory M (0),
P (n, 1) + P (n + 1,1) + ... Adds P (2n-1,1) to the memory address M (1), stores it in the memory M (1), and repeats this sequence in sequence. A pattern recognition method characterized by performing pattern recognition from the obtained reduced image. 2. An A / D converter and at least two adders connected in series for sharing partial sums and partial sum additions.
A hardware comprising a memory and two counters for outputting an address signal to the memory is provided, and a two-dimensional digital conversion value P (M, N) is obtained from the input video signal and at least based on a desired reduction ratio. When calculating the sum of these digital conversion values for every 2 pixels in the horizontal direction and 2 pixels in the vertical direction, 1 / n
For reduction of P (0,0) + P (1,0) + ... P (n-1,0)
Store the partial sum of P at the address M (0) of the memory and P (n, 0)
The partial sum of + P (n + 1,0) + ... P (2n−1,0) is stored in the address M (1) of the memory, and primary storage is sequentially performed in the memory.
(0,1) + P (1,1) + ... P (n-1,1) is the memory address M
(0) is added and stored in memory M (0),
P (n, 1) + P (n + 1,1) + ... Adds P (2n-1,1) to the memory address M (1), stores it in the memory M (1), and repeats this sequence in sequence. An image reducing device characterized by obtaining a reduced image.