JPS5937770A - Picture reduction device - Google Patents

Abstract

PURPOSE:To perform high-speed pattern recognition, by obtaining a reduced image as a multilevel picture by an A/D converter dedicated to a picture reduction device, a memory, and two adders. CONSTITUTION:An input video signal is converted by the A/D converter from an analog signal to a two-dimensional digital signal. For example, when an image reduce to at least every two lateral picture elements and every two longitudinal picture elements on the basis of desired reduction magnification, for example, every four lateral picture elements and every four longitudinal picture elements for 1/16 reduction, and the sum of those digital converted values is calculated principally by adders A1 and A2. The sum is stored in a memory M to obtain the reduced image as the multilevel picture. Thus, a desired reduced image is obtained on real-time basis by hardware without performing computer processing. Further, data is shifted to perform averaging processing, and the averaged reduced image is therefore obtained simultaneously with the completion of data input, performing the high-speed pattern recognition.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image reduction device and a pattern recognition method using its image reduction function, and more specifically, to an image reduction device and a pattern recognition method using the image reduction function thereof, and more particularly, to an image reduction device and a pattern recognition method using the image reduction function thereof. This invention relates to a reduction device and a pattern recognition method that enables high-speed pattern recognition. , [Technical background of the invention and its problems] Conventionally, the following two methods have been mainly implemented in pattern recognition systems for gray scale images, but both methods require computer processing and the calculation time is high. This has been a very long process and has been an impediment to industrial applications, and there is a need for improved systems that enable high-speed pattern recognition.

In the first conventional pattern recognition method, the video signal obtained by scanning the TV camera is A/D converted, the obtained converted value is stored in the image backup memory, and then the image inside the computer memory is stored. The area is stored as image data in other memory, and computer processing is performed using a program to perform pattern recognition. however,
The image data input for pattern recognition is enormous, for example 128 x 128 pixels or 256 x 256 pixels, and the computer recognition time required for this is as long as 2 seconds. It required a high-speed computer with a large capacity image buffer memory and a large capacity memory, and it was not possible to recognize and weave patterns at a practical cost.

The second method takes into consideration that digital processing of multivalued images is difficult in practical equipment as in the first method, and converts the video signal into a binary image, reducing the size of this binary image. and enlargement to perform pattern recognition. However, in recognition using a binarized image, whether or not appropriate binarization can be performed greatly influences obtaining a normal result.

“There are also problems such as changes in the ITV camera and lighting system over time.

[Object of the Invention] Therefore, an object of the present invention is to provide a novel method for performing high-speed pattern recognition using compressed image data obtained by obtaining a reduced image of a multivalued image. teeth,
It is an object of the present invention to provide a multivalued image reduction device that performs calculations using dedicated hardware to perform conventional computer processing and enables high-speed pattern recognition.

[Summary of the invention]

The present invention consists of at least an A/D converter, a memory, and two adders as dedicated hardware for an image reduction device.The A/D converter converts an input video signal from an analog signal to a digital After converting to a signal, KI/'i 4 pixels horizontally and 4 pixels vertically to obtain a reduced image of, for example, 1/16, at least every 2 pixels horizontally and 2 pixels vertically, based on the desired reduction magnification.
For each pixel, the sum of these digital conversion values is mainly calculated by 2
This is an image reduction device that performs calculations mainly using two adders, stores the sum in the memory, and obtains a reduced image as a multivalued image, and also performs pattern recognition from the above reduced images. It is a pattern recognition method. Through hardware calculations in the present invention, the total pattern recognition time can be reduced from 2 seconds in the first conventional method to 0.
It can be shortened to 2 seconds.

[Embodiments of the invention]

An embodiment of the image reduction device of the present invention will be described below.

FIG. 1 shows a block diagram of this embodiment. First, the video signal obtained from the ITV camera as an analog signal such as gradation is converted into 8 bits (0 to 255
level) is converted to a gray value.

Figure 2 shows the array of two-dimensional digital converted values, where the converted values are signals p(o, o), p(
1,0), P(2,0)...P(M,N). The converted value of the 4×4 pixels existing within the dashed-dotted line represents one pixel after two-dimensional 1/16 reduction in this embodiment.

FIG. 6 is a memory address arrangement diagram for explaining data storage of the memo IJM.

Next, the operation of the hardware when performing two-dimensional 1/16 reduction will be described with reference to FIGS. 1 to 3. In FIG. 1, the outputs of register R1 and register R6 are set to zero. Now, P(o, o) (number M in the second figure) is output from the A/D converter and becomes the input signal of al of adder A1, but since it is set to the output Fio of register R1, the addition The input signal b0 of the device A1 is 0. Therefore adder A1
tj: Adds al and b1, and the sum p(o, o) is set in register R1.

Next, when P(1,0) (see Figure 2) is input as a□ from the A/D converter, p(o, o) is input as b□ from register R1, and P(1, 0)(!:P(0,0
) is added by adder A1 as P(0,0)+P(1,
0) is set in register R1. Similarly, when P(2,0) and P(3,0) are input as d, P(
0,0) + P(1,0) 10P(2,0) 10P(3,0)
is calculated, and the result becomes the b2 input of adder M.

Since the output of register R3 is set to 0, the 62 input power of adder A2 is 0. Therefore, adder Mua2 and b2i are added, and the partial sum P(0,0)+P(1°o)
+p(kai,0)+P(3,0) is set in register R2. Next, the output d2 of the register R2 is written to the address of the memory 13M designated by the register R4 (here, address 0 in FIG. 3) and temporarily stored.

Thereafter, P(4,0)+...10P(7,0) to P(M-3,0)+...+P(M,O) are calculated in the same way, and each of them is added to the memo IJM. It is temporarily stored in addresses 1 to i.

Next, when P(0,1) (see Figure 2) is output from the A/D converter, the contents of address O in memory M are P(0°0) 10P(1,0)+P(2, '0) 10P(3,0) is read and set in register R6. By adder A1 and register R1, partial sum P(0,1)+P(1°1)+
When the calculation of P (2, 1) + P (3, 1) is completed, adder A2 adds the contents of register R1 and register R6, and the result is temporarily stored again at address O of memo 17M. be done. Similarly, P(0゜2)+...→
- partial sum of P (3, 2) and P (0, 3) ten...+
The partial sum of P(3,3) is also added, resulting in 16 pixels within the dashed-dotted line in Figure 2.
The sum of P(3,:3)) is stored at address 0 of the memo IJM.

As described above, the sum totals of 4 pixels horizontally, 4 pixels vertically, and 16 pixels are respectively stored at addresses 1 to i of the memory M in FIG. A predetermined number of inputs of 16 pixels each are repeated, and the total sum thereof is stored.

Thus, in the present invention, a 1/16 reduced image can be obtained in real time using hardware without computer processing.

Note that the average value of 16 pixels may be multiplied by the total value 'kl/16, but this can be done by performing a data shift operation, and averaging processing can also be executed at the same time. Therefore, an averaged reduced image is obtained as soon as the input of image data is completed, making high-speed pattern recognition possible.

Note that it becomes the address signal A of the memory M via the counter CH and the counter CVI/i register R41z in FIG.

φ□ and φ7 are input with signals that are controlled by another control circuit to control the number of input pixels (vertical×horizontal pixels), create reduced image, start, end, etc.

〔Effect of the invention〕

According to the image reduction device of the present invention, computer processing is avoided, and
Since hardware performs summation and averaging processing of the pixel group to be reduced, conventional computer reduction processing requires
56 x 240 pixels two-dimensional 1/16 reduction K 1.7
It took only 0.016 seconds to obtain the multi-level reduced image at the same time that the λ phase of the image data was completed.

According to the pattern recognition method of the present invention, since a compressed reduced image is obtained by hardware, the time required for conventional computer pattern recognition is only about 0.2 seconds, compared to about 2 seconds. could be shortened to. As a result, the industrial application of image processing has been able to expand to various fields without hindering productivity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the image reduction apparatus of the present invention, and FIGS. 2 and 6 are graphs explaining the operation of the embodiment. AI, A2...adder, M...memory. Figure 1

Claims (1)

[Scope of Claims] 1. Equipped with hardware consisting of at least an A/D converter, a memory, and two adders, obtains a digital conversion value from an input video signal, and converts at least a horizontal value based on a desired reduction ratio. An image reduction device characterized in that the sum of digital conversion values is calculated for every two pixels vertically, and the sum is stored in the memory to obtain a reduced image. 2. Obtain digital conversion values from the input video signal using hardware consisting of at least an A/D converter, memory, and two adders, and convert them for at least every 2 pixels horizontally and 2 pixels vertically based on the desired reduction ratio. 1. A pattern recognition method, comprising: calculating a sum of digitally converted values, storing the sum in the memory, and performing pattern recognition from the obtained reduced image.