JP2783917B2 - Image address generating apparatus and image address generating method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Contents] Industrial Application Field Conventional Technology (FIGS. 9 and 10) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Embodiment (1) First Embodiment (2) Description of the second embodiment (FIGS. 7 and 8) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image address generating apparatus and an image address generating method, and more particularly, to an apparatus and method for generating an image address when performing image band compression and data transfer processing. It is about.

In recent years, in the field of image communication such as videophone and video conference, when digital images are communicated, image data is compressed to limit communication lines and improve transmission efficiency or to save recording media. It is undergoing communication processing and storage processing.

According to this, a target image, 2 ⁿ pixels × 2 ^m
The image address of the line is a block size, for example, 8
It is generated sequentially so as to perform block scanning on the entire matrix divided into × 8 pixels.

For this reason, the address generating circuit can be simply constructed, but the screen width is limited to 2 ⁿ pixels (256, 512... Bits). Therefore, the screen width may be N pixels (N is a multiple of 8) instead of 2 ⁿ pixels due to the necessity of the display screen application, the resolution and cost of the CRT device, the memory capacity and cost, etc. When there is a request to perform image compression processing and transfer processing only on an arbitrary image area of a target image, the conventional circuit cannot generate an image address.

Therefore, a register for setting an arbitrary screen width without being limited to the screen width 2 ⁿ of the target screen is provided,
An apparatus and method capable of generating an image address in consideration of a screen width are desired.

[0007]

2. Description of the Related Art FIGS. 9 and 10 are explanatory views according to a conventional example.

FIGS. 9A and 9B are explanatory diagrams of an image address generating apparatus according to a conventional example, and FIG. 9A is an explanatory diagram of image band compression.

In FIG. 1A, for example, in the field of image communication such as videophone and videoconference, there is a tendency that digital image data is subjected to image band compression and transfer processing.
COMPUTER DESIGN 89 / August issue published by Dempa Shimbun). This is for the purpose of efficiently transmitting data within the limits of the communication line, and for compressing image data to save recording media. According to this, the target image N (2
ⁿ ) × M (2 ^m ) pixels are divided into, for example, 8 × 8 pixel blocks, and the block image is divided into two-dimensional DCTs.
(Discrete cosine transform) processing is performed. Also, two-dimensional DC
The T-processed block image is decomposed into two-dimensional sequence components, and bits are assigned to each of the sequence components.
Image band compression is being realized by encoding this.

FIG. 1B is a block diagram of a conventional image address generating device. In FIG. (B), the target image N
(2 ⁿ ) × M (2 ^m ) = 512 (2 ⁹ ) × 512 (2 ⁹ ) pixels are 8 ×
An image address generator for dividing and transferring data in units of blocks of 8 pixels includes an X counter 1 composed of a 3-bit binary counter and a Y counter 2 composed of a 3-bit binary counter.
BX counter 3 comprising a 6-bit binary counter;
It comprises a BY counter 4 consisting of a 6-bit binary counter.

The function of the device is as follows.
Based on LK, X counter 1 outputs image addresses A0 to A2 indicating X coordinates in the block and X carry. The Y counter 2 outputs the image addresses A9 to A11 indicating the Y coordinates in the block and the Y carry based on the X carry. Further, the BX counter 3 outputs image addresses A3 to A8 indicating the X coordinate of the block matrix and the block X carry based on the Y carry. In the BY counter 4, an image address A12 indicating the X coordinate of the block matrix based on the block X carry
~ 17 is output. Thereby, the target image N × M = 512
It is possible to generate an image address based on the upper left portion of the screen when dividing and transferring x512 pixels in blocks of 8x8 pixels.

FIGS. 10A and 10B are diagrams for explaining an image address generating method according to a conventional example, and FIG. 10A shows the order of generation of image addresses in a block.

In FIG. 1A, an image address in a block of a target image N = 2 ⁿ pixels (scan (horizontal) direction) × M = 2 ^m lines (vertical direction) is represented by b = head address of the screen.
Then, the first line is from b to b + N−1, the second line is from b + N to b + 2N−1, and the third line is b + 2.
Are assigned in raster scan order by the method of N to b + 3N-1.

FIG. 1B shows the transfer order of the block image of the target image N × M. In FIG. 6B, the transfer order of the block images B1 to B64... Is performed in the raster scan order on the screen in the same manner as the image address generation order in the block. This is referred to as a block scan to distinguish this from a raster scan.

For example, the image address of a block size of 8 × 8 pixels in the compression transfer processing of the target image N × M = 512 × 512 pixels is as follows. First, assuming that the top address at the upper left of the target screen is “0”. When the first line in the block image B1 is line-scanned, the X counter 1 counts from 0 to 7 and outputs image addresses A0 to A7. Next, the Y counter 2 is generated by the X carry from the X counter 1.
Is incremented, and the process moves to the second line in the block. In the second line scan, X
The counter 1 counts from 0 to 7 and the image address A
0 to 7 are output. At this time, one of the Y counters 2 is configured to have the address 512. This allows
Image addresses 512 to 519 are output.

When the scanning of all the lines of the first block image B1 is completed, the Y carry from the Y counter 2 is output, and the BX counter 3 is incremented. As a result, the head address = 8 of the second block image B2 is output. The above-described line scan in a block is similarly repeated, and a block scan of the entire screen is executed.

Thus, the target image N × M = 512 × 512
Image addresses A0 to A17 each having a block size of 8 × 8 pixels and related to pixel transfer processing can be sequentially output with reference to the upper left portion of the screen.

[0018]

According to the conventional example, the address is generated by the binary counter. For this reason, the screen width N is limited to 2 ⁿ . Further, the width of the scan range must be equal to the screen width N.

From this, the demands of the image processing system,
For example, the need for display screen applications, CRT
The screen width N is not 2 ⁿ pixels but 2 ⁱ × an arbitrary integer = N because of the relationship between the resolution and cost of the device, the memory capacity and cost, etc.
Scan range W × H with pixels or arbitrary screen width N
When there is a request to perform image compression processing and transfer processing of only pixels, the conventional circuit cannot generate an image address. This is because, when a specific area of the target image is cut out and the image is compressed and transmitted to a communication line or the like, an image address of an arbitrary screen width N of the target image cannot be specified, and a scan range for cutting out the specific area cannot be specified. That's why.

As a result, there is a problem that a block scan address having an arbitrary screen width N cannot be generated.

The present invention has been made in view of the problems of the conventional example, and is not limited to a screen width of 2 ⁿ pixels, but is provided with a register for setting the screen width, and an image address in consideration of the screen width. It is an object of the present invention to provide an image address generating device and an image address generating method capable of generating an image address.

[0022]

FIG. 1 is a block diagram showing the principle of an image address generating apparatus according to the present invention.

According to the first image address generating device of the present invention,
From an image of N pixels × M lines, 2 ⁱ pixels × 2 ^j
Means for extracting an image area of an arbitrary size in which blocks each having a line image area as a basic unit are collected; means for setting the number of blocks in the horizontal direction of the image area to be extracted; and image area to be extracted. Means for setting the number of blocks in the vertical direction, means for dividing the arbitrary image area into a plurality of blocks according to the number of blocks in the horizontal direction and the vertical direction, and means for distinguishing the positions of the plurality of blocks. Means for generating an address and for generating an address for distinguishing the position of a pixel in the block. In the first device of the present invention, a first register (start address register 60) for setting a start address for designating a head pixel of an arbitrary image area extracted from the image having the size of N pixels × M lines. ), A second register (horizontal block number register 23A) for setting the number of horizontal blocks of the arbitrary image area as a first block count value, and a number of vertical blocks of the arbitrary image area. As a second block count value (vertical block number register)
24A) and a first counting means 1 for generating an address for distinguishing a horizontal position of a pixel in the block with reference to a start address set in the first register.
1, a second counting means 12 for generating an address for distinguishing a vertical position of a pixel in the block with reference to the start address, and a first counter set in the second register. First block counting means for counting the number of blocks in the horizontal direction based on the block count value; and counting of the number of blocks in the vertical direction based on the second block count value set in the third register. A second block counting means 14 for performing the operation; a data calculating means 16 for generating an address for distinguishing the positions of a plurality of blocks based on the outputs of the first and second block counting means; And a control means for controlling input / output of the second and third registers, the first and second counting means, the first and second block counting means, and the data calculation means.

According to a second image address generator of the present invention,
The first block counting means includes first comparing means 13A for comparing a first block count value set in the second register with the number of blocks counted by the first counting means. And the second block counting means includes:
A second comparison means 14A for comparing a second block count value set in the third register with the number of blocks counted by the second counting means is provided.

The image address generation method according to the present invention provides an image area of an arbitrary size obtained by collecting blocks each having an image area of 2 ⁱ pixels × 2 ^j lines as a basic unit from an image of N pixels × M lines. And generating a starting address of the image area, the number of blocks in the horizontal direction and the number of blocks in the vertical direction of the image area. An input for performing a setting process of inputting an arbitrary image area into a plurality of blocks according to the number of blocks in the horizontal direction and the vertical direction based on the setting process, and discriminating positions of the plurality of blocks. And generating an address for distinguishing the position of a pixel in the block, thereby achieving the above object.

[0026]

According to the first apparatus of the present invention, there are provided means for setting the numbers of horizontal and vertical blocks of an image area to be extracted from an image having a size of N pixels × M lines. Therefore, an image obtained by multiplying an image area of a block by an integer from an image having a size of N pixels × M lines can be extracted without limiting the image area to 2 ⁿ pixels × 2 ^m pixels. Thereby, as compared with a case where an image area having a size of 2 ⁿ × 2 ^m pixels is extracted from an image having a size of N pixels × M lines, the pixel size is an integer multiple of 2 ⁱ × 2 ^j . When the image area is extracted, the degree of freedom of the image area that can be extracted from the image of N pixels × M lines can be greatly increased. That is, in the first apparatus of the present invention, the second register for outputting the number of blocks in the horizontal direction of an arbitrary image area (hereinafter also referred to as a transferred image area) as the first block count value, And a third register for outputting the number of blocks as the second block count value.

For this reason, the scan range from which a specific area of the target image N × M pixels is cut out, for example, the number of horizontal and vertical blocks is set as the first and second block count values, and the first and second block count means 13 and 14 are used. When the first image address is set in the data operation means 16 as the external control data S0, the first counting means 11 outputs the first carry signal S1 and the lower address AL. A second carry signal S2 is output from the second counting means 12 based on the first carry signal S1, and a first block count signal S3 is produced based on the second carry signal S2. It is output from one block counting means 13.

Further, based on the first block count signal S3, a second block count signal S4 is output from the second block counting means 14, and the first carry signal S1 and the second carry signal S2 are output. , A plurality of data control signals C1 to Ci are output from the control means 15 based on the first block count signal S3 and the second block count signal S4. Thus, the upper address AM is output from the data operation means 16 based on the plurality of data control signals C1 to Ci and the external control data S0.

For this reason, the screen width does not become 2 ⁿ pixels but becomes 2 ⁱ × from the requirements of the image processing system, for example, the necessity of a display screen application, the resolution and cost of the CRT device, the memory capacity and the cost, etc. When an arbitrary integer = N pixels, for example, i = 3, an arbitrary integer (2 or more) is 4
Even when N1 = 320 pixels and N2 = 400 pixels at 0 and 50, or when there is a request to perform image compression processing and transfer processing only on an arbitrary image area of the target image N × M, The screen width N is not limited to the screen width = 2 ⁿ pixels as in the conventional example.

Thus, it is possible to generate a block scan address having an arbitrary screen width N.

According to the second apparatus of the present invention, FIG.
In the first block counting means 13 as shown in FIG.
Of the second block counting means 1 is provided.
4 is provided with second comparing means 14A.

For this reason, the scan range for cutting out a specific area of the target image N × M pixels, for example, the number of horizontal and vertical blocks is set as the first and second block count values, and the first and second block count means 13 and 14. When the first block count signal S3 and the first compared block signal S5 are
The second block count signal S4 and the second compared block signal S6 are compared by the second comparing means 14A. As a result, each comparing means 13
A, based on the comparison result signals S7, S8 from
As in the case of the device described above, a plurality of data control signals C1 to Ci are generated, and the upper address AM can be output from the data calculation means 16 based on the control signals C1 to Ci and the external control data S0.

Thus, similarly to the first device, the screen width is 2 ⁿ from the necessity of the application of the display screen, the resolution and cost of the CRT device, the memory capacity and the cost, etc.
Even when 2 ⁱ × an arbitrary integer = N pixels instead of pixels, or when there is a request to perform image compression processing and transfer processing only on an arbitrary image area of the target image N × M, The width N is not limited to the screen width W = 2 ⁿ pixels as in the conventional example. This makes it possible to sufficiently cope with the request for the image compression transfer processing.

According to the image address generation method of the present invention, the start address b of the transferred image area with respect to the screen width N, the number of blocks in the horizontal direction = W / ^2i, and the number of blocks in the vertical direction = H / 2. ^j is being set.

Therefore, it is possible to generate an image address a for transferring a pixel having an arbitrary screen width N from a target screen N × M pixels in which image blocks of 2 ⁱ pixels × 2 ^j lines are arranged in a matrix. .

This makes it possible to perform image compression transfer processing of an arbitrary screen width N based on the generated image address a.

[0037]

Next, an embodiment of the present invention will be described with reference to the drawings. 2 to 6 are views for explaining an image address generating device according to an embodiment of the present invention.

(1) Description of First Embodiment FIG. 2 is a block diagram of an image address generating apparatus according to a first embodiment of the present invention.

In the figure, for example, an image address generator for performing digital band compression and transfer processing of digital image data such as a videophone call or a video conference is provided with an X counter 21 and an X counter 21.
It comprises a Y counter 22, a horizontal block counting circuit 23, a vertical block counting circuit 24, a control circuit 25, and an upper address operation output circuit 26.

That is, the X counter 21 is an embodiment of the first counting means 11, and outputs the X carry signal and the lower address AL as an example of the first carry signal S1 based on the data control signals C8 and C9. Output. For example, a 3-bit counter is used as the X counter 21,
When scanning inside each block in the horizontal direction with reference to an arbitrary start address having a screen width as shown in FIG. 5, the lower 3 bits of the image address are output and counted up each time one pixel is transferred. is there.

The Y counter 22 is an embodiment of the second counting means 12, and is an example of the second carry signal S2 based on the data control signals C10 and C11 and the X carry signal S1 from the X counter 21. It outputs a Y carry signal. For example, a 3-bit counter is used as the Y counter 22, and indicates a scanning position in the row direction (vertical direction) in each block with reference to a start address b having an arbitrary screen width as shown in FIG.

The horizontal block counting circuit 23 is an embodiment of the first block counting means 13 and includes a horizontal block number register.
23A and a BX counter 23B. The counting circuit 23
BX = 0, which is an example of the first block count signal S3, is generated by the data control signals C12 and C13 based on the carry signal S2.
It outputs a detection signal. For example, when the number of horizontal blocks is set based on the start address b of an arbitrary screen width as shown in FIG. 5, the down count is performed based on the Y carry signal S2 from the Y counter 22, and the horizontal direction (horizontal) is set.
Are counted. Thereby, when the count value becomes “0”, BX indicating transfer of one row of the block is indicated.
= 0 detection signal is output.

The vertical block counting circuit 24 is an embodiment of the second block counting means 14, and comprises a vertical block number register 24A and a BY counter 24B. The counting circuit 2
4 is a data control signal C1 based on the BX = 0 detection signal S3.
4, a BY = 0 detection signal as an example of the second block count signal S4 is output by C15. For example, after counting the number of blocks for one row of the horizontal block transferred based on the start address b at a point having an arbitrary screen width N as shown in FIG. 5, it is down-counted based on the BX = 0 detection signal. , The number of blocks in the vertical direction (vertical direction) is counted. Thus, when the count value becomes “0”, a BY = 0 detection signal is output, and a block image in an arbitrarily designated scan range is transferred.

The control circuit 25 is an embodiment of the control means 15, and includes an X carry signal S1, a Y carry signal S2, and a BX signal.
A plurality of data control signals C1 to C15 are output based on the = 0 detection signal S3 and the BY = 0 detection signal S4. The control circuit 25 will be described in detail with reference to FIG. Table 1 shows the data control signals C1 to C15.
It is described in. The signal states in the table indicate operations when the data control signals C1 to C15 are activated (active).

[0045]

[Table 1]

The upper address operation output circuit 26 is an embodiment of the data operation means 16, and the start address register 6
0, buffers 61, 66, 68, constant 1 register 62,
It comprises a constant 2 register 63, a selector 64, a computing unit 65, a stack register 67, and an address register 69.
Here, the image address a of an arbitrary coordinate point (x, y) in the block is defined as follows.

A = b + x + y × N, where b is the start address, and N is the screen width (unit: pixel) of the target image.

The lower 3 bits of the image address a are assigned to the X counter 21 described above. The remaining upper bits are assigned to the address register 69. Accordingly, one eighth of the image address a is held in the address register 69. Note that the upper bits of the image address are the upper address AM.

The main function of the arithmetic output circuit 26 is as follows.
The start address set in the register 60 via the host bus is output to the address bus (hereinafter, referred to as A bus) by the buffer 61 based on the data control signal C1. As a result, the data is written to the address register 69 and output to the image memory or the like as the first upper address AM. Further, the constant K1 or the constant K2 of the register 62 or the register 63 is selected by the selector 64 based on the data control signal C7, and is output to the arithmetic unit 65. Arithmetic unit 6
At 5, the upper address AM of the address register 69 and the constant K1 or K2 are performed. This result is output to the address bus by the buffer 66 based on the data control signal C2.

Thus, the upper address AM of the address register 69 is updated. At this time, the new upper address AM of the address register 69 is output to the image memory or the like, and is stored in the stack register 67 based on the data control signal C4. The stored image address a is based on the data control signal C3. The buffer 68 outputs the data to the address bus.

From this, a plurality of data control signals C1 to C1
Start address b as an example of C8 and external control data S0
Based on the upper address AM (= the fourth image address).
Bit or higher bits).

FIGS. 3A and 3B are explanatory diagrams of a control circuit according to the first embodiment of the present invention, and FIG. 3A shows a configuration diagram thereof.

In FIG. 9A, a control circuit 25 includes a condition selector 50, an AND circuit 51, a program counter (hereinafter referred to as a P counter) 52, and a ROM (14 words).
53.

The condition selector 50 detects an address generation condition, for example, a control start signal START, an X carry signal S1, a Y carry signal S2, a BX = 0 detection signal S3, and a BY = 0 detection, based on the value PC 0-3 of the P counter 52. Signal S4
Is to select. The AND circuit 51 performs an AND operation of the condition jump signal JMP and the condition select signal SEC, outputs a load control signal SRR, and controls the P counter 52.

The P counter 52 reads the ROM signal based on the clock signal Clk, the reset (RESET) signal and the ROM address.
53 and the condition selector 50 are controlled. In addition,
The P counter 52 indicates where the step Pn [n = 1 to 14] in the operation flowchart of FIG. 4 is being executed.

The ROM 53 outputs data control signals C1 to C15 and a condition jump signal JMP for executing a condition change based on the counter output value PC0-3 of the P counter 52. The ROM 53 is composed of a total of 14 words, and corresponds to step Pn in the operation flowchart of FIG.
[N = 1 to 14]. When the condition is satisfied, the ROM 53 outputs a set end signal JA3-0 to the P counter 52.

FIG. 7B shows a part of the contents of the data table of the ROM of the control circuit according to the first embodiment of the present invention.

In FIG. 6B, for example, the data control signal C14 = 1 is read by the ROM address = “0001”, and the counter 24 counts down based on the number of vertical blocks based on the control signal C14. . Also, the Y counter 22 is cleared to "0" by the data control signal C10 = 1, and similarly, the X counter is cleared by the data control signal C8 = 1.
The counter 21 is cleared to "0". Further, the start address b is set to A by the data control signals C1 = 1 and C5 = 1.
The data is transferred from the register 60 to the address register 69 via the bus.

The AND circuit 51 stores the ROM address =
By the conditional jump signal JMP = 1 by “1011”,
Enable conditional jumps. At this time, the condition selector 5
A value of 0 selects BX = 0 detection as a jump condition. If the condition is satisfied, the load processing is performed by activating (active) the load control signal SRR of the P counter 52. If the condition is not satisfied, the P counter 52 continues counting.

As described above, according to the image address generator according to the first embodiment of the present invention, as shown in FIG. 2, the X counter 21, the Y counter 22, the horizontal block counting circuit 23, and the vertical block counting circuit 24, a control circuit 25 and an upper address operation output circuit 26.

For this reason, the scan range in which a specific area of the target image N × M pixels is cut out, for example, the number of horizontal and vertical blocks is set as the first and second block count values in the horizontal block count circuit 23 and the vertical block count circuit 24. When the first image address b is set as the external control data S0 in the upper address calculation output circuit 26, the X counter 21 outputs the X carry signal S1 and the lower address AL. Further, a Y carry signal S2 is output from the Y counter 22 based on the X carry signal S1, and a BX = 0 detection signal S3 is output from the horizontal block counting circuit 23 based on the Y carry signal S2.

Further, a BY = 0 detection signal S4 is output from the vertical block counting circuit 24 based on the BX = 0 detection signal S3, and the X carry signals S1, Y carry signals S2, B
A plurality of data control signals C1 to C15 are output from the control circuit 25 based on the X = 0 detection signal S3 and the BY = 0 detection signal S4. This allows the plurality of data control signals C1 to C1
Upper address A based on C15 and external control data S0
M is output from the upper address operation output circuit 26.

For this reason, the screen width is not 2 ⁿ pixels but 2 ⁱ ×, because of the requirements of the image processing system, for example, the necessity of the application of the display screen, the resolution and cost of the CRT device, the memory capacity and the cost, etc. Any integer (2 or more)
= N pixels, for example, i = 3, any integer (2
N1 = 320 pixels and N2 = 4 when the above is 40 and 50
Even if the pixel width is 00 pixels or if there is a request to perform image compression processing and transfer processing only on an arbitrary image area of the target image N × M, the screen width N is equal to the conventional screen width = 2. ⁿ
It is not limited to pixels.

Thus, it is possible to generate a block scan address having an arbitrary screen width N.

Next, the image address generating method according to the first embodiment of the present invention will be described while supplementing the operation of the apparatus.

FIG. 4 is a flowchart showing the operation of the image address generating apparatus according to the first embodiment of the present invention.
FIG. 6 shows a relationship diagram (No. 1 and 2) between an image address and a screen width according to each embodiment of the present invention.

For example, an arbitrary scan range W × H pixels is designated for a screen format N [arbitrary screen width] × M [lines] pixels as shown in FIG. A method of generating an image address when performing a transfer process will be described. If the start address is b and an arbitrary coordinate position in the block in the screen format of the start address b is x, y (hereinafter simply referred to as (x, y)), the image address a is given by the first equation. .

A = b + x + y × screen width N (1) That is, in FIG. 4, first, in step P1, a process of confirming control start (START) is performed. At this time, if the control is to be started (YES), the flow shifts to Step P2. If the control is not to be started (NO), the control waits for a control start instruction such as a control start signal. Further, the start address b, the constant K1, the constant K2, the number of horizontal blocks W / 8 and the number of vertical blocks H / 8 are set in the respective registers via the host bus by the host CPU before control is started.

Next, in step P2, initialization processing of each circuit is performed. At this time, the X counter 21 and the Y counter 22
Are both cleared to "0".

Next, at step P4, the stack register 6
In step 7, the start address b is saved or transferred. Thus, the initialization of the processing of the first row of the block matrix is completed.

Thereafter, in step P5, the counter values of the address register 69 and the X counter 21 are output as image addresses.

Further, at step P6, a constant K1 is added to the X counter value. In parallel with this, the constant K1 of the register 62 is selected by the selector 64 based on the data control signal C7, and is output to the arithmetic unit 65. Arithmetic unit 6
In the case of 5, 1 is added based on the start address b written in the address register 69. This result is output to the address bus by the buffer 66 based on the data control signal C2.

Thereafter, in step P7, it is determined whether or not the X carry is output from the X counter 21. At this time, X
If there is a carry output (YES), step P8
To end the generation of the address of one line in the block. If there is no X carry output (NO), the process returns to step P5 and repeats steps P5 to P7.

Next, in Step P8, a constant K1 is set in the address register 69, and 1 is added to the Y counter value. This is processing for shifting to the next line in the block. Here, the constant K1 set in the register 62 is one eighth of an arbitrary screen width N. The image address of the coordinates (x, y) in the block is a = b + x + y × N. The image address a 'of (x, y + 1) is as follows.

A '= b + x + (y + 1) × N, where N
Is the screen width. That is, the image address a 'of (x, y + 1) is equal to the value obtained by adding N to the image address a of (x, y). Since 1/8 of the image address a is stored in the address register 69, adding 1 to y means that a constant K1 = 8 of the screen width N is added to the address register 69.
This is equivalent to adding one part.

Next, in step P9, it is determined whether or not there is an output of the Y carry from the Y counter 22. At this time, if there is an output of Y carry (YES), the flow shifts to Step P10 to end the processing of one block. If there is no Y carry output (NO), the process returns to step P5 and repeats steps P5 to P9.

Next, in step P10, the value stored in the stack register 67 is transferred to the address register 69. This is a process for moving to the next block.

Thereafter, at step P11, a constant K1 is added to the image address of the address register 69, and the BX counter 23B is decremented by one. That is, the process returns to the beginning of the block in step P10, and the process moves to the next block by adding 1 to the address register value. Here, adding 1 to the address register value is equivalent to adding 8 to the image address a.

Further, in step P12, it is determined whether or not the BX counter value has become "0". At this time, if the number of horizontal blocks has become "0" (YES), the flow shifts to step P13 to terminate the generation of the address of one row of the block matrix. If it does not become "0" (NO), the process returns to step P4 and returns to steps P4 to P4.
Repeat 12 Immediately before the operation of Step P13 is executed, since the generation of the address of one row of the block matrix is completed, the image address a indicates the right end of the scan range as shown in FIG. Here, in order to move to the head of the next row of the block matrix, +
8. It is sufficient to move in the x direction by -W. Here, assuming that coordinates before execution of step P13 are (x, y), the image address is a = b + x + y × N. On the other hand, the image address a 'of the next row of the block matrix is as follows.

A ′ = b + (x−W) + (y + 8) × N =
a + 8N-W, where N is the screen width.

That is, if 8N-W is added to the image address a, the block matrix is moved to the head of the next row. Since one eighth of the image address a is stored in the address register 69, N-W / 8 may be added to the register 69. This N−W / 8 is set to a constant K
2 is set in the register 63 in advance.

As a result, the counter value of the register 63 is added to the address register 69 in step P13, thereby moving to the head of the next row of the block matrix. Further, 1 is subtracted from the BX counter value in parallel with the update of the address register 69.

Further, in step P14, it is determined whether or not the number of vertical blocks has become "0". At this time, if the number of vertical blocks becomes “0” (YES), the image address generation processing ends. If it does not become "0" (NO), the process returns to step P3 and returns to step P3.
Repeat steps 3 to P12.

As a result, an image address "a" is generated for block transfer of a block image of 8.times.8 pixels in a scan range arbitrarily specified to a screen format N [arbitrary screen width] .times.M [lines] pixels.

As described above, according to the image address generating method according to the first embodiment of the present invention, the start address b of the transferred image area related to the screen width N, the number of blocks in the horizontal direction =
W / 8 and the number of blocks in the vertical direction = H / 8 are set.

Therefore, it is possible to generate an image address a for transferring a scan range W × H pixels having an arbitrary screen width N in which image blocks of 8 pixels × 8 lines are arranged in a matrix.

As a result, it is possible to perform image compression transfer processing of an arbitrary screen width N based on the generated image address a.

(2) Description of the Second Embodiment FIG. 7 shows a configuration diagram of an image address generator according to a second embodiment of the present invention.

In the figure, the second embodiment differs from the first embodiment in that the first block counting means 13 in the principle diagram of FIG. 1 is provided with a first comparing means 13A, and the second block The counting means 14 is provided with a second comparing means 14A.

That is, the horizontal block number comparison output circuit 29
Is another embodiment of the first block counting means 13, which comprises a horizontal block number register 29A, a comparator 29B and a BX counter.
Consists of 29C. The horizontal block number register 29A is the same as the horizontal block number register 23A according to the first embodiment. The comparator 29B is an embodiment of the first comparing means 13A,
The BX counter value, which is an example of the block count signal S3, is compared with the set value of the number of horizontal blocks, which is an example of the first compared block signal S5.
7 is output. At this time, the BX counter 29C
Are the data control signals C15 and C based on the Y carry signal S2.
The BX counter outputs the BX counter value to the comparator 29B.

The vertical block number comparison output circuit 30 is another embodiment of the second block counting means 14, and includes a vertical block number register 30A, a comparator 30B and a BY counter 30C.
Consists of The vertical block number register 30A is the same as the vertical block number register 24A according to the first embodiment. Comparator 30
B is an embodiment of the second comparing means 14A, and the BY counter value, which is an example of the second block count signal S3, and the second
Is compared with a set value of the number of vertical blocks, which is an example of the compared block signal S6, and outputs a vertical match detection signal S8 to the control circuit 31. At this time, the BY counter 30C outputs the BY counter value to the comparator 30B by the data control signals C17 and C18 based on the horizontal coincidence detection signal S7.

[0092] Other circuit configurations will be described. That is, the X counter 27 is another embodiment of the first counting means 11, and the first counter is based on the data control signals C11 and C12.
Of the carry signal S1 and the lower address AL. For example, a 3-bit counter is used as the X counter 27. When scanning inside each block in the horizontal direction with reference to an arbitrary start address as in the first embodiment, the lower 3 bits of the image address are used.
It outputs a bit and counts up each time one pixel is transferred.

The Y counter 28 is another embodiment of the second counting means 12, which is an example of the second carry signal S2 based on the data control signals C13 and C14 and the X carry signal S1 from the X counter 27. Output a Y carry signal. A 3-bit counter is used as the Y counter 28, and indicates a scanning position in a row direction (vertical direction) in each block with reference to a start address b having an arbitrary screen width N as shown in FIG.

The control circuit 31 is another embodiment of the control means 15, and comprises a plurality of data control signals C1 to C18 based on the X carry signal S1, Y carry signal S2, horizontal coincidence detection signal S7 and vertical coincidence detection signal S8. Is output.

Table 1 shows data control signals C1 to C18. The signal states in the table indicate the operation when each of the data control signals C1 to C18 is activated (active).

[0096]

[Table 2]

The upper address operation output circuit 32 is another embodiment of the data operation means 16, and includes a start address register 40, buffers 41, 44A, 44B, 48A to 48C, a constant K
1 register 42, constant K2 register 43, arithmetic unit 45,
Start address holding register (hereinafter referred to as T register)
47 and an address register 49. The main function of the arithmetic output circuit 32 is that the start address b set in the register 40 via the host bus is the data control signal C
5 based on an address bus (hereinafter C)
Bus). Thereby, the address b
Is written to the T register 47. The register 42
Alternatively, the constants K1 or K2 of the register 43 are output from the buffers 44A and 44B based on the data control signals C3 and C4, and output to the arithmetic unit 45 via a second internal bus (hereinafter, referred to as a B bus). You. In the arithmetic unit 45,
The operation of the upper address of the address register 49 and the T register 47 and the constant K1 or the constant K2 is performed based on the data control signal C8. At this time, the T register 47 holds the start address in the block based on the data control signal C9, and starts the line scan in the block.
The head address is transferred to the address register 49 via the buffer 48C based on the data control signal C7. This eliminates the need to transfer the address immediately before the end of the intra-block scan as in the first embodiment.

The result is output to the A bus by the buffer 46 based on the data control signal C6. As a result, the upper address is updated in the address register 49. At this time, the upper address of the address register 49 is output to an image memory or the like based on the data control signal C10.

From this, a plurality of data control signals C1 to C1
It is possible to output the upper address AM (= the upper bit of the fourth bit or more) based on C18, the start address b which is an example of the external control data S0, and the detection of coincidence with the final value of the number of horizontal and vertical blocks. it can.

As described above, according to the image address generator according to the second embodiment of the present invention, as shown in FIG. 2, the X counter 27, the Y counter 28, the horizontal block number comparison output circuit 29, the vertical block A number comparison output circuit 30, a control circuit 31, and an upper address operation output circuit 32 are provided.

For this reason, the number of horizontal blocks W / 8 is the number of vertical blocks H / 8 is the first and second block count values corresponding to the scan range W × H pixels for cutting out a specific area of the target image N × M pixels. Is set in the horizontal block number comparison output circuit 29 and the vertical block number comparison output circuit 30, and when the first image address is set in the high-order address calculation output circuit 32 as the external control data S0, the X carry signal is output by the X counter 27. S1 and the lower address AL are output. Also, based on the X carry signal S1, the Y carry signal S2
Is output from the Y counter 28, and the Y carry signal S2
, A horizontal match detection signal S7 is output from the horizontal block number comparison output circuit 29.

Further, a vertical coincidence detection signal S8 is output from the vertical block number comparison output circuit 30 based on the horizontal coincidence detection signal S7, and the X carry signal S1, the Y carry signal S2,
A plurality of data control signals C1 to C18 are output from the control circuit 31 based on the horizontal coincidence detection signal S7 and the vertical coincidence detection signal S8. This allows the plurality of data control signals C1 to C
18 based on the external control data S0.
Is output from the upper address operation output circuit 32.

As a result, similarly to the first apparatus, the screen width is 2 ⁿ from the necessity of the application of the display screen, the resolution and cost of the CRT apparatus, the memory capacity and the cost, and the like.
This is the case where 2 ⁱ × an arbitrary integer (2 or more) = N pixels instead of pixels or when there is a request to perform image compression processing and transfer processing only on an arbitrary image area of the target image N × M. However, the screen width N is not limited to the screen width N = 2 ⁿ pixels as in the conventional example. This makes it possible to sufficiently cope with the request for the image compression transfer processing.

Next, an image address generating method according to a second embodiment of the present invention will be described while supplementing the operation of the apparatus.

FIG. 8 is a flowchart showing the operation of the image address generating apparatus according to the second embodiment of the present invention.

In FIG. 8, first, at step P1, a control start (START) confirmation process is performed. At this time, if the control is to be started (YES), the flow shifts to Step P2.
If the control is not to be started (NO), the control waits for a control start instruction such as a control start signal. Further, the start address b, the constant K1, the constant K2, the number of horizontal blocks W / 8 and the number of vertical blocks H / 8 are set in the respective registers via the host bus by the host CPU before control is started.

Next, in step P2, initialization processing of each circuit is performed. At this time, the counter values of the X counter 27, the Y counter 28, and the BY counter 30C are all cleared to "0".

Thereafter, at step P3, the BX counter 29C
Is cleared to "0". At this time, the BX counter 27 is controlled by the data control signals C15 and C16.

Next, in step P4, the start address b is written from the T register 47 to the address register 49.
Thus, the initialization of the processing of the first row of the block matrix is completed.

Next, at step P5, the address register 4
9 and the counter value of the X counter 27 are output as the image address a. At this time, the start address b and the X counter value are output to an image memory or the like based on the data control signal C10.

Further, at step P6, the X counter value is set to 1
Add. At this time, a constant K1 of the register 42 is output from the buffer 44A based on the data control signal C3,
It is output to the arithmetic unit 45. Also, the T register 47
Is transferred by the buffer 48B and the first internal bus (hereinafter, referred to as A bus) based on the data control signal C1, and the arithmetic unit 45 calculates a constant K1. This result is output to the C bus by the buffer 46 based on the data control signal C6.

Thereafter, in step P7, it is determined whether or not the X carry is output from the X counter 27. At this time, X
If there is a carry output (YES), step P8
To end the generation of the address of one line in the block. If there is no X carry output (NO), the process returns to step P5 and repeats steps P5 to P7.

Next, in Step P8, a constant K1 is added to the address register value and 1 is added to the Y counter value. This is processing for shifting to the next line in the block. Here, the constant K1 set in the register 42 is 1/8 of an arbitrary screen width N. Since the image address of the coordinates (x, y) in the block is a = b + x + y × N, the image address a 'of the next coordinate point (x, y + 1) is as follows.

A ′ = b + x + (y + 1) × N = a + N,
Here, N is the screen width. That is, the image address a 'of (x, y + 1) is equal to the value obtained by adding N to the image address a of (x, y). Since 1/8 of the image address a is stored in the address register 49, adding 1 to y is equivalent to adding a constant K1 = 1/8 of the screen width N to the address register 69. is there.

Next, in step P9, it is determined whether or not the Y carry is output from the Y counter 28. At this time, if there is an output of Y carry (YES), the flow shifts to Step P10 to end the processing of one block. If there is no Y carry output (NO), the process returns to step P5 and repeats steps P5 to P9.

Next, at step P10, 1 is added to the upper address of the T register 47, and 1 is added to the number of horizontal blocks of the BX counter 29B. This is a process for moving to the next block. Here, by adding 1 to the T register value, the process moves to the head of the next block. Further, adding 1 to the T register value is equivalent to adding 8 to the image address a.

Further, in step P11, it is determined whether or not the BX counter value has reached the number of horizontal blocks. At this time, if the counter value is equal to the number of horizontal blocks (YES), the process shifts to Step P12 to end one row of the block matrix. If they are not equal (NO), the process returns to Step P4 and returns to Steps P4 to P4.
Repeat P11.

Next, the routine goes to step P12, where the T register 4
The constant K2 is added to the image address a of 7 and 1 is added to the number of vertical blocks of the BY counter 30B. Immediately before the operation of Step P12 is performed, since the generation of the address of one row of the block matrix is completed, the image address a indicates the right end of the scan range as shown in FIG. Here, in order to move to the head of the next row of the block matrix, it is necessary to move +8 in the y direction and −W in the x direction. Here, assuming that coordinates before execution of step P12 are (x, y), the image address is a = b + x + y ×
N. On the other hand, the image address a 'of the next row of the block matrix is as follows.

A ′ = b + (x−W) + (y + 8) × N =
a + 8N-W, where N is the screen width.

That is, if 8N-W is added to the image address a, the block matrix moves to the head of the next row. This is because one-eighth of the image address a is held in the T register 47,
What is necessary is just to add W / 8. This N−W / 8 is set in the register 43 in advance as a constant K2.

Next, in step P12, the value of the register 43 is added to the T register value to move to the head of the next row of the block matrix.

Further, in step P13, it is determined whether or not the number of vertical blocks has reached the set value. At this time, if the number of vertical blocks has reached the set value (YES), the image address generation processing ends. If it does not become the set value (NO), the process returns to step P3 and returns to step P3.
Repeat ~ P12.

As a result, an image address a for performing block transfer processing of 8 × 8 pixels of a block image of a scan range W × H arbitrarily specified in a screen format N [arbitrary screen width] × M [lines] pixels. Can occur.

As described above, according to the image address generating method according to the second embodiment of the present invention, the start address b of the transferred image area related to the screen width N, the number of blocks in the horizontal direction =
The setting processing of W / 8 and the horizontal block = H / 8 is performed.

Therefore, similarly to the first embodiment, 8 pixels × 8 pixels
It is possible to generate an image address a for transferring a pixel having an arbitrary screen width N from a target screen N × M pixels in which eight lines of image blocks are arranged in a matrix.

As a result, it is possible to perform the image compression transfer processing of an arbitrary screen width N based on the generated image address a at a higher speed than in the first embodiment.

[0127]

As described above, according to the first image address generator of the present invention, the horizontal and vertical blocks of the image area to be extracted from the image having the size of N pixels × M lines are obtained. Since means for setting the numbers are provided, the image area is not limited to 2 ⁿ pixels × 2 ^m lines, and an image of an integral multiple of the image area of the block from an image of N pixels × M lines is used. Can be taken out. That is, in the first device of the present invention, a register for outputting the number of blocks in the horizontal direction of an arbitrary image area as a first block count value, and the number of blocks in the vertical direction as a second block count value Output register.

For this reason, when the number of horizontal and vertical blocks for cutting out a specific area of N × M pixels of the target image is set in the first and second block counting means, and the first image address is set in the data calculating means. The image address can be generated based on a plurality of data control signals and external control data. Accordingly, when the screen width becomes 2 ⁱ × an arbitrary integer (2 or more) times instead of 2 ⁿ pixels as in the conventional example, only an arbitrary image area of the target image is imaged. Even when there is a request to perform the compression process and the transfer process, the screen width is not limited to the screen width as in the conventional example.

Further, according to the second apparatus of the present invention,
First and second comparing means are provided in the second block counting means.

Therefore, when the number of horizontal and vertical blocks is set in the first and second block counting means in the same manner as in the first device, the first and second comparing means calculates the number of horizontal and vertical blocks. Compared to a number. Thus, it is possible to generate an image address faster than in the first device based on each comparison result signal. Thus, similarly to the first apparatus, it is possible to generate a block scan address without limiting the screen width to 2 ⁿ pixels as in the conventional example.

According to the image address generation method of the present invention, the start address, the number of blocks in the horizontal direction, and the number of blocks in the horizontal direction of the transfer image area are set according to the screen width.

Therefore, it is possible to generate an image address for transferring pixels of an arbitrary screen width from a target screen in which image blocks of 2 ⁱ pixels × 2 ^j lines are arranged in a matrix. This makes it possible to generate a block scan address having an arbitrary screen width.

As a result, it is possible to sufficiently cope with a demand for speeding up image compression transfer processing of an arbitrary screen width.

[Brief description of the drawings]

FIG. 1 is a principle diagram of an image address generation device according to the present invention.

FIG. 2 is a configuration diagram of an image address generation device according to a first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a control circuit according to the first example of the present invention.

FIG. 4 is an operation flowchart according to the first embodiment of the present invention.

FIG. 5 is a diagram (part 1) illustrating a relationship between an image address and a screen width according to each embodiment of the present invention.

FIG. 6 is a diagram (part 2) illustrating a relationship between an image address and a screen width according to each embodiment of the present invention.

FIG. 7 is a configuration diagram of an image address generation device according to a second embodiment of the present invention.

FIG. 8 is an operation flowchart according to the second embodiment of the present invention.

FIG. 9 is an explanatory diagram of an image address generating device according to a conventional example.

FIG. 10 is an explanatory diagram of an image address generation method according to a conventional example.

[Explanation of symbols]

 11, 12 ... first and second counting means, 13, 14 ... first and second block counting means, 13A, 14A ... first and second comparing means, 15 ... control means, 16 ... data calculation means AL: Lower address, AM: Upper address, S1, S2: First and second carry signals, S3, S4: First and second block count signals, S5, S6: First and second addresses S7, S8: first and second comparison result signals, S0: external control data, C1 to Ci: a plurality of control signals.

Claims (4)

(57) [Claims] 1. An image having a size of N pixels × M lines,
Means for extracting an image area of an arbitrary size in which blocks each having an image area of 2 ⁱ pixels × 2 ^j lines as a basic unit are collected; means for setting the number of blocks in the horizontal direction of the image area to be extracted; Means for setting the number of blocks in the vertical direction of the image area to be extracted; means for dividing the image area of any size into a plurality of blocks according to the number of blocks in the horizontal and vertical directions; Means for generating an address for discriminating the position of the block and generating an address for discriminating the position of the pixel in the block. 2. A first register for setting a start address for designating a head pixel of an arbitrary image area extracted from an image having a size of N pixels × M lines, A second register for setting the number of blocks in the direction as a first block count value; a third register for setting the number of blocks in the vertical direction of the arbitrary image area as a second block count value; First counting means for generating an address for distinguishing a horizontal position of a pixel in the block with reference to a start address set in a first register; and Second counting means for generating an address for distinguishing a vertical position of a pixel in a block; and a horizontal block based on a first block count value set in the second register. A first block counting means for counting the number of blocks; a second block counting means for counting the number of blocks in the vertical direction based on a second block count value set in the third register; Data operation means for generating an address for distinguishing the positions of a plurality of blocks based on the outputs of the first and second block counting means; and the first, second, third registers, first, second 2. The image address generating device according to claim 1, further comprising a control unit for controlling input / output of the counting unit, the first and second block counting units, and the data calculation unit. 3. The first block counting means for comparing a first block count value set in the second register with the number of blocks counted by the first counting means. Comparing means for comparing the second block count value set in the third register with the number of blocks counted by the second counting means; 3. An image address generating apparatus according to claim 1, further comprising: comparing means. 4. From an image having a size of N pixels × M lines,
An image area of an arbitrary size obtained by collecting blocks each having an image area of 2 ⁱ pixels × 2 ^j lines as a basic unit is extracted, and
An address generation method for transferring only pixels in the image area, comprising: setting processing for inputting a start address of the image area, a number of horizontal blocks and a number of vertical blocks of the image area. Performing, dividing the arbitrary image area into a plurality of blocks according to the number of the horizontal and vertical blocks based on the setting processing, generating an address for distinguishing the positions of the plurality of blocks, and An image address generating method for generating an address for distinguishing a position of a pixel in the block.