JP3008883B2 - Digital information transmitter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information transmitting apparatus, and more particularly, to a digital information transmitting apparatus for time-compressing, bit-compressing, modulating and transmitting digital information.

[0002]

2. Description of the Related Art Conventionally, an apparatus for compressing, modulating, and transmitting an information signal and receiving the transmitted signal includes, for example,
It is described in JP-A-63-28143. This publication describes a technique in which a program in a fixed time unit is broadcasted in a short time by employing a packet transmission technique, and the broadcast is expanded and reproduced in real time on a receiving side.

The Journal of the Institute of Television Engineers of Japan, Vol. 37, No. 5,
No., pages 366-374 (May 1983), a commentary article entitled "Audio Signal System for Satellite Television Broadcasting" is published. In this article, the audio signal
Compress based on the 10-bit quasi-instantaneous companding (5 range) rule,
This document describes an audio signal system of television broadcasting in which four-phase DPSK (Differential Phase Shift Keying) is transmitted and the transmission signal is received.

[0004]

However, there is no description of a digital information transmitting apparatus for time-compressing, bit-compressing, modulating, and transmitting digital information.

An object of the present invention is to provide a digital information transmitting apparatus for time-compressing, bit-compressing, modulating and transmitting digital information.

[0006]

Means for Solving the Problems In order to achieve the above object, the present invention has the following means.

Time compression means for time-compressing digital information, bit compression means for bit-compressing an output signal of the time compression means, and parity for correcting an error occurring in a transmission line in the output signal of the bit compression means. A parity signal adding unit for adding a signal, a modulating unit for modulating an output signal of the parity signal adding unit, and a transmitting unit for transmitting a modulated signal from the modulating unit to the transmission path by radio waves. With.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings.

FIG. 1 is a block diagram of a digital information transmitting apparatus according to an embodiment of the present invention.

In FIG. 1, 1 is a magnetic tape, 2 and 3 are magnetic heads, 4 is a cylinder, 5 is a capstan, 10 is a servo control circuit, 20 is a demodulation circuit, 21 is an error correction circuit, and 22 and 23 are compressions. Circuit, 130 is a control signal generation circuit, 24 is a parity addition circuit, 25 is a modulation circuit, 26 is a transmission circuit, and 27 is a transmission line.

The digital video signal and audio signal recorded on the magnetic tape 1 are reproduced by the magnetic heads 2 and 3 mounted on the cylinder 4 and input to the demodulation circuit 20. The magnetic tape 1 runs on the capstan 5. Magnetic tape 1
And the rotation frequency of the cylinder 4 are set to, for example, 10 times the normal speed. Therefore, the signal input to the demodulation circuit 20 is time-compressed ten times. For example,
If a signal for 120 minutes is recorded on the magnetic tape, it can be reproduced in 12 minutes.

Generally, when a digital signal is recorded on a magnetic recording medium, it is recorded after being modulated into a scrambled NRZ, M2 code or the like. The demodulation circuit 20 performs signal processing for returning the modulated signal to the original digital data, that is, demodulation. Demodulation circuit 20
The signal demodulated in step (1) is input to an error correction circuit 21, which detects and corrects erroneous data in a magnetic recording / reproducing process.

Also, the video signal and the audio signal are separated,
The signals are input to the compression circuits 22 and 23, respectively. The video signal is bit-compressed by a discrete cosine transform (DCT). The audio signal is bit-compressed by nonlinear quantization, differential PCM, or the like. As a result, the transmission rate of the total of the video signal and the audio signal is reduced to, for example, 1/20.

The output signals of the compression circuits 22 and 23 are input to a parity addition circuit 24. Further, a control signal from the control signal generating circuit 130 is also input to the parity adding circuit 24. Here, the control signal includes at least a control signal for controlling the operation of the printing apparatus as described later. The parity adding circuit 24 adds an error correcting parity signal for correcting an error occurring during transmission, and performs signal processing such as serially outputting a video signal and an audio signal in accordance with a transmission format. The output signal of the parity adding circuit 24 is input to the modulation circuit 25. In the modulation circuit 25, according to the characteristics of the transmission path 27 and the frequency band,
Modulates a serial signal. In this case, the transmission path 27 is a space.
Then, modulation is performed by four-phase phase modulation (QPSK). The modulated signal is input to the transmission circuit 26 and output to the transmission path 27 as a transmission signal. In this way, signals can be transmitted at a speed ten times that of a normal signal.

In the above embodiment, the case where a signal is reproduced from the VTR has been described. However, the signal source is not limited to the VTR, and may be any of a magnetic disk device and an optical disk device.

FIG. 2 is a block diagram of an embodiment of a digital information receiving and recording / reproducing apparatus including a digital information receiving apparatus. In FIG. 2, 27 is a transmission line, 30 is a receiving circuit, 3
1 is a demodulation circuit, 32 is an error correction circuit, 82 is a memory circuit, 80 is a changeover switch, 62 is a decompression circuit, and 64 is D / D
A conversion circuit, 70 is a video signal output terminal, and 131 is a control circuit.

The transmission signal transmitted from the digital information transmitting apparatus of FIG. 1 to the transmission line 27 is received by the receiving circuit 30. The received signal is input to the demodulation circuit 31.
The demodulation circuit 31 corresponds to the modulation circuit 25 in FIG. 1, and demodulates to the original signal. The demodulated signal is input to the error correction circuit 32, and based on the error correction parity signal added by the parity addition circuit 24 in FIG.
Detects and corrects the error generated in. At this time, the transmission system S
If / N is insufficient and the error cannot be corrected, correction is performed by replacing the signal using the correlation of the signal.

The error-corrected video signal output from the error correction circuit 32 is input via the memory circuit 82 to the terminal R side selected at the time of recording by the changeover switch 80. The memory circuit 82 has a memory capacity of at least one field. Video signals received at high speed are stored in the memory frame by frame, read out from the memory at a regular speed, and input to the decompression circuit 62.

The decompression circuit 62 corresponds to the compression circuit 22 of FIG. 1. In accordance with the discrete cosine transform (DCT), the compressed video signal is bit-decompressed and restored to the original video signal. You. The output signal from the D / A conversion circuit 6
4 and converted from digital to analog video signals and output from an output terminal 70.

An error-corrected control signal output from the error correction circuit 32 is detected by the control circuit 131, so that the operation of the recording apparatus, for example, the start of recording can be controlled.

In FIG. 2, 33 is a parity addition circuit, 34 is a modulation circuit, 40 is a magnetic tape, 41 and 42.
Is a magnetic head, 43 is a cylinder, 44 is a capstan,
50 is a servo control circuit, 60 is a demodulation circuit, 61 is an error correction circuit, 63 is a decompression circuit, 65 is a D / A conversion circuit, 71
Is an audio signal output terminal.

The output signal of the error correction circuit 32 is input to a parity addition circuit 33. The parity adding circuit 33 adds a parity signal for detecting and correcting an error occurring in the process of recording and reproducing. The signal to which the parity is added is input to the modulation circuit 34. In the modulation circuit 34,
Modulates to a code suitable for magnetic recording. For example,
It is a scrambled NRZ, M2 code or the like. The modulated signal is supplied to the magnetic heads 41 and 4 mounted on the cylinder 43.
2 is recorded on the magnetic tape 40.

At this time, the signal is time-compressed to 10 times the normal time axis, so that the rotation frequency of the cylinder 43 and the running speed of the magnetic tape 40 become 10 times the normal time.
The servo control circuit 50 controls the rotation of the cylinder 43 and controls the capstan 44. Further, in order to record a predetermined signal at a predetermined position of the magnetic tape 40, synchronization information is detected from the received signal, and the rotation phase of the cylinder 41 is controlled based on the synchronization information.

Next, the operation of reproducing the signal recorded in this manner will be described. At the time of the reproduction, the running speed of the magnetic tape 40 and the rotation frequency of the cylinder 43 are set to the normal reproduction. The reproduced signal is input to the demodulation circuit 60. The demodulation circuit 60 corresponds to the modulation circuit 34, and demodulates and outputs the modulated signal.
The demodulated signal is input to an error correction circuit 61, which detects and corrects an error generated in the magnetic recording / reproducing system based on a parity signal added by a parity addition circuit 33.
In addition, the video signal and the audio signal are separated and output.

The video signal is input to the expansion circuit 62 via the changeover switch 80. The decompression circuit 62 corresponds to the compression circuit 22 in FIG. 2, and the compressed video signal is restored to the original video signal by the decompression circuit 62. The output signal is input to the D / A conversion circuit 64, converted from digital to analog video signal, and output from the terminal 70.

The audio signal is input to a decompression circuit 63.
The decompression circuit 63 corresponds to the compression circuit 23 of FIG. 1, and the compressed audio signal is restored to the original audio signal by the decompression circuit 63. The output signal from the D / A conversion circuit 6
5 and is converted from a digital to an analog audio signal and output from a terminal 71.

In the embodiment shown in FIG.
The output video signal is input to the expansion circuit 62 via the memory circuit 82, but the output signal of the modulation circuit 34 may be input to the demodulation circuit 60 via the memory circuit. The demodulation circuit 60 and the error correction circuit 6
If there is room in the operation speed of the first circuit, a memory circuit may be appropriately added, or if there is room in the storage capacity of the error correction circuit 61 and the expansion circuit 62, the memory circuit may be used by using it. It may be omitted.

In the embodiment shown in FIGS. 1 and 2, a parity is added in order to detect or correct an error occurring in the transmission system or the magnetic recording / reproducing system. As an example of the method of adding parity, a magnetic recording / reproducing apparatus using the D2 format,
FIG. 3 shows the case of a two-format VTR. D2
In the format VTR, a signal of one field is divided into a plurality of segments for signal processing.
One of the segments is shown.
In FIG. 3, 90 is a video data group, 91 is an outer code parity group, and 92 is an inner code parity group. First, an outer code parity is added to the data of the video data group 90 arranged in a matrix in the figure in the vertical direction. Thereafter, the video data group 90 and the outer code parity group 9
In FIG. 1, a recording signal is generated in a form in which an inner code parity is added to data arranged in the horizontal direction. The generation of the parity is not described in detail here, but is generated according to a generator polynomial G (x).

In the embodiment shown in FIGS. 1 and 2, if the parity generating circuits 24 and 33 generate parity in the same manner, most of the error correction circuits 32 and 61 can be shared. That is, since the error correction circuits 32 and 61 are circuits used at the time of recording and at the time of reproduction, respectively,
The circuit scale can be reduced.

Although not described in the above embodiment, such a helical scan type magnetic recording / reproducing apparatus, ie, VTR
In this case, since the signal becomes discontinuous when the track is jumped during reproduction, an amble signal is added to the head of the signal and recorded. Since the addition of the amble signal is also performed in the D2 format VTR, its detailed description is omitted. Also, to determine the starting position of the signal,
Although a synchronization signal is appropriately added, a detailed description thereof is omitted, for example, since it is a known technique in a D2 format VTR.

In the embodiment shown in FIG. 1, it can be considered that the addition of the amble signal is performed by the parity adding circuit 24. Alternatively, in order to increase the use efficiency of the transmission path 27, it can be performed on the recording / reproducing apparatus side. In this case, it can be considered that the addition of the amble signal is performed by the parity adding circuit 33 in FIG. If the recording / reproducing device adds the amble signal, the use efficiency of the transmission path 27 can be increased.
If the digital signal transmission apparatus is used, the cost of the VTR can be reduced and the effect can be enhanced when signals are simultaneously transmitted to a large number of recording / reproducing apparatuses, that is, VTRs.

As an application example of the present invention, a signal can be transmitted from a digital signal transmitting apparatus to a number of recording / reproducing apparatuses, that is, VTRs, simultaneously and at high speed via a transmission line. At this time, it is difficult to control a large number of VTRs at the same time, and further, it is necessary to perform control such as recording on any VTR and not recording on any VTR. The technology for realizing such control is described below.

For this purpose, a control signal is transmitted when transmitting a digital signal to be recorded. FIG. 4 shows an example of the control signal. In FIG. 4, reference numeral 110 denotes a synchronization signal;
1 is an ID signal indicating what kind of control is performed, 112 is an address signal indicating which VTR is to be controlled,
Reference numeral 113 denotes a control signal for setting the VTR designated by the address signal 112 to the recording mode, reference numeral 114 denotes a control signal for stopping recording, reference numerals 115 and 116 denote blank signals, and reference numeral 120 denotes a signal to be actually recorded.

An address signal 11 indicating which VTR is to be recorded at a predetermined position with respect to the synchronization signal 110
2 to transmit an ID signal 111 indicating that
Put TR in standby state. When all the address signals have been transmitted, the recording of the recording signal 120 on the designated VTR can be started by transmitting the ID signal 113. After transmitting the recording signal 120, an ID signal 114 for controlling recording stop is transmitted. Signals 115 and 116
Is a blank signal, which is a signal for making the signal transmission format uniform with other parts and has no meaning.

In the embodiment shown in FIG. 1, these control signals are generated by the control signal generating circuit 130, and the parity adding circuit 24 adds a parity signal for correcting an error generated during transmission and transmits the control signal.

In the apparatus of the embodiment shown in FIG.
0, and is demodulated by a demodulation circuit 31 and an error correction circuit 32
After correcting an error occurring during use during transmission, the control circuit 131 detects a control signal and controls recording and playback of the recording / reproducing apparatus.

As described above, a large number of VTRs can be selectively and simultaneously controlled by using the present embodiment.

[0038]

As described above, according to the present invention,
Digital information can be time-compressed, bit-compressed, modulated, and transmitted.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital information transmitting apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an embodiment of a digital information receiving and recording / reproducing apparatus including a digital information receiving apparatus.

FIG. 3 is a diagram showing a conventional parity adding method.

FIG. 4 is a diagram of a control signal.

[Explanation of symbols]

 1, 2, 3, 4, 5, 10 time compression means 22 compression circuit 23 parity addition circuit 25 modulation circuit 26 transmission circuit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Keizo Nishimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Yuzumi Watani 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi, Ltd. Home Appliance Research Laboratory (72) Inventor Akira Shibata 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. Home Appliance Research Laboratory (56) References JP-A-63-175266 (JP, A) JP-A-1-114176 (JP, A) JP-A-1-276470 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/10 H04L 1/00 H04N 5/92

Claims (1)

(57) [Claims] 1. A time compression means for time-compressing digital information, a bit compression means for bit-compressing an output signal of the time compression means, and an error occurring in a transmission path in an output signal of the bit compression means. Parity signal adding means for adding the parity signal of the above, modulating means for modulating an output signal of the parity signal adding means, and transmitting the modulated signal from the modulating means toward the transmission line by radio waves. Means for transmitting digital information.