JP3006162B2 - Memory write control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write control method used for writing character pattern data to a line memory.

[0002] 1 according to the code information received from the center
When editing a page, editing is performed with the character editing unit as one line, and character extension scanning in the sub-scanning direction is performed with a bit width (bit 0).
When processing at bit 7), if the extension rate of character patterns (enlargement rate of character patterns) that occur in the same line are different,
Lines where no characters appear appear.

Therefore, it is necessary to make it possible to mix the drawing ratios in the same row without changing the peripheral circuits.

[0004]

2. Description of the Related Art FIG. 6 is a diagram showing an example of a conventional data setting circuit. FIG. 7 is an example of a configuration explanatory diagram of a conventional line memory.
FIG. 8 is an explanatory diagram of a memory state when the line memory is generated at a drawing rate of 1 (conventional), FIG. 9 is an explanatory diagram of a memory state when the line memory is generated at a drawing rate of 2 (conventional), and FIG. FIG. 4 is an explanatory diagram (conventional) of a memory state generated at a draw ratio 1 when a draw ratio 1 and a draw ratio 2 are mixed.

Hereinafter, FIGS. 6 to 10 will be described. First, in FIG. 6, LDAT 0 to LDAT 7 in the figure are character pattern data (hereinafter, referred to as “hereafter”) that has been expanded and smoothed by a preceding circuit (not shown).
When the drawing rate is 1, LDAT 0 data is input to the line memory 21.

[0006] When the drawing rate is 2, the character that has been enlarged twice is shown. When the drawing rate is 4, the data of LDAT 0 and LDAT 1 show that the character is enlarged four times. Input ~ LDAT 3 data to the line memory.

Since the address counter 11 sends the count value obtained by counting the write clock * WR to the line memory as an address, for example, the data LDAT 0 applied to the line memory 21 is written to the corresponding address. .

Note that the above address counter is also used at the time of reading, and the address at this time is applied to the line memory as a read address using the read clock from the line memory read circuit 22.

For example, when writing the character "A" in the line memory, the address of the line memory in the main scanning direction (horizontal direction) is 0000 to FFF (hexadecimal).
However, the area in which characters are written does not use all addresses in the main scanning direction, but writes in a set address area.

For example, if the start position of this area is 000,
The end position is 017 (hexadecimal), and the number of bits in the main scanning direction is
24 bits. When the scanning of the first line is completed, the address is shifted to the second line.
And sends the start address of the second line.
The address in the main scanning direction is transmitted bit by bit.

The start address of the third line is 2000,
… The start address of the 16th line is F000, and the start address of the 24th line is 17000. Also,
The line memory has eight memory portions of bit 0 to bit 7 as shown in FIG.
Since only DAT 0 data is input, only bit 0 is used. However, when the drawing rate is 2, since two data of LDAT 0 and LDAT 1 are input, bit 0 and bit 1
, And when the drawing rate is 4, bits 0 to 3 are used, respectively.

When the address counter 11 sends the above address to the line memory, the "A" pattern is written on the bit 0 surface in the line memory as shown in FIG.

In the figure, S is a pattern generation start position, + X ₅ is a position shifted by 5 bits from S, and an end position is + X ₂₃ . In addition, Y ₁ is because the start address of the second line 1000, Y ₂ is 2000 because the third line, Y ₃
The fourth line but since 3000 ·· Y ₂₃ is the 17000 because 24 line.

When the elongation rate is 2, the LDTA 0
And LDTA1 data are written to the bit 0 and bit 1 planes. As shown in FIG. 9, the "A" pattern in which the main scanning direction (horizontal direction) and the sub-scanning direction (vertical direction) are doubled Is written to the line memory.

Here, when reading the data written in bit 0 (corresponding to the decompression rate 1) or bit 0 to bit 3 (corresponding to the decompression rate 4) in the line memory, Bit 0 or bit 0 to bit 3 are read out by setting the corresponding values, and transferred to a system memory (not shown).

[0016]

However, when the character pattern of "A" generated at the deduction rate of 1 and the character pattern of "A" generated at 2 are mixed in the same line (see FIG. 5),
As described above, in the character pattern of "a" generated at the deduction rate 1, data is written only to bit 0, and no character pattern is written to bit 1.

Therefore, when the enlargement ratio is set to 2 at the time of reading, since the surfaces of bit 0 and bit 1 are alternately read, the portion of bit 1 where no character pattern is written becomes an all white line, Since only the portion is read out, the pattern becomes an alternating pattern as shown in FIG. 10, and there is a problem that character patterns having different elongation rates cannot be generated on the same line.

According to the present invention, without changing the peripheral circuit,
It is an object of the present invention to make it possible to mix the draw ratios in the same line.

[0019]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is an address counter, 2 is a line memory composed of a plurality of memory portions each having a different processing bit position added, and 3 is a character read from the memory portion of the processing bit position for which writing was previously specified. Latch means for temporarily storing pattern data.

4 shifts the input character pattern data by a predetermined amount by using the applied processing bit position signal and demagnification signal, and reads out the shifted character pattern data and the latch means. This is a memory means having a function of combining the set character pattern data and writing the data in a memory portion at a designated processing bit position this time.

Reference numeral 5 denotes an added address generated by adding the applied next address to the address output from the address counter when the next address is applied, and is read out from the memory means. An address addition / data selection means for selecting and transmitting character pattern data to be written to the addition address from the character pattern data.

Further, a memory means and an address addition / data selection means are provided, and writing is performed on the line memory by determining a write bit width corresponding to the enlargement ratio.

[0023]

According to the present invention, a pattern is written to all bits (for example, bits 0 to 7) regardless of the drawing rate (conventionally, all bits from bit 0 to bit 7 are written only when the drawing rate is 8). Use), by controlling to read at the enlargement ratio 8, even if the character pattern of the enlargement ratio 1 and the character pattern of the enlargement ratio 2 are generated on the same line, the character pattern can be written accurately. Different draw ratios can be mixed in the same direction.

[0024]

FIG. 2 is a diagram showing an example of a data setting circuit according to the present invention, FIG. 3 is a layout diagram of data to be written in a line memory according to an embodiment of the present invention, and FIG. FIG. 5 is an explanatory diagram of a memory state when the draw ratios 1 and 2 according to the present invention are mixed.

Here, the ROM 41 is a constituent part of the memory means 4, the address counter 51, the selector 52, and the selector 53 are constituent parts of the address addition / data selecting means 5, and the latch 31 is a constituent part of the latch means 3. In addition, the same reference numeral indicates the unified object throughout the drawings.

First, "LDAT 0 to LDAT 7", "*" in FIG.
"WR" is data and a write signal sent from a pre-stage expansion / smoothing circuit (not shown), "CLK" is a synchronization clock in a kanji pattern generation circuit (not shown), and "BIT0 to BIT2".
"" Is a signal for designating a processing bit position, and designates any one of bit 0 to bit 7 of the line memory as described above.

"NEXT ADRS" is a signal that is effective when there is write data up to the next line, depending on the enlargement ratio and the processing bit position. For example, 1 in FIG.
If the start position in the sub-scanning direction (vertical direction) is specified from 10 and the enlargement ratio is 4, and the data of LD0 to LD3 to be written spans the address of the next line, LD0 and LD1 are addressed. This is the address for writing LD 2 and LD 3 to address 1000 after writing to 0000.

Further, "BIT 2 to BIT 0" in FIG. 3 are signals for designating processing bit positions in the same manner as described above, and "DI 0 to D
I 7 "is the data bit of the line memory 21," LD 0 to LD 7
"(Shaded area in the figure) Line data from the enlargement / smoothing circuit not shown (same as LDAT0 to LDAT7)," RAM
0 to RAM 7 "are data read from the line memory.

The address of the ninth line is +1000 (1
Hexadecimal) The value is added. Next, the operation in the case of generating the character pattern of "A" shown in FIG. 4 (drawing ratio 1) according to the present invention will be described with reference to FIGS.

Since the drawing rate is 1, valid data among the data LDAT0 to LDAT7 input to the ROM 41 in FIG.
This data is only T 0, but this data is
(The processing bit position will be 000).

Therefore, as shown in FIG.
0 (same as LD 0 in the figure) is written to DI 0 at processing bit position “000”, address “0000”, and then the data of LD 0 is stored for 24 addresses (similar to FIG. 7, Writing (for the address in the main scanning direction) is completed, and the writing is completed.

Next, at the processing bit position "001",
The ROM is operated to write LDAT 0 to DI1 at address "0000". At this time, the processing bit position "
000 "is read from the line memory 21 and stored in the latch 31.

Then, when the next LDAT 0 is input, it is input to the ROM 41 in combination with the data of the latch 31 (denoted as RAM 0). At this time, as shown in FIG.
01 ", Address" 0000 "RAM 0 in DI 0, LD in DI 1
Perform an operation to write 0.

That is, since the data read from the same address of the line memory is written in the ROM 0 as it is, the data of the first line is not rewritten, and the data of the second and subsequent lines are rewritten.

Similarly, at the processing bit position "010", the LDAT
When the ROM is operated to write 0 to DI 2 of address "0000", the data of DI 0 and DI 1 are read from RAM 21 and stored in the latch, and input to ROM at the same time as input LDAT0. , As shown in FIG.
RAM 0 is stored in DI 0 of "010" and address "0000".
Causes RAM 1 to perform an operation such that LD 0 is written to DI 2.

By repeating this, the processing bit position in FIG.
As shown in "111", RAM0 to RAM6 are read out and stored in the latch, input to ROM 41 in combination with LDAT0 to be input, and ROM0 to ROM6 are input to DI0 to DI6, and LD0 is input to DI7. By performing an operation such that 0 is written, eight lines are completed.

As a result, as shown in the first line (S) to the eighth line in FIG. 4, a part of the character pattern of "A" is stored at the address 0000 of the memory portion of bit 0 to bit 7. You.

Hereinafter, the addresses of the RAM are represented by Y ₀ = 1000 and Y ₁ = 200.
By doing the same as above with 0
Is set. When the drawing rate is 2, the processing bit positions are four positions of 000, 010, 100, and 110.
, DI 1 to LD 1, DI 0, DI 1 at processing bit position 010
RAM 0 and RAM 1 are written to LD 2 and LD 0 and LD 1 are written to DI 2 and DI 3 respectively.

As a result, even if character patterns whose deduction rates are 1 and 2 are mixed in the same line, each pattern can be generated without any influence as shown in FIG.
When the drawing rate is 4, LD 0 to DI 3
The corresponding character pattern can be generated by writing LD 3 and writing LD 0 to LD 7 in DI 0 to DI 7 when the drawing rate is 8.

Here, the address counter 51, the selector 52
Has a function to add the address by a predetermined value when "NEXT ADRS" is applied, and to select data so that the character pattern data to be written to the line memory is continuous. It has a function to select one of them.

Further, in the reading from the line memory, if the reading rate is always set and read, all the eight memory portions from bit 0 to bit 7 can be read.
Each character pattern data is transferred to the system memory even when the ratios are mixed.

[0042]

As explained in detail above, according to the present invention, there is an effect that it is possible to realize the mixture of the drawing ratios in the same row without changing the peripheral circuit.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram illustrating an example of a data setting circuit according to the present invention.

FIG. 3 is a layout diagram of write data to a line memory according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a memory state when the data is generated at a drawing rate of 1 according to the present invention.

FIG. 5 is an explanatory diagram of a memory state when the draw ratios 1 and 2 are mixed according to the present invention.

FIG. 6 is a diagram illustrating an example of a conventional data setting circuit.

FIG. 7 is an example of a configuration explanatory diagram of a conventional line memory.

FIG. 8 is an explanatory diagram (conventional) of a memory state when a line memory is generated at a drawing rate of 1;

FIG. 9 is an explanatory diagram of a memory state when a line memory is generated at a drawing rate of 2 (conventional).

FIG. 10 is an explanatory diagram (conventional) of a memory state generated at a draw ratio 1 when a draw ratio 1 and a draw ratio 2 are mixed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Address counter 2 Line memory 3 Latch means 4 Memory means 5 Address addition and data selection means

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 5/26 G06F 12/02 G06T 1/60 G06T 9/00

Claims (1)

(57) [Claims] An address sent from an address counter (1) is used to convert input character pattern data into a plurality of memory parts, each of which is a constituent element of a line memory (2) and to which different processing bit positions are added. When writing to the memory, character pattern data read from the memory portion of the processing bit position previously specified for writing is temporarily stored in the latch means (3), and the applied processing bit position signal and the enlargement ratio Using the signal, the input character pattern data is shifted by a predetermined amount, and the shifted character pattern data and the character pattern data read from the latching means are combined, and this time, the designated processing bit position is designated. A memory means (4) having a function of writing data to a memory portion, and when a next address is applied, an The added address generated by adding the applied next address to the address is transmitted, and character pattern data written to the added address is selected from character pattern data read from the memory means and transmitted. A memory writing control method, comprising: an address addition / data selection means (5), and writing to the line memory with a write bit width determined in accordance with a drawing ratio.