JP3004764B2 - Charge-coupled device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-coupled device (hereinafter referred to as C) applied to a solid-state image sensor used for an optical sensor or the like, an analog signal processor, or the like.
CD), and particularly to a gate electrode structure in consideration of the driving method.

[0002]

2. Description of the Related Art Conventionally, as a technique relating to this kind of CCD, there has been a technique described in, for example, Japanese Patent Application Laid-Open No. 2-230770. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a sectional view of a signal charge transfer section in a CCD applied to a conventional solid-state imaging device.

This CCD is a buried channel type CCD having a two-layer electrode structure using a two-phase driving method, and has a P-type silicon substrate 1. A channel layer 2 made of an N ^- impurity layer is formed on a silicon substrate 1. A plurality of N ^- impurity layers made of N ^- impurity layers for enabling two-phase driving are formed at predetermined locations near the surface of the channel layer 2. The potential barrier layer 3 is formed.

A first gate oxide film 4 made of a silicon oxide film is formed between the potential barrier layers 3 on the surface of the channel layer 2, and a polycrystalline silicon film (polysilicon film) is formed thereon. First-layer gate electrode 5 made of
Are formed. On the potential barrier layer 3 and the first
A second gate oxide film 6 made of a silicon oxide film is formed on a part of the gate electrode 5 of the layer, and a second gate oxide film 6 made of a polysilicon film is further formed thereon. -Electrode 7 is formed.

Each of the gate electrodes 5 and 7 has a signal line 10 and 1 connected thereto.
1 are connected, and drive pulses φ1 and φ2 having phases opposite to each other are applied via the signal lines 10 and 11.

Next, the operation of FIG. 2 will be described with reference to FIG. 3 and FIG.

FIG. 3 is a diagram showing the channel potential distribution of the channel portion in the CCD shown in FIG. 2, and FIG. 4 is a diagram showing the waveforms of the driving pulses .phi.1 and .phi.2 applied to the gate electrodes for executing the charge transfer shown in FIG. .

When drive pulses φ1 and φ2 having opposite phases as shown in FIG. 4 are applied to signal lines 10 and 11,
A channel potential distribution as shown in FIG.

For example, as shown in FIG. 3, when an "L" level driving pulse φ2 and an "H" level driving pulse φ1 are applied to the gate electrodes 5 and 7, as shown by solid lines in FIG. Potential distribution. Therefore, the signal charges (electrons e ^{− in} this case) move to the higher potential. Conversely, when the drive pulse φ2 is at the “H” level and φ1 is at the “L” level, the exchange of signal charges is repeated under the adjacent gate electrodes 5 and 7, as described above.
The signal charges are sequentially transferred in one direction.

In a solid-state image pickup device such as an optical sensor using a CCD of this type, a signal processing device, and the like, higher density and higher speed are desired. For example, to achieve high resolution in a solid-state imaging device, high density and high speed are required. Similarly, in a signal processing device, high speed processing is required for high density information processing, and in addition, high density Is also required.

Taking a CCD delay element as a representative example of the signal processing element, the clock frequency _{fck of the} CCD and the CC
Between the number of bits (the number of stages) N of D and the delay time t _d , t _d
= N / f _ck . For this reason, increasing the clock frequency f _{ck in} order to increase the speed increases the number of bits of the CCD, that is, the chip area.

[0013] The conventional CCD has the following disadvantages with respect to the above required performance.

(A) Since a polysilicon film is used for the gate electrodes 5 and 7, the sheet resistance is 30 to 50Ω /.
□ and high. Therefore, a delay corresponding to the parasitic capacitance occurs in the drive pulse waveform of the CCD, and there is a limit to speeding up.

(B) When the voltages of the driving pulses φ1 and φ2 are 9 to
Since the voltage is as high as 12 V, insulation between the gate electrodes 5 and 7 and between the gate electrodes 5 and 7 and the silicon substrate 1 is maintained, and furthermore, a gate oxide film thickness of 500 to 1
It is designed as thick as 000mm. Therefore, since the MOS capacitance per unit area is small, it is necessary to increase the area of the gate electrodes 5 and 7 in order to secure the amount of charge to be handled, thereby increasing the chip area. Moreover, increasing the area of the gate electrodes 5 and 7 leads to an increase in the parasitic capacitance between the gate electrodes 5 and 7.
It also causes an increase in power consumption.

In order to solve such disadvantages (a) and (b), according to the technique of the above-mentioned document, only the gate electrode 5 of the first layer or the gate electrodes of the first and second layers are used. Electrodes 5, 7
Are made of a polycide film. This polycide film is composed of a laminated film of a silicide film of a refractory metal and a polysilicon film. Since the gate electrodes 5 and 7 having the polycide structure have a sheet resistance of about 1/10 as compared with those formed only of the polysilicon film, the speed of the CCD can be increased.

[0017]

However, the technique disclosed in the above-mentioned document in which the gate electrode is made polycide has the following problems.

(I) When the first-layer gate electrode 5 is formed of a polycide film, the second gate oxide film 6 composed of a thermal oxide film formed on a part of the polycide film is formed. Since the film quality is weak, insulation and reliability are unstable, and the second-layer gate electrode 7 cannot be superposed thereon. Furthermore, the first and second layer gate electrodes 5,
When both have a polycide structure, they are unstable in terms of insulation and reliability, and are difficult to realize.

(Ii) If only the gate electrode 7 of the second layer has a polycide structure, the problem (i) can be solved, but the following problem occurs.

That is, when the first-layer gate electrode 5 is formed of a high-resistance polysilicon film and the second-layer gate electrode 7 is formed of a low-resistance polycide film, the resistance and capacitance of the gate electrode 7 are reduced. Of the first layer and the second layer
There is a time difference between the drive pulse voltages transmitted to the gate electrodes 5 and 7. Therefore, the potential distribution under the first-layer gate electrode 5 made of high-resistance polysilicon is lower than the channel potential under the second-layer gate electrode 7 made of a low-resistance polycide film. It will take more time to become uniform within the channel.

As a result, the transfer charge in the CCD is left behind, or the transfer charge amount is reduced. In particular, this phenomenon becomes more conspicuous as the CCD is driven by a high-speed drive pulse and as the channel width is increased and the gate electrode length is increased. Therefore, even if the gate electrodes 5 and 7 are simply made of a polycide structure, it is still difficult to obtain a CCD that is sufficiently satisfactory in terms of high speed and high density.

SUMMARY OF THE INVENTION The present invention solves the problem of the prior art that it is difficult to obtain a CCD that is sufficiently satisfactory in terms of speed and density.
Is provided.

[0023]

According to the present invention, in order to solve the above-mentioned problems, a first insulating film is formed on a semiconductor substrate via a gate insulating film.
The gate electrode of the second layer and the gate electrode of the second layer are partially off.
C of two-layer electrode structure alternately arranged in a overlapping manner
In the CD, the first-layer gate electrode is formed of a polysilicon film, and the second-layer gate electrode is formed of a polycide film, which is a stacked film of polysilicon and a refractory metal. . Further, a constant DC voltage (DC) is applied to the gate electrode of the first layer, and a drive pulse voltage having a predetermined level with respect to the DC voltage is applied to the gate electrode of the second layer. To transfer signal charges.

[0024]

According to the present invention, since the CCD is constructed as described above, the polysilicon film forming the first layer gate electrode is used for insulation between the second layer gate electrodes. On the other hand, it has the function of enabling the use of a high-quality insulating film and improving the withstand voltage, leak current and reliability of the CCD. Applying a constant DC voltage to the gate electrode of the first layer is equivalent to C
It does not become a hindrance factor when operating the CD at high speed.

Further, by adjusting the DC voltage, the electric field applied between the gate electrodes is weakened, and the insulating film between the first-layer gate electrode and the second-layer gate electrode is reduced. By reducing the thickness, the capacity per unit area of the gate electrode is increased, and the density of the CCD is thereby increased. Further, the gate electrode of the second layer of the polycide structure has a function of reducing the resistance value of the gate electrode and increasing the speed of the CCD. Therefore, the above problem can be solved.

[0026]

FIG. 1 shows an embodiment of the present invention and is a cross-sectional view of a charge transfer section in an embedded CCD having a two-layer electrode structure using a two-phase driving method.

This CCD has a semiconductor substrate 21 made of a P-type silicon substrate. In the semiconductor substrate 21, a channel layer 22 made of an N ^- impurity layer forming a channel portion of the buried CCD is formed. I have. Channel layer 22
A plurality of potential barrier layers 23 made of an N ⁻ impurity layer for determining the transfer direction of signal charges are formed at predetermined positions near the surface of the semiconductor device. The potential barrier layer 23 is formed, for example, by lowering the surface concentration by implanting boron into the channel layer 22.

On a surface of the channel layer 22 adjacent to the potential barrier layer 23, a first gate insulating film 24 made of a silicon oxide film is selectively formed.
Further thereon, a first-layer gate electrode 25 made of a conductive polysilicon film containing high-concentration impurities is selectively formed.

The part on the channel layer 22 including the potential barrier layer 23 and a part on the gate electrode 25 of the first layer are:
A second gate insulating film 26 made of a silicon oxide film is selectively formed, and a second gate insulating film 26 having a polycide structure is further formed thereon.
The gate electrode 27 of the layer is selectively formed. Second
The gate electrode 27 of the layer includes a conductive polysilicon film 27a formed on the second gate insulating film 26, and a high melting point material such as tungsten or titanium formed on the polysilicon film 27a. And a metal silicide film 27b. The second gate insulating film 26 and the gate electrode 27 of the second layer are arranged to slightly overlap with the gate electrode 24 of the first layer.

From left to right in FIG. 1, the second-layer gate electrode 27, the first-layer gate electrode 25, and the second-layer gate electrode 27 have: Signal line 31 for applying drive pulse φ1, signal line 3 for applying constant DC voltage Vdc
2, and a signal line 30 for applying the drive pulse φ2 are connected to each other. The drive pulses φ1 and φ2 have two voltage levels of “H” level and “L” level. The signal lines 30, 31, 32 are formed of an aluminum film or the like.

Next, the operation of FIG. 1 will be described with reference to FIG.

FIG. 5 is a channel potential distribution diagram in a bias state under each gate electrode in FIG.

The DC voltage Vdc is applied to the first
When applied to the gate electrode 25 of the layer, a potential ψ _dc is set in the channel. With this potential ψ _dc as a boundary, as shown in FIG.
Is applied to the signal lines 31 and 30, respectively, thereby forming a step-like potential distribution capable of transferring signal charges (electrons e ^{− in} this case) in one direction.

In order to form such a potential distribution, drive pulses φ 1 and φ 2 having different phases are applied to the gate electrode 27 of the second layer. At this time, the “L” level driving pulses φ1 and φ2 are pulse voltages having a potential lower than the potential _{dc dc} , and the “H” level driving pulses φ1 and φ2 are pulse voltages having a higher potential than the potential _{dc dc.} , The gate electrode 2 of the second layer, respectively
7 is applied. Thus, the signal charges e ^- is gradually moved to the higher potential, sequentially, the signal charges e in one direction ^- the transfer is performed.

This embodiment has the following advantages.

(I) Since the first-layer gate electrode 25 is formed of a polysilicon film, the second-layer gate electrode 27 is made of, for example, a high-quality silicon oxide film for insulation from the second-layer gate electrode 27. Of the gate insulating film 26 can be formed. Therefore, withstand voltage,
The leakage current and the reliability can be improved. On the other hand, the polysilicon film used for the first-layer gate electrode 25 has a disadvantage in high-speed pulse driving because of its high resistance. However, the gate electrode 25 is supplied with a constant DC voltage Vdc. Since the voltage is always applied, the magnitude of the resistance hardly hinders high-speed driving.

(II) In the conventional CCD, the voltage applied to the second gate oxide film 6 between the first-layer gate electrode 5 and the second-layer gate electrode 7 Are the driving pulses φ1, φ
The power supply voltage is applied almost as it is between the two. This is because the driving pulses φ1 and φ2 are switched in opposite phases, and a high voltage of 9 to 12V is normally used as it is.

On the other hand, in this embodiment, the driving pulse φ1
Since the first-layer gate electrode 25 for applying the DC voltage Vdc is disposed between the gate electrode 25 and φ2, the voltage applied between the gate electrodes 25 and 27 is adjusted by adjusting the voltage of the DC voltage Vdc. Electric field can be weakened. For example, the DC voltage Vd
If c is set to 5V, even if the driving pulses φ1 and φ2 swing at 9V (Swing), they are about １ ／ of the conventional case.
The electric field is weakened. On the other hand, the first-layer gate electrode 25
Since the upper insulating film is formed of the second gate insulating film 26, there is an advantage that the insulating film can be made thinner than before. As a result, the capacitance per unit area of the gate electrode increases, thereby reducing the area of the gate electrode and reducing the capacitance.
Higher density can be achieved by downsizing and higher integration of CD.

(III) Since the gate electrode 27 of the second layer has a polycide structure, the resistance of the gate electrode 27 can be reduced to about 1/10 or less as compared with the conventional case using only polysilicon. Thus, the speed of the CCD can be increased. For example, when a CCD driving circuit or a signal processing circuit at the front and rear stages is formed on a chip as a peripheral circuit, when these circuits are configured by, for example, CMOS or NMOS,
By simultaneously using the polycide film used in the CCD for the gate electrode of each MOS transistor, not only the manufacturing process is simplified, but also the speed of the entire circuit can be increased.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications.

(A) In the above embodiment, the P-type semiconductor substrate 2
Although the buried channel type CCD formed on 1 has been described, the present invention is not limited to this. For example, the above-described embodiment can be applied to a CCD formed on an N-type semiconductor substrate such as a solid-state imaging device including a CCD. Further, not only the above-described embodiment can be applied to the surface channel type CCD, but also the semiconductor substrate 21 may be formed of a substrate other than silicon.

(B) In the above embodiment, the driving pulse φ1,
Although the two-phase driving method using φ2 has been described, the above-described embodiment can be applied to a driving method such as three-phase driving or four-phase driving.

[0043]

As described above in detail, according to the present invention, since the first layer gate electrode is formed by the polysilicon film, the insulation between the second layer gate electrode is provided. In addition, a high-quality silicon oxide film or the like can be used, thereby improving the withstand voltage, leak current, reliability, and the like. The polysilicon film forming the first layer gate electrode has a high resistance, but since a constant DC voltage is applied to the gate electrode, the magnitude of the resistance is high. Does not hinder operation.

Since the first-layer gate electrode for applying a DC voltage is arranged between the second-layer gate electrodes to which the driving pulse is applied, the voltage value of the DC voltage is adjusted. By doing so, it becomes possible to weaken the electric field applied between the gate electrodes. Therefore, the thickness of the insulating film between the first-layer gate electrode and the second-layer gate electrode can be reduced. As a result, the capacity per unit area of the gate electrode is increased, and by reducing the area of the gate electrode, it is possible to reduce the size of the CCD and increase the density by high integration.

Further, since the gate electrode of the second layer has a polycide structure, the resistance value of the gate electrode can be reduced and the speed of the CCD can be increased. In addition, in the case where the peripheral circuits of the CCD are formed on-chip, if a polycide film is also used for the gate of those circuits, the manufacturing process can be simplified and the speed of the entire circuit can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view of a charge transfer unit in a CCD showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a charge transfer unit showing a conventional CCD.

FIG. 3 is a channel potential distribution diagram of FIG.

FIG. 4 is a waveform diagram of a driving pulse in FIG. 2;

FIG. 5 is a channel potential distribution diagram of FIG. 1;

[Explanation of symbols]

 Reference Signs List 21 semiconductor substrate 22 channel layer 23 potential barrier layer 24, 26 first and second gate insulating films 25 first layer gate electrode 27 second layer gate electrode 27a polysilicon film 27b high Melting point metal silicide film 30, 31, 32 Signal line φ1, φ2 Drive pulse Vdc DC voltage

Claims (1)

(57) [Claims] 1. A gate electrode of a first layer and a gate electrode of a second layer are alternately overlapped on a semiconductor substrate with a gate insulating film interposed therebetween. In the charge coupled device having a two-layer electrode structure, the first-layer gate electrode is formed of a polycrystalline silicon film, and the second-layer gate electrode is formed of polycrystalline silicon and A constant DC voltage is applied to the first-layer gate electrode, and a drive pulse voltage of a predetermined level with respect to the DC voltage is applied to the second gate electrode. A charge-coupled device characterized in that a signal charge is transferred by being applied to a gate electrode of a layer.