JPH03184375A - Solid image-pickup element - Google Patents

Abstract

PURPOSE:To cope with high density and high-speed drive by connecting parallel alumina wirings to a first-layer polysilicon electrode layer, turning a second- layer polysilicon electrode layer into silicide, and then adjusting each resistance for setting time constant of each electrode layer to be nearly equal. CONSTITUTION:In a solid image-pickup element where a first-layer polysilicon electrode layer 12 and a second-layer polysilicon electrode layer 13 which is extended in parallel to the first-layer polysilicon electrode layer 12 are transfer electrodes, an alumina wiring 16 which is in parallel to the first-layer polysilicon electrode layer 12 is connected to it, the second-layer polysilicon electrode layer 13 is turned into silicide, and each resistance is adjusted, thus enabling time constant of each electrode layer 12 and 13 to be set to nearly the same value. Therefore, it becomes possible to reduce delay of a drive clock waveform within a CCD easily for coping with high density and high-speed drive in a solid image-pickup element favorably.

Description

[Detailed description of the invention]

[Industrial Application Field J] The present invention relates to a solid-state image sensor, and more specifically, to an improved structure of a solid-state image sensor that reduces the delay of an internal clock waveform. [Prior Art] This type of conventional solid-state imaging device (hereinafter referred to as CCD)
The pattern structure schematically representing one pixel part in the Charge Coupled Device) is shown in the fourth diagram.
Figure (a) shows the cross-sectional structure of each of the mb-mb and IHc41c lines in the same figure.
and (c). In these conventional configurations shown in FIGS. 4(a), (b), and (c), the reference numeral 1 indicates a semiconductor substrate, and 2 and 3 indicate the first and second layers (φ1 and φ2). Each of the polysilicon electrode layers 2 and 3 serves as a transfer electrode and wiring in a CCD, and each extends in the horizontal direction. 4 is the CCD channel, 5
is a photodiode that performs photoelectric conversion. Incidentally, the thickness t of the interlayer film between each of the first and second polysilicon electrode layers 2 and 3. However, due to manufacturing problems, it is difficult to make it thick. In addition, in the conventional COD with the above configuration, as is well known, the signal charge accumulated in the photodiode 5 is read out onto the channel 4, and the readout signal charge is transferred to the transfer electrode. The data are transferred through the CCD in synchronization with clock pulses that are sequentially applied to the CCD. In this conventional configuration, normally, CC
A polysilicon wiring layer 2.3 is used as a transfer electrode in D.
Therefore, when viewed from the clock supply end side, these polysilicon wiring layers 2 and 3 themselves have a large resistance. Next, FIG. 5 shows the first part of the CCD in the conventional example described above.
Each polysilicon electrode layer 2.3 of the second layer and the second layer
This shows a dimensional equivalent circuit. In the equivalent circuit shown in FIG. are the parasitic capacitances that occur in the overlapping portions of the first and second polysilicon electrode layers 2.3, and C1, j15 and C1° are the parasitic capacitances of the first and second polysilicon electrode layers 2.3, respectively. is the ground capacitance of each polysilicon electrode layer 2, 3. [Problems to be Solved by the Invention] However, with the progress of higher density and higher speed driving of this type of solid-state image sensor in recent years, each of the polysilicon layers in the first and second layers has There is an increasing demand for reducing wiring resistance and load capacitance in the electrode layer 2.3. Here, FIG. 6(a) schematically shows the imaging section of the solid-state imaging device in the conventional example described above, and FIG. 6(b) shows various positions in the same imaging section, In this case, the drive clock waveforms in the supply bottom portion A, middle portion B, and center portion C are shown respectively. In other words, in the case of this conventional configuration, as is clear from FIG. In the central portion C, a delay occurs in the drive clock waveform due to the wiring resistance and load capacitance of each of the polysilicon electrodes 2.3 in the first and second layers described above. As a guideline for this delay time τ, if R+azRma+C+a4C*a, it can be expressed as Z OCR+a·(cov+c+a). In other words, in order to increase the density of the device, each of the first and second polysilicon electrode layers 2
．． If the wiring width of No. 3 is made thinner, there is a problem that the delay time of the internal clock increases, making it impossible to support high-speed driving. This invention was made to solve these conventional problems, and its purpose is to reduce the wiring resistance of each of the first and second polysilicon electrode layers in a CCD. This makes it possible to support higher density and higher speed driving. An object of the present invention is to provide a solid-state image sensor of this type.

[Means to solve the problem]

In order to achieve the above object, the solid-state imaging device according to the present invention includes a first layer of polysilicon electrode layer and a second layer of polysilicon layer extending parallel to the first layer of polysilicon electrode layer. In a solid-state imaging device using an electrode layer as a transfer electrode, an aluminum wiring parallel to the first polysilicon electrode layer is connected to the first polysilicon electrode layer, and the second polysilicon electrode layer is silicided. The resistance value of each electrode layer is adjusted, and the time constant of each electrode layer is set to be approximately the same. [Function] Therefore, in this invention, the first polysilicon electrode layer is connected to the aluminum wiring parallel to it, and the second polysilicon electrode layer is silicided, so that each By adjusting the resistance value, the time constants of each of these electrode layers are set to be substantially the same, so that the delay of the drive clock waveform inside the COD can be reduced. (Embodiments) Hereinafter, embodiments of the solid-state image sensor according to the present invention will be described in detail with reference to FIGS. 1 to 3. FIGS. 1(a), (b), and (c) are FIG. 1 is a planar pattern configuration diagram schematically showing the outline of a pixel section in a CCD to which an embodiment of the present invention is applied; FIG. In the structure, reference numeral 11 indicates a semiconductor substrate, 12 a first layer (φl) polysilicon electrode layer, and 13 a second layer (φ2) polysilicon electrode layer silicided to reduce resistance. Each of these electrode layers 12 and 13 serves as a transfer electrode and wiring in the CCD, and each extends in the horizontal direction.
The OD channel 15 is a photodiode that performs photoelectric conversion, and 16 is an aluminum wiring arranged parallel to the first polysilicon electrode layer 12 and connected to the same electrode layer 12 through a contact hole 17. It is. In the configuration of the embodiment shown in FIG. 1, the second polysilicon electrode layer 13 is silicided to lower the resistance of its wiring. However, regarding the first polysilicon electrode layer 12, due to manufacturing problems,
It is difficult to silicide the wiring. That is, it is extremely difficult to form an insulating film only on the silicide for the first polysilicon electrode layer 12. Also, what should be noted here is that each of these electrode layers 12.
This is the wiring resistance setting in No. 13. In other words, in this case, the aluminum arrangement J in the first polysilicon electrode layer 12
116 and the second silicided polysilicon electrode layer 13 have different resistance values.
Even at the same position in D, due to the difference in the time constant,
There is a possibility that a delay may occur in the propagation time of the driving clock waveform as shown in FIGS. It is necessary to That is, in other words, when the resistance of the aluminum wiring 16 is RA and the resistance of the silicide layer is Ro. RA-(cov+c+a) RtaiCev+C*a
), it is necessary to adjust and select each parameter to satisfy the following. In order to adjust this parameter, aluminum wiring 1
It is preferable to select and set a thickness of 6, a width of 1, etc., and thereby the time constants of both can be easily matched or made to match f. In addition, in the embodiment shown in FIG. 1, only the second layer polysilicon electrode layer 13 is silicided, but in addition to this second layer silicidation, the first layer polysilicon electrode layer 12 is By siliciding the opening (12a), the resistance of the first polysilicon electrode layer 12 can be further reduced. That is, I b - I b in the embodiment of FIG. 1 in the case of this other embodiment. The cross sections corresponding to the Ic-Ic line portions are shown in Figure 2 (a
) and (b), and FIGS. 3(a) to 3(g) sequentially show the main manufacturing steps in the embodiment shown in FIG. 2. The outline of the manufacturing process shown in FIG. 3 is as follows. (a) Process The first
The third polysilicon electrode layer 12 is selectively formed. (b) Step: A second polysilicon electrode layer 12 is formed on these with an insulating film interposed therebetween. (c) Step: The second polysilicon electrode layer 12 is selectively formed, and the portion corresponding to the first polysilicon electrode layer 12 is selectively opened. (d) Step: Openings are made in the insulating film corresponding to selective openings in the second polysilicon electrode layer 12. (e) Step: The exposed portions of each of the first and second polysilicon electrode layers 12 and 13 are silicided. (f) Step: Cover these with an insulating film between the eyebrows. (g) Step: The interlayer insulating film is selectively opened, and the aluminum wiring 16 is connected to the second polysilicon electrode layer 12 through the opening. [Effects of the Invention] As detailed above, according to the present invention, the first polysilicon electrode layer and the second polysilicon electrode layer extending parallel to the first polysilicon electrode layer In a solid-state imaging device that uses a silicon electrode layer as a transfer electrode, an aluminum wiring parallel to the first polysilicon electrode layer is connected to the first polysilicon electrode layer, and the second polysilicon electrode layer is silicided. , by adjusting the respective resistance values,
Since the time constants of each of these electrode layers were set to be almost the same,
It is possible to easily reduce the delay of the driving clock waveform inside the CCD, which makes it possible to respond favorably to higher density and faster driving in this type of solid-state image sensor, and it is also structurally comparable. It has excellent features such as being simple and easy to implement.

[Brief explanation of drawings]

FIGS. 1(a), 1(b), and 1(c) are planar pattern configuration diagrams schematically showing the outline of a pixel portion in a CCD to which an embodiment of the present invention is applied, and Ib-Ib as above. A schematic cross-sectional diagram enlarged to each of the Ic-Ic line sections, 2nd
Figures (a) and (b) show the same I b- according to other embodiments.
Ib. Schematic cross-sectional diagram corresponding to each of the Ic-1c line parts, 3rd
The figures are schematic cross-sectional views sequentially showing the main manufacturing steps in the embodiment shown in Fig. 2 above, and Fig. 4(a)
and (b) and (c) are a planar pattern configuration diagram schematically showing the outline of a pixel part in a CCD in a conventional example, and a schematic cross-sectional diagram enlarged along lines IVb-IVb and IVc-IVc, respectively, Figure 5 shows the CCD in the conventional example as above.
Two-dimensional equivalent circuit diagrams of the first and second polysilicon electrode layers in FIGS. 6(a) and 6(b)
These are an explanatory diagram schematically representing an imaging section in the solid-state imaging device in the conventional example same as the above, and graphs respectively showing drive clock waveforms at respective positions in the imaging section same as the above. II... Semiconductor substrate, 12... First layer polysilicon electrode layer, 13... Second layer silicided polysilicon electrode layer, 14... Channel, 1
5...Photodiode, 16...Aluminum wiring, 17...Contact hole.

Claims (1)

[Claims] In a solid-state imaging device in which a first polysilicon electrode layer and a second polysilicon electrode layer extending parallel to the first polysilicon electrode layer are used as transfer electrodes,
An aluminum wiring parallel to the first polysilicon electrode layer is connected to the first polysilicon electrode layer, and the second polysilicon electrode layer is silicided to adjust the resistance value of each. A solid-state imaging device characterized in that the time constants of electrode layers are set to be substantially the same.