JP3004669B2 - Logic simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a logic simulator.

(Prior Art) In general, a semiconductor device is configured by a logic circuit including a large number of basic functional elements. For example, when designing a new semiconductor device, whether or not the designed logic circuit operates as expected is performed. Are simulated in advance by a logic simulator. Conventionally, such a logic simulator has been configured by software using a general-purpose computer or the like.

In order to speed up the logic simulation in such a logic simulator, Japanese Patent Laid-Open No.
No. 52, JP-A-63-257841, and the like propose a logic simulator in which a part of the software of the logic simulator as described above is replaced with hardware.

(Problems to be Solved by the Invention) However, in recent years, semiconductor devices tend to be highly integrated, and accordingly, logic circuits to be simulated by a logic simulator also tend to be large-scale and complicated. For this reason, even in a logic simulator in which a part of the conventional software described above is replaced with hardware, simulation may require several hours or tens of hours, and it is required to speed up the logic simulation. I have.

In general, in a semiconductor device manufacturing process,
Each semiconductor device is inspected for good or bad in the state of a semiconductor wafer using a wafer prober and a tester. At this time, a test signal (test pattern) supplied to the semiconductor device from the tester to determine good or bad. ) Needs to be set in advance so that any defect (failure) of the semiconductor device can be determined efficiently.

When creating such a test pattern, a logic simulator may be conventionally used to determine the failure detection rate of the test pattern.If the failure detection rate of such a test pattern is determined using a conventional logic simulator, However, there is a problem that it takes a long time because the simulation needs to be repeated many times.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional situation, and an object thereof is to provide a logic simulator capable of performing simulation on a logic circuit and determining a failure detection rate of a test pattern at a higher speed as compared with the related art. is there.

[Structure of the Invention] (Means for Solving the Problems) That is, the invention of claim 1 is a logic simulator for simulating the operation of a logic circuit composed of a large number of cells and a large number of nets connecting these cells. A plurality of RAMs storing at least data relating to the configuration of the logic circuit input from the input / output device, data relating to a test pattern for testing the operation of the logic circuit, and a simulation result; and A simulation chip that simulates the state of the logic circuit in a self-running manner, and the simulation chip generates information on the type of the event of the simulation input signal and the name of the net where the event has occurred. The test vectors described in chronological order are stored in the RAM. From the test wheel, and a newly generated event is written between these test vectors in the order of the time of occurrence, and the time of occurrence of the next event is indicated by a pointer. An accumulator unit that sequentially reads the event information and executes a simulation in each net; and a function that receives a simulation result from the accumulator unit, determines an event occurrence state in each logical block, and outputs a determination result. Comprising a logic unit, the accumulator unit, the logic value of at least one of the nets constituting the logic circuit,
It is characterized in that it is configured so that it can be fixedly transferred to the function logic unit regardless of the logical value of the net and a failure occurrence state can be simulated.

According to a second aspect of the present invention, in the logic simulator according to the first aspect, in the time wheel unit, the pointer chains are reconnected by updating the pointers as necessary.

(Operation) In the logic simulator of the present invention, at least data on the configuration of a logic circuit to be simulated, data on a test pattern for testing the operation of the logic circuit, and a plurality of RAMs storing simulation results are stored. Based on the response, the simulation chip simulates the state of the simulated logic circuit by self-running.

Therefore, the simulation can be executed at high speed by self-propelled operation (calculation processing in the simulation chip) without responding to the general-purpose computer during the simulation.

Further, the simulation chip is configured so that the logic value of at least one of the nets constituting the logic circuit is fixed and the failure occurrence state can be simulated.

Therefore, for example, as shown in FIG.
One of the logical values of each of the nets 111 to 117 connected to 03 is fixed (stacked at 1 or 0 regardless of the output logical value), and a simulation is performed in a failure occurrence state by a predetermined test pattern. It can be checked whether failure detection is possible. At this time, if the effect of fixing the logical value appears on the simulation result, it indicates that fault detection is possible with the test pattern.If the effect of fixing the logical value is not on the simulation result, fault detection is not performed. Shows what is possible. Then, by sequentially changing the nets 111 to 117 for fixing the theoretical values and repeatedly performing the simulation, the failure detection rate of the test pattern can be determined in a shorter time than in the past.

Embodiment Hereinafter, a logic simulator according to one embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, a logic simulator of this embodiment includes a simulation chip 1 composed of hardware formed on one chip, a data storage unit 2 composed of, for example, a plurality of RAMs, An engineering work station (hereinafter, referred to as EWS) 3 as an apparatus constitutes a main part thereof.

The simulation chip 1 includes a time wheel unit (hereinafter, TWU) 11, an accumulator unit (hereinafter, ACU) 12, a function logic unit (hereinafter, FWU).
DU) 13.

On the other hand, the data storage unit 2 includes a condition state memory (hereinafter, referred to as COM) 21, a test vector memory (hereinafter, referred to as TVM) 22, a time wheel memory (hereinafter, referred to as T).
WM) 23, event table memory (hereinafter ETM) 24, net information memory (hereafter NI)
M) 25, result storage memory (RSM) 2
6, a cell specification memory (hereinafter referred to as CSM) 27, a net signal state memory (hereinafter referred to as STM) 28, and the like.

The simulation chip 1 and the data storage unit 2
It is connected via an external bus (external data bus, external address bus) 4.

The TWU 11, ACU 12, and FDU 13 in the logic unit 1 are connected via an internal bus (internal data bus, internal address bus) 14.

Further, of the plurality of memories, only the STM 28 is connected to the ACU 12 via a dedicated state bus (state data bus, state address bus) 30.

The data required for the simulation is input by the EWS3, transferred to the data storage unit 2, and taken into the simulation chip 1 as necessary. Necessary data is stored.

The data necessary for the simulation include data related to the configuration of the logic, that is, net information data related to the connection state of each cell (logic element), cell specification data related to the specification of each cell, and test vectors related to the input signal for the simulation. However, these are pre-EW
It is written from S3 into TVM22, NIM25, CSM27.

The test vector stored in the TVM 22 describes, for example, the type of a change (hereinafter, referred to as an event) such as rising or falling of an input signal, and information on a net name where the event has occurred, in the order of occurrence time. Further, each event is provided with an event gate flag indicating the order of occurrence of the event.

As shown in FIG. 4, the net information data stored in the NIM 25 includes, for example, a net next-stage memory (hereinafter referred to as NNM) 25a indicating which cell the output-side net of a certain cell is connected to, and an extended net. The next-stage memory (hereinafter referred to as ENNM) 25b, the pre-net memory (hereinafter referred to as NBM) 25c which indicates which net is connected to the input side of a certain cell, and the extended net pre-stage memory (hereinafter referred to as ENBM) 25d are shown. ing. Also,
This net information data includes information on the cell type (for example, whether it is an AND gate or an OR gate) and information on the fan-out (load capacity) of the cell. The cell specification data stored in the CSM 27 indicates the performance required to calculate a delay time due to a fan-out and a timing error such as a hold time and a setup time of each cell.

Next, regarding the configuration and operation of the logic unit 1 composed of hardware formed on one chip, TWU11, A
CU12 and FDU13 will be described in this order.

 The TWU 11 is configured, for example, as shown in FIG.

In the TWU 11, the test vectors written in the TVM 22 from the EWS 3 are sequentially read, expanded to the TWM 23 and the ETM 24, and a newly generated event is written between these test vectors in the order of the occurrence time.

That is, the TWM 23 is a memory for managing an event, has an address in absolute time, and stores, as data, an event value (pointer) in the ETM 24 which stores event-related data such as an event occurrence net name and an event value. The event occurrence time (TWM address: pointer) and the like are stored. The ETM 24 has, as data, an occurrence net name and an event value of an event that has occurred at a certain time, and further has an ETM address value (pointer) in which another event data that has occurred at the same time is stored.

The data bus register 40 of the TWU 11 is a bidirectional register that connects an internal bus and an external bus. Further, the comparator logic 41 determines whether or not the event occurs at the same time.
Determines whether a newly generated event or an event that has been loaded disconnects the pointer (whether it is necessary to reconnect the chain of pointers), or whether memory writing is not prohibited. The addition logic 43 calculates the absolute time of a newly generated event from the current absolute time and the delay value.

In addition, the TVM counter 44 sets the test vector of the TVM 22 to TW
For loading into M23, the TWM counter 45 is
The ETM counter 46 calculates the absolute time serving as the address of the TWM23,
Indicates the address of ETM24.

A before event register (hereinafter, referred to as a BE register) 47 indicates data of the TWM 23 at the current time. The next event register (hereinafter referred to as the NE register) 48 is the TVM2
Stores and processes data loaded from step 2 and newly generated event data.

The TWU control logic 49 controls the operation of the TWU 11.

 Next, the operation of the TWU 11 will be described.

First, the TWU 11 loads, into the TWM 23, a test vector for performing a simulation accommodated in the TVM 22.
(However, only the time range indicated by TWM23 is loaded.)

In the above operation, if there is an event that occurs at the same time, the net name and event value of the event are written to the ETM 24, and the address of the ETM 24 is written as a pointer of the TWM 23. This operation is performed using the BE register 47 and the NE register 48. If the loaded event exceeds the previously loaded event and it is necessary to update the pointer indicating the next occurrence time of the TWM 23 (reconnect the pointer chain), the pointer is updated.

When the loading of the test vector from the TVM 22 to the TWM 23 is completed as described above, the events are sequentially received in response to the event read request signal (ACU request) from the ACU 12.
Read from WM23 to ACU12.

When the data is transmitted, the right to use the external bus 4 is transferred to the ACU 12, and the TWU 11 is in a standby state until a newly generated event write request signal coming from the FDU 13 or an ACU request from the ACU 12 comes.

Then, when the ACU request comes, the event is sequentially read from the TWM 23 to the ACU 12 again.

When an event write request signal is generated from the FDU 13, the net name, event value and delay value of the newly generated event are sent to the internal data bus 14. After latching this data in the data bus register 40, the TWU 11 calculates the absolute time of the newly generated event from the current absolute time and the delay value in the adder logic 43 and writes the calculated absolute time in the TWM 23. At this time, if it is necessary to update the pointer indicating the next event occurrence time of the TWM 23 (reconnect the pointer chain), the pointer is updated.

Thereafter, if there is still an event in the TWM 23, the event is read from the TWM 23 to the ACU 12 as described above, and the same processing is performed. If no event exists in the TWM 23, a test vector in the next time range is loaded from the TVM 22 to the TWM 23, and the above processing is repeated. Then, all the test vectors for performing the simulation in the TVM 22 are loaded and processed, and if all the events generated thereby are processed, the operation is terminated.

In the example shown in FIG. 3, SRAM is used as each memory. However, when DRAM is used, it is necessary to add a DRAM controller circuit.

 Next, the ACU 12 will be described with reference to FIG.

In ACU12, first, ACU control logic 60 starts ACU
A request is issued, and the event data output on the internal bus in synchronization with the TW acknowledge signal from TWU11 is
Latch into register 61. Upon receiving the TW acknowledge signal, the ACU 12 obtains the occupation right of the external bus 4, latches the event data, and sets the event read request signal to "L" to enter the internal operation.

Then, the STM 28 is accessed with the event net name (address) latched in the IBUS register 61, and the current state (theoretical value) of the net where the event has occurred and the event gate flag are stored in the status register 62.

Thereafter, the event gate flag from the TWU 11 stored in the IBUS register 61 and the event gate flag from the STM 28 stored in the status register 62 are
By performing a comparison operation in the LU 63, it is determined whether the current event is a valid event, an invalid event, or an uncertain event and has to be replaced with the logical value “E”.

If it is determined in the above determination that the current event is invalid, the event gate flag of the IBUS register 61 is written to the STM 28 in preparation for the calculation of the event data from the next TWU 11, and the processing of the current event ends. .

On the other hand, if it is determined in the above determination that the current event is valid or indefinite, the event gate flag of the IBUS register 61 is written to the STM 28, and then the contents of the current event are written and left in the RSM 26 via the data selector 64. At this time, the address at which the current event is written is sequentially incremented from “0000” to “FFFF” by the RSM write address counter 65.

Note that the simulation result is once TWM23 or EWM
It is written to TM24, read from these memories after the delay time, becomes a past event only after checking the event gate flag, and is written to RSM26.

Next, the ACU 12 enters a task of finding an output change (next-stage event) of the next-stage cell caused by the current event.

First, the NNM 25a in the NIM 25 is identified by the net name (address) at which the event occurred,
And stores the net name (address), cell type, and fan-out in which the next event may occur in the NN register 66. Here, if there are two or more nets where the next-stage event may occur, only the pointers connecting the next-stage net addresses are read for the second and subsequent nets, and after processing the first next-stage net, The next next net is sequentially read out by the pointer and processed.

Next, the NBM 25c in the NIM 25 is accessed by the address of the next-stage net stored in the NN register 66, the address of the input net that affects the next-stage net, and its input pin code (clock, clear, data enable,
Load) is stored in the NB register 67. When there are two or more addresses of the input net, as in the case of the next-stage net, the input is read out one by one using the pointer. Further, by parallel processing, the STM 28 is accessed based on the address of the next-stage net stored in the NN register 66, and the current state (theoretical value) of the next-stage net and the event gate flag are stored in the status register 62.

Thereafter, the STM 28 is accessed using the address of the input net stored in the NB register 67, and the current state (logical value) of the input net is stored in the status register 62. Also,
The ENBM 25d is accessed by a pointer connecting the address of the input net stored in the NB register 67, and the address of another input net is stored in the NB register 67. And
The information on the next stage net, input net, pin code, cell type, fan-out, etc. stored in the status register 62, the NN register 66, and the NB register 67 is transferred from the data selector 68 to the internal bus 14 every time the status register 62 is rewritten. Transfer to the input register of FDU13 via

When all the information has been transferred to the FDU 13, the ACU control logic 60 issues an ACU continue or an ACU request to pass the occupation right of the external bus 4 to the FDU 13.

That is, when there are a plurality of next-stage nets, an ACU continuation signal is output and the processing of the FDU 13 and the TWU 11 is waited for, and if there is a TW acknowledge, the above process is repeated for the next next-stage net. If there is no next net, the NN register 66, NB register 67, and status register 62 are all cleared, and the next current event is cleared.
It is output from the TWU 11 onto the internal bus 14, issues an ACU request and waits until a TW acknowledgment is received.

As described above, for example, as shown in FIG. 2, one of the logical values of the nets 111 to 117 connected to the cells 101 to 103 is fixed (stacked at 1 or 0 regardless of the output logical value). In the case of performing a simulation with a predetermined test pattern and checking whether or not the effect of fixing the logical value on the simulation result is possible, and determining the failure detection rate of the test pattern, among the processing in the ACU 12 described above, Regarding the net whose logical value is to be fixed when the logical value of the net is read from the STM 28, a fixed logical value (1 or 0) is stored in the status register 62 regardless of the logical value read from the STM 28, and this fixed The logical value thus set is transferred to the input register of FDU13.

Therefore, the simulation in this case is a simulation of a fault state in which a net having a fixed logical value is connected to, for example, a power supply or a ground.

 Next, the FDU 13 will be described with reference to FIG.

First, the FDU 13 latches the data transferred from the ACU 12 as described above. Then, in each logic block, the output logic value is determined from the input terminal logic value, and the output logic value of the designated cell is selected based on the cell type data.

Next, the selected output logic value is compared with the current output logic value to determine occurrence of an event (presence or absence of a change). When the output is determined by input data other than the event pin (the pin where the event has occurred), it is determined that no event has occurred.

If no event has occurred, a signal indicating that no event has occurred is sent to the internal bus 14 and the processing of the FDU 13 ends.

On the other hand, if an event occurs, the current output logical value
From the output logic value selected above, the rising edge of the event /
Judgment of falling change, create CSM27 address based on cell type, input pin name, output pin name, calculate delay time from data input from CSM27 and fan-out data, net address, presence / absence of event Are sent to the internal bus 14 together with the logical value, and the processing of the FDU 13 ends.

Thus, the state of the simulated logic based on the event that has occurred at a certain time is simulated. And such, TWU11, ACU
12. By repeating the processing by the FDU 13, the temporal change of the simulated logic according to the test vector in the TVM 22 is sequentially simulated without responding to the EWS 3 during the simulation.

That is, in the logic simulator of this embodiment, all the logic parts other than the memory are formed as hardware on one chip, and the simulation can be performed by this hardware alone.

Therefore, there is no need for the hardware part (simulation chip 1) and the software part (EWS3) to respond during the simulation as in the conventional logic simulator. For this reason, the time required for such a response can be eliminated, and the simulation speed can be significantly increased as compared with the related art.

In addition, since one of the logical values of each net is fixed and the net having the fixed logical value can be simulated assuming a failure state connected to, for example, a power supply or a ground, the net for which the logical value is fixed can be used. By repeating such a simulation repeatedly for all nets by sequentially changing, it is possible to judge the failure detection rate of the test pattern in a short time. At this time, the simulation result is sequentially compared with the expected value. If it is found that the simulation result is different from the expected value and the failure can be detected, the simulation (failure simulation) for the net is stopped at that time, and the next If the logic value of the net is fixed and simulation (fault simulation) is performed on the net, the failure detection rate of the test pattern can be determined in a shorter time.

In the above embodiment, the TWU 11 and the ACU 12
And an example in which the FDU 13 is provided, it is not always necessary to provide them on one chip.
Alternatively, it may be provided on three to three chips separately. With such a configuration, it is easy to change the configuration of each unit, but the simulation speed is slightly slower than when it is provided on one chip.

[Effects of the Invention] As described above, according to the logic simulator of the present invention, the simulation speed can be significantly increased as compared with the related art.

Further, for example, by sequentially fixing the logical value of one of the nets constituting the logic circuit and repeatedly performing the simulation, the failure detection rate of the test pattern can be determined in a shorter time than before. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing the overall configuration of a logic simulator according to one embodiment of the present invention, FIG. 2 is a diagram for explaining a method of determining a failure detection rate of a test pattern, and FIG. 3 is a logic diagram of FIG. FIG. 4 is a diagram showing a configuration of a time wheel unit of the simulator, FIG. 4 is a diagram showing a configuration of an accumulator unit of the logic simulator of FIG. 1, and FIG. 5 is a diagram showing a configuration of a function logic unit of the logic simulator of FIG. is there. 1 simulation chip 2 data storage unit (RAM) 3 engineering work station (input / output device) 4 external bus 11 time wheel unit 12 accumulator unit 13 ... Function logic part, 14 ... Internal bus, 21 ... Condition state memory, 22 ... Test vector memory, 23
…… Time wheel memory, 24 …… Event table memory, 25 …… Net information memory,
26 …… Result storage memory, 27… Cell spec memory, 28… Net signal state memory, 30… State bus.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-90152 (JP, A) JP-A-54-75251 (JP, A) JP-A-63-278150 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 17/50

Claims (2)

(57) [Claims] 1. A logic simulator for simulating the operation of a logic circuit comprising a large number of cells and a large number of nets connecting these cells, wherein at least the configuration of the logic circuit inputted from an input / output device And a plurality of RAMs for storing data relating to test patterns for testing the operation of the logic circuit, and a plurality of RAMs for storing simulation results. The simulation chip sequentially reads, from the RAM, test vectors in which information on the type of event of a simulation input signal and the name of the net in which the event has occurred are described in order of occurrence time, And newly generated An event is written between these test vectors in the order of occurrence time, and information of the event is sequentially read from the time wheel unit where the occurrence time of the next event is indicated by a pointer. An accumulator unit for executing a simulation; and a function logic unit for receiving a simulation result from the accumulator unit, determining an occurrence state of an event in each logic block, and outputting a determination result.The accumulator unit includes the logic circuit. Wherein the logic value of at least one of the nets constituting the net is fixedly transferred to the function logic unit regardless of the logic value of the net, and a failure occurrence state is simulated. Logical stain Regulator. 2. The logic simulator according to claim 1, wherein the time wheel unit reconnects the pointer chain by updating the pointer as needed.