JP2995979B2 - LSI manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving the yield of LSIs by performing inspection and correction in the course of a wiring process in an LSI having a multilayer wiring structure, and an LSI manufactured by this method.
About.

[0002]

2. Description of the Related Art In an LSI development process, a completed LSI is used to debug a logic design defect or a circuit operation defect.
"On-chip wiring correction technology" that cuts and connects a part of the wiring on the chip is effective. This technique is disclosed in Hiroshi Yamaguchi et al .: Device repair method and device (Japanese Patent Laid-Open No. 59-1686).
52), Hiroshi Yamaguchi et al .: Methods and apparatus for connecting IC wiring (JP-A-62-229956). In a known wiring correction method, a focused ion beam (FIB: Focused Ion) is formed on the surface of a completed LSI.
The wiring is cut by processing a fine hole about the width of the wiring by Beam, etc., or a connection hole is formed in the wiring by FIB, and then the wiring is directly drawn on the surface of the LSI by laser CVD or FIB-CVD. , Had to connect the wiring.

As shown in FIG. 9, for example, it takes many days to re-manufacture a three-layer wiring LSI for wiring correction, as shown in FIG. ) Can be corrected in a very short time. This effect increases as the number of wiring layers increases, for example, to five.

[0004]

As shown in FIG. 9, as the number of wiring layers increases, the effect of on-chip wiring correction increases. However, in recent years, the number of wiring layers of an LSI tends to further increase. Further, since the number of circuits and functions in one LSI increases, the chip size of the LSI tends to increase.

[0005] For this reason, in the conventional wiring correction performed from the surface of the LSI, (1) the depth from the chip surface to the lower wiring layer becomes large, so that a hole is formed in the lower wiring and a metal is formed in the connection hole. Embedding becomes difficult. (2) It becomes difficult to find a gap that can be modified to the lower wiring due to the upper wiring running many layers above the lower wiring. There is a problem.

In addition, since an LSI having many circuits and functions has a large chip size, there is a disadvantage that (3) after completion of the LSI process, the yield is poor and the correction becomes large-scale.

[0007]

In order to achieve the above object, the wiring is corrected using a focused ion beam or laser CVD before all the wiring steps are completed, and then the remaining wiring steps are performed. Is what you do.

[0008]

The wiring can be corrected in the middle of the wiring process without any problem in the process. However, when the remaining wiring layers are further formed after the correction, it is necessary to bury the interlayer film in the cut holes by FIB. For this, a local insulating film is formed by laser CVD or FIB-CVD. In some cases, it is necessary to make a connection to a wiring layer that is at least one distance away from the wiring layer created after the correction. For this,
Drilled by focused ion beam processing.

As a result, the normal wiring forming process and FI
A wiring repair process using B, laser CVD, or the like can be performed without any problem.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a four-layer wiring L made according to the present invention.
FIG. 3 is a cross-sectional view of a wiring layer portion of an SI. FIGS. 2 to 8 sequentially show the process of producing the LSI shown in FIG.

FIG. 2 shows a first wiring layer 2, an interlayer insulating layer 3, a second wiring layer 4, an interlayer insulating layer 5, a third wiring layer 6, an interlayer insulating layer on a diffusion layer 1 formed on a silicon substrate. 7 shows a cross section of the LSI wiring layer at the stage of manufacturing up to 7. This element is designed so that an electrical test can be performed when the third wiring layer is completed. The element has several test openings 8, and the electrical test is performed using these openings. As a result, it is possible to find a logic design defect or a circuit operation defect, and perform necessary wiring correction.

The wiring correction at the stage up to FIG. 2 will be described below. As shown in FIG. 3, the cutting of the third-layer wiring 6 is performed by drilling 9 by focused ion beam processing (FIB processing) as shown in the prior art. Further, a connection hole between the second layer wiring 4 and the third layer wiring 6 is formed by FIB processing, and laser CVD (or FI
Metals 10 and 11 are buried by B-CVD) or the like, and are connected by a metal wiring 12 by laser CVD or the like. Next, production of the fourth wiring layer is started. Before this,
It is necessary to insulate the third layer wiring 6 exposed on the inner surface of the cut hole 9 formed by the FIB processing, the wirings 10, 11, 12 formed by laser CVD or the like, and the third wiring layer 8 exposed on the test opening. The cutting hole 9 is not limited to cutting the third wiring layer as shown in FIG. 3, but may be a hole for cutting a deeper wiring layer. Therefore, there is a possibility that the insulation may not be sufficiently provided to the inside of the hole in the ordinary formation of the insulating film. Therefore, as shown in FIG. 4, an insulator (SiO ₂ or the like) 13 is formed only in the inside of the hole by laser CVD or the like. Thereafter, as shown in FIG. 5, an interlayer insulating film 14 is formed on the entire surface of the wafer by a normal film forming method such as sputtering.

Next, as shown in FIG. 6, a resist 15 is applied, and a connection hole 16 for the third wiring layer is formed by a photoresist step and dry etching. Here, as a result of the previous electrical test, there may be a case where a correction is required to make a connection between the fourth wiring layer and the lower wiring layer. In this case, if the mask for patterning the interlayer insulating layer 14 is modified, the manufacturing period of the LSI is extended. Even if connection between the fourth wiring layer and the second wiring layer is necessary, it is difficult to form a connection hole in the second wiring layer in a dry etching step for forming a connection hole in the third wiring layer.

After removing the resist, as shown in FIG. 7, for example, a connection hole 17 for the second wiring layer is formed in the FIB.
Performed by processing. The embedding of the metal in the connection hole is deeper than the connection hole 16 and is therefore difficult by ordinary sputtering film formation or CVD. Therefore, as shown in FIG.
A film filling film 18 for filling this hole is formed by the above method.

Thereafter, as shown in FIG. 1, the fourth wiring layer 19 is formed.
Is formed by sputtering film formation or the like. Pattern this,
Thereafter, a protective film 20 is formed.

In this embodiment, first, the first to third layer wirings (N = 3) are formed, and then tested and corrected, and then only the four-layer wirings are formed (M = 1) to complete the four-layer wirings. (N +
M = 4). N and M are not limited to this, and 6 and 6 in FIG.
As shown in the example of the layer wiring, first, a lower four-layer wiring is formed (N
= 4), and after performing on-chip wiring correction, an upper two-layer wiring (M = 2) can be formed to complete a six-layer wiring (N + M = 6).

FIG. 10 shows an application example of the present invention. The large chip 20 includes element chips 21 to 24. Each element chip is composed of N-layer wiring and has a power supply and signal I / O so that an electrical test can be performed independently. After the test / correction of each element chip is completed, power supply and signal wiring between the element chips are performed by M-layer wiring. As a result, a large-sized chip having a total of (M + N) layers can be manufactured with high yield. FIG. 11 shows a cross section of FIG. A dummy N is provided between the element chips 21 and 22.
There is a layer wiring section 25 so that an M layer wiring between element chips can be formed on a flat base.

FIG. 12 is an enlarged view of the large chip of FIG. 10 up to the wafer scale, which is well known as WSI (wafer scale integration).
The present invention is effective for this as well, after testing and correcting the function of each element chip to ensure it,
It is possible to integrate.

In this embodiment, the description is limited to FIB processing, but the present invention is not limited to this. FIB assisted etching, laser processing, laser etching,
Energy beam processing such as B processing and EB assist etching can be used. In this embodiment, the laser CV
Expressions such as D were used, which included FIB-CVD, E
Includes energy beam deposition such as B-CVD.

[0021]

According to the present invention, as shown in the example of the six-layer wiring in FIG. 9, although the number of days for forming the upper two layers is not reduced,
A sufficiently large total number of days can be obtained.
In FIG. 9, the method of the present invention in which the remaining upper layer wiring is manufactured after the on-chip wiring correction is referred to as in-chip wiring correction.

Further, according to the present invention, high-yield production of a large chip LSI or a wafer scale LSI having many functions can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of an LSI showing an embodiment of the present invention.

FIG. 2 is an LSI sectional view illustrating a method of the present invention.

FIG. 3 is a sectional view of the same LSI.

FIG. 4 is a sectional view of the same LSI.

FIG. 5 is a sectional view of the same LSI.

FIG. 6 is a sectional view of the same LSI.

FIG. 7 is a sectional view of the same LSI.

FIG. 8 is a sectional view of the same LSI.

FIG. 9 is a diagram showing the effects of the prior art and the present invention.

FIG. 10 is a conceptual diagram of a large chip including a plurality of element chips.

FIG. 11 is a sectional view of FIG. 10;

FIG. 12 is a conceptual diagram of a wafer scale circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Diffusion layer, 2,4,6,19 ... First, second, third and fourth wiring layers, 3,5,7,14 ... Interlayer insulating layer, 8 ... Electrical test opening, 9 ... FIB Wiring cut holes, 10, 11, 18: Filled metal by laser CVD etc., 12: Wiring by laser CVD, etc., 13: Filled insulator by laser CVD, etc., 15: Resist, 16: Connection holes by dry etching, 17: FIB Connection hole, 20 ... protective film, 21-24 ... element chip, 25 ... dummy wiring layer.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/66

Claims (4)

(57) [Claims] A wiring pattern formed on a semiconductor wafer substrate;
A structure in which an interlayer insulating film covering the line pattern is sequentially laminated
In the manufacturing process of the LSI having the multilayer wiring structure of
Inspect and correct wiring patterns covered with the interlayer insulating film
Is detected, and the detected wiring pattern is detected.
The area requiring correction is locally processed from above the interlayer insulating film.
And locally apply the insulating film to the corrected location.
Before including the portion where the insulating film is locally formed.
A method for manufacturing an LSI, comprising forming a new wiring pattern on the interlayer insulating film . 2. A wiring pattern and a wiring pattern on a semiconductor wafer substrate.
A structure in which an interlayer insulating film covering the line pattern is sequentially laminated
In the manufacturing process of the LSI having the multilayer wiring structure of
Inspect and correct wiring patterns covered with the interlayer insulating film
Is detected, and the detected wiring pattern is detected.
Focused on the interlayer insulating film at the location requiring correction
Irradiating an ion beam to the interlayer insulating film and the
A part requiring correction of the wiring pattern is removed and the part is removed.
An insulating film is locally formed on the processed part by laser CVD.
The interlayer including the region where the insulating film is locally formed.
The feature is that a new wiring pattern is formed on the insulating film
Method of manufacturing the LSI to be. 3. A wiring pattern and a wiring pattern on a semiconductor wafer substrate.
A structure in which an interlayer insulating film covering the line pattern is sequentially laminated
In the manufacturing process of the LSI having the multilayer wiring structure of
Inspect and correct wiring patterns covered with the interlayer insulating film
Is detected, and the detected wiring pattern is detected.
Focused on the interlayer insulating film at the location requiring correction
Irradiating an ion beam to remove a part of the interlayer insulating film;
Cutting the wiring pattern that needs to be corrected below
Then, the cut wiring pattern and another wiring pattern
Is formed locally, and the local
An interlayer insulating film in the area including the area where the wiring film is formed
Then, a new wiring pattern is formed on the formed interlayer insulating film.
A method for manufacturing an LSI. 4. An interlayer insulation formed on a semiconductor wafer substrate.
The electrical defect of the wiring pattern covered with the film is detected in the interlayer.
Detecting through an opening formed in the insulating film;
Correct the electrically defective portion of the wiring pattern, and
The upper layer wiring pattern and the upper layer wiring pattern
Characterized by forming an insulating film covering the layer wiring pattern
LSI manufacturing method .