JP2995905B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having wiring electrodes formed by plating.

[0002]

2. Description of the Related Art In recent years, higher integration of large scale integrated circuits has been demanded, and emphasis has been placed on miniaturization. As a result, wiring resistance is high and contact holes (or through holes)
Has a problem that the wiring electrode is easily broken. In order to solve these problems, a low-resistance material such as Au is used as a wiring material, and a wiring electrode is formed by a plating method, so that electrical connection is ensured even in a contact hole (or through hole) having a relatively high aspect ratio. The connection was made, and the flatness over the contact hole (or through hole) could be improved.

A conventional method for manufacturing a wiring electrode will be described with reference to the drawings. FIG. 3 is a longitudinal sectional view in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

First, an insulating film 13 is formed on a semiconductor substrate 11, and a first contact hole is formed in a predetermined region. In order to form a fine and shallow diffusion layer, an impurity-added polycrystalline silicon film 15 is formed in a region covering the first contact hole, and the diffusion layer 12 is formed using this as a diffusion source. The polycrystalline silicon film 15 is used as a lead electrode.
Thereafter, in order to reduce the contact resistance between the polycrystalline silicon film 15 and the wiring electrode, the silicide layer 16 is
Form on the surface. Subsequently, a silicon oxide film is grown on the entire surface as the insulating film 14 to a thickness of about 200 to 500 nm by a CVD method or the like. After that, the second reaching the silicide layer 16
3 is opened in the insulating film 14 [FIG.
(A)].

Next, over the entire surface including the second contact hole,
A plurality of metal films 21 and 22 which serve as plating electrodes and serve as a barrier metal between the polycrystalline silicon film 15 (or diffusion layer) which is a lead electrode and the wiring electrode material, and have good adhesion to the silicide layer 16 are formed. [Fig. 3
(B)]. These metal films are formed by a sputtering method.
-Pt, TiW-Pt, TiW-Pd, Ti-Pd and the like can be considered. In this case, it is not always necessary to form a multi-layer film, and a single-layer film may be used. However, when a single-layer film is used, the single-layer film needs to function as a barrier metal, and is formed of a material such as Pt and Pd. In any case, the metal film in contact with the wiring electrode is formed of a barrier metal.

Next, a photoresist film 19 having an opening including the second contact hole is formed [FIG.
(C)]. Subsequently, using the photoresist film 19 as a mask, the wiring electrodes 20 are formed by an electrolytic plating method such as Au.
Is formed (FIG. 3D).

Next, the photoresist film 19 is removed.
Subsequently, using the wiring electrode 20 as a mask, the metal film 22 and the metal film 21 are sequentially removed by reactive ion etching (RIE) using an Ar-based gas [FIG. 3 (e)].

[0008]

According to the above-described conventional method for manufacturing a semiconductor device, it is very difficult to remove a metal film (eg, Pt, Pd) serving as a barrier metal by wet etching. By etching. In this case, etching is performed using the wiring electrode as a mask, and it is very difficult to obtain a selective ratio of etching between the barrier metal layer and the wiring electrode.
Since the wiring electrodes are simultaneously etched, there is a disadvantage that it is difficult to control the film thickness of the wiring electrodes when the semiconductor device is formed.

In addition, since the barrier metal is formed by the sputtering method, as the contact hole becomes finer, the barrier metal is not formed more uniformly, and there is a disadvantage that heat resistance and the like are deteriorated.

[0010]

According to a method of manufacturing a semiconductor device of the present invention, a semiconductor element region formed on a semiconductor substrate is provided.
Alternatively, in a method for manufacturing a semiconductor device having a wiring electrode connected to a lead electrode region of the semiconductor element region through a contact hole provided in an insulating film through a barrier metal layer, the insulating film is formed over the entire surface; This insulating film
An electrode layer for plating is formed on the entire upper surface, and the electrode layers for plating are arranged.
Forming the above-mentioned contact hole penetrating through the insulating film
And a first opening in a region including the contact hole.
Forming a first photoresist film having
Electroless plating using the first photoresist film as a mask
The semiconductor element region or the semiconductor element region
Connecting the extraction electrode area to the plating electrode layer
Selectively forming the barrier metal layer;
After removing the first photoresist film, the first opening
A second opening having a second opening in a required area including
Forming a photoresist film;
The above burr is formed by electrolytic plating using a dist film as a mask.
Selectively over the metal layer and the plating electrode layer
Forming a wiring electrode, and forming the second photoresist
After removing the film, use the wiring electrodes as a mask to
Etching the key electrode layer .

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view in the order of steps for explaining the related art of the present invention.

First, a silicon oxide film, a silicon nitride film, or the like having a predetermined thickness is formed as an insulating film 13 on a semiconductor substrate 11, and a first contact hole is formed in a predetermined region. Deposit a polycrystalline silicon film on the entire surface, add impurities to it,
An impurity-added polycrystalline silicon film 15 is formed in a region covering the first contact hole by photolithography. In order to form a fine and shallow diffusion layer, the diffusion layer 12 is formed by performing a heat treatment using the polycrystalline silicon film 15 as a diffusion source. The polycrystalline silicon film 15 is used as a lead electrode. Thereafter, a silicide layer 16 is formed on the surface of the polycrystalline silicon film 15 in order to reduce the contact resistance between the polycrystalline silicon film 15 and the wiring electrode. Subsequently, a silicon oxide film is grown on the entire surface as the insulating film 14 to a thickness of about 200 to 500 nm by a CVD method or the like. Thereafter, a second contact hole reaching the silicide layer 16 is opened in the insulating film 14 (FIG. 1A). Up to this stage, it is the same as the conventional method of manufacturing a semiconductor device.

Next, over the entire surface including the second contact hole,
A metal film 17 serving as an electrode for electrolytic plating is formed by a sputtering method or the like (FIG. 1B). The thickness of the metal film 17 is 100
About 300 nm. The metal film 17 is made of, for example, Ti
It is made of a metal such as W or Ti which can be easily removed by wet etching.

Next, a photoresist film 19 having an opening including the second contact hole is formed, and a metal film 18 is selectively formed on the exposed surface of the metal film 17 using the photoresist film 19 as a mask. [FIG. 1 (c)]. The thickness of the metal film 18 is about 100 to 200 nm. Metal film 1
The method of forming 8 is an electrolytic plating method or an electroless plating method, and either method may be used. The metal film 18 functions as a barrier metal between the polycrystalline silicon film 15 (or diffusion layer) as a lead electrode and a wiring electrode formed in a later step, and is made of, for example, Pt, Pd, Ni, or the like.

Next, the wiring electrode 20 is formed of Au by an electrolytic plating method (FIG. 1D). The film thickness of the wiring electrode 20 is about 0.6 to 2.0 μm.

Next, after removing the photoresist film 19, the exposed portion of the metal film 17 is removed by wet etching [FIG. 1 (e)]. The wet etching of the metal film 17 is performed with a hydrogen peroxide solution when the metal film 17 is made of TiW, and with dilute hydrofluoric acid when the metal film 17 is made of Ti.

When a sputtering method is used to form a barrier metal by a conventional method, for example, when Pt of about 100 nm is formed, a portion having a thickness of about 30 nm is formed at the bottom of the contact hole. In the case of Pt, the film thickness is 30n
m, heat treatment at 450 ° C for 30 minutes causes leakage,
Heat resistance sharply decreases. On the other hand, in this related technique , since the barrier metal is formed by plating, the film thickness is secured even at the bottom of the contact hole, and the heat resistance is 480 ° C. or higher. Therefore, when the semiconductor device is mounted, the semiconductor device can sufficiently withstand a heat treatment at about 450 ° C. for sealing glass, for example.

FIG. 2 is a longitudinal sectional view in the order of steps for explaining an embodiment of the present invention.

First, a silicon oxide film, a silicon nitride film, or the like having a predetermined thickness is formed as an insulating film 13 on a semiconductor substrate 11, and a first contact hole is formed in a predetermined region. Deposit a polycrystalline silicon film on the entire surface, add impurities to it,
An impurity-added polycrystalline silicon film 15 is formed in a region covering the first contact hole by photolithography. In order to form a fine and shallow diffusion layer, the diffusion layer 12 is formed by performing a heat treatment using the polycrystalline silicon film 15 as a diffusion source. The polycrystalline silicon film 15 is used as a lead electrode. Thereafter, a silicide layer 16 is formed on the surface of the polycrystalline silicon film 15 in order to reduce the contact resistance between the polycrystalline silicon film 15 and the wiring electrode. Subsequently, a silicon oxide film is grown on the entire surface as the insulating film 14 to a thickness of about 200 to 500 nm by a CVD method or the like [FIG.
(A)].

Next, a metal film 23 serving as an electrode for electrolytic plating is formed on the entire surface by a sputtering method or the like. The thickness of the metal film 23 is about 100 to 300 nm. The metal film 23 is made of a metal such as TiW or Ti that can be easily removed by wet etching. Thereafter, a photoresist film 25 for opening a second contact hole is formed (FIG. 2B).

Next, using the photoresist film 25 as a mask, the metal film 23 and the insulating film 14 are sequentially etched to form a second contact hole and expose the silicide layer 16 at the bottom thereof [FIG. (C)]. When the metal film 23 is etched by wet etching, when the metal film 23 is made of TiW, hydrogen peroxide is used, and when the metal film 23 is made of Ti, dilute hydrofluoric acid is used. When etching the metal film 23 by RIE, an Ar-based gas is used. Also,
The etching of the insulating film 14 is CF ₄ -based RIE.

Next, the metal film 24 is formed by electroless plating.
Is formed (FIG. 2D). The thickness of the metal film 24 is 10
It is about 0 to 300 nm. The metal film 24 functions as a barrier metal. The metal film 24 is connected to the metal film 23 and becomes a part of the electrode for electrolytic plating. Therefore, the metal film 24 is made of Pt, Pd, Ni, or the like. Since this metal film becomes a part of the electrode for electrolytic plating, it is necessary to form the metal film on the side wall of the insulating film 14 in the second contact hole, and an activator such as Pd is used before the electroless plating. Pretreatment is desirable. As the activator, Red Schumer of Nippon Kanigen and the like are known.

Next, after removing the photoresist film 25, a photoresist film 19 having an opening including the second contact hole is formed. Subsequently, the wiring electrode 20 is formed of Au by an electrolytic plating method (FIG. 2E). The film thickness of the wiring electrode 20 is about 0.6 to 2.0 μm.

Next, after removing the photoresist film 19, the exposed portion of the metal film 23 is removed by wet etching in the same manner as in the related art [FIG. 2 (f)].

In the present embodiment, the reason why the thickness of the metal film formed by electroless plating is set to about 100 to 300 nm is that the selectivity of plating is reduced by increasing the plating time and the plating time. That's why.

As the barrier metal, in addition to those described above, Co, Cr, Mn, Rh, Ru, Ir, Re and the like can be considered. Among these, Co and Rh can be used for electroless plating.

In this embodiment, since the barrier metal is formed in the contact hole by the electroless plating method, the embedding of the barrier metal in the contact hole becomes more reliable, heat resistance and the like are improved, and more stable. A semiconductor device can be provided.

[0028]

As described above, according to the present invention, since the barrier metal layer is formed only in a predetermined region by the plating method, even if the contact hole becomes fine, the contact hole can be formed with good uniformity. Deterioration can be prevented.

Further, the metal film used as the plating electrode can be easily wet-etched, and a material having a sufficient selectivity can be selected at the time of etching using the wiring electrode as a mask. This can obtain the wiring electrode.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view for explaining a related technique of the present invention.

FIG. 2 is a longitudinal sectional view for explaining one embodiment of the present invention.

FIG. 3 is a longitudinal sectional view illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 11 semiconductor substrate 12 diffusion layer 13, 14 insulating film 15 polycrystalline silicon film 16 silicide layer 17, 18, 21, 22, 23, 24 metal film 19, 25 photoresist film 20 wiring electrode

Claims (1)

(57) [Claims] 1. A semiconductor device region formed on a semiconductor substrate or a lead electrode region of the semiconductor device region,
In a method of manufacturing a semiconductor device having a wiring electrode connected via a barrier metal layer through a contact hole provided in an insulating film, the insulating film is formed on the entire surface, and plating is performed on the entire surface of the insulating film.
Forming an electrode layer and penetrating the plating electrode layer and the insulating film;
Forming the contact hole passing therethrough, and having a first opening in a region including the contact hole.
Forming a first photoresist film, and an electroless mask using the first photoresist film as a mask.
The semiconductor device region or the semiconductor device region
Contact between the extraction electrode region of the region and the plating electrode layer.
Selectively forming the subsequent barrier metal layer, removing the first photoresist film, and removing the first opening
A second opening having a second opening in a required region including the portion
Forming a photoresist film and electrolytic plating using the second photoresist film as a mask
The barrier metal layer and the plating electrode
Selectively forming the wiring electrode on the layer, and removing the second photoresist film,
Etching removal of the plating electrode layer using the pole as a mask
And a method of manufacturing a semiconductor device.