JPH05129445A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH05129445A
JPH05129445A JP28778091A JP28778091A JPH05129445A JP H05129445 A JPH05129445 A JP H05129445A JP 28778091 A JP28778091 A JP 28778091A JP 28778091 A JP28778091 A JP 28778091A JP H05129445 A JPH05129445 A JP H05129445A
Authority
JP
Japan
Prior art keywords
hole
semiconductor
metal wiring
wiring
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28778091A
Other languages
Japanese (ja)
Inventor
Yukio Morozumi
幸男 両角
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, セイコーエプソン株式会社 filed Critical Seiko Epson Corp
Priority to JP28778091A priority Critical patent/JPH05129445A/en
Publication of JPH05129445A publication Critical patent/JPH05129445A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To practically manufacture and stably supply a fine semiconductor device excellent in characteristics, yield, and reliability, by a method wherein, after conducting material for through hole burying use is grown, a desired amount of the material is etched back, and the conducting material is again etched by using a patterned metal wiring as a mask. CONSTITUTION:After an interlayer insulating film 104 is grown on a first metal wiring 103 on the surface of an Si substrate 101 and a through hole is formed, W 104 is subjected to vapor growth on the whole surface, via TiN turning to an adhesion layer 105. By etch back, W is left in the through hole, and left as residue 110 in a level-difference part like a space of the first metal wiring 103. After a second metal wiring 107 is patterned, the exposed residue 110 is etched by using the wiring 107 as a mask. Thereby flatness and throwing power of the through hole and the metal wiring itself are improved, so that electric characteristics and long term reliability of quality are improved, and semiconductor devices of high quality and high level of integration can be stably supplied.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置及びその製造
方法に関し、特に微細化された層間配線の接続技術に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technique for connecting miniaturized interlayer wiring.

【0002】[0002]

【従来の技術】一般に半導体装置の配線技術に於いては
多層構造の配線が用いられ、例えばSi基板の不純物
層,不純物がドーピングされたPolySiや金属ある
いはこれらの合金等でなる第1の配線層上にシリコン酸
化膜等の層間絶縁膜を介在させ、これらの層間絶縁膜に
形成された接続孔(スルーホール)を介して、上層のA
l合金等の金属でなる第2の配線層へ接続をとってい
る。微細化が進みスルーホールがハーフミクロン程度に
なるとアスペクト比の増大により配線材の接続孔への付
き回りが厳しくなり、ホール抵抗やマイグレーション等
半導体装置の特性や信頼性を決める重要な因子となり、
よって改善策として、気相法によるPolySi,W
(タングステン)やそのシリサイドをスルーホールに埋
め込む方法が提案されている。この様な半導体装置の従
来の構造,製造方法を図3で説明する。
2. Description of the Related Art Generally, in a wiring technique of a semiconductor device, a wiring having a multi-layer structure is used. For example, an impurity layer of a Si substrate, a first wiring layer made of impurity-doped PolySi, a metal, or an alloy thereof is used. An interlayer insulating film such as a silicon oxide film is interposed on the upper layer, and an upper layer A is formed through a connection hole (through hole) formed in these interlayer insulating films.
Connection is made to the second wiring layer made of a metal such as an l-alloy. As miniaturization progresses and the through hole becomes about half micron, the increase in aspect ratio makes it difficult to keep the wiring material in contact with the connection hole, which is an important factor that determines the characteristics and reliability of the semiconductor device such as hole resistance and migration.
Therefore, as an improvement measure, PolySi, W by the vapor phase method is used.
A method of burying (tungsten) or its silicide in a through hole has been proposed. A conventional structure and manufacturing method of such a semiconductor device will be described with reference to FIG.

【0003】例えばAl2層配線構造のCMOS−LS
Iは、トランジスタや抵抗等の半導体素子が作り込まれ
たSi基板101上の選択酸化や気相成長によるシリコ
ン酸化膜によるフィールド絶縁膜102を介在させて、
Al合金等でなる第1の金属配線103を施す。次に層
間絶縁膜104として300〜450℃程度の気相反応
で厚みが約600nmのシリコン酸化膜を成長させ、ス
ルーホールを開孔後、密着層105としてスパッタや気
相法で薄いTiNやTiWを成長させてから、450℃
前後の温度でW106を全面に800nm程度減圧気相
成長させる(図3(a))。次にSF6 やCl2 にAr
やHeを添加したドライエッチャーでエッチバックを行
なうが、気相成長させたW106の膜厚相当分を単純に
エッチバックしたのでは、第1の金属配線103のスペ
ース等の段差にも密着層105やコンフォーマルに付き
回るW106が残渣110として残ってしまう(図3
(b))。この残渣110は除去しないと、この上に形
成される第2の金属配線の横方向が電気的に短絡してし
まう。そこでW106の膜厚ばらつきやエッチバックす
る装置のエッチ速度の均一性も考慮して、密着層を含め
た残渣110がなくなる様に50%前後のオーバーエッ
チングをする。その後Al合金をスパッタし第2の金属
配線107を施して(図3(c))、更にプラズマシリ
コン窒化膜等のパッシベーション膜を気相成長させ、最
後に外部への電極取り出しの為にボンディングパッド部
を開孔している。
For example, a CMOS-LS having an Al two-layer wiring structure
I is a field insulating film 102 made of a silicon oxide film formed by selective oxidation or vapor phase growth on a Si substrate 101 in which semiconductor elements such as transistors and resistors are formed,
First metal wiring 103 made of Al alloy or the like is applied. Next, as the interlayer insulating film 104, a silicon oxide film having a thickness of about 600 nm is grown by a gas phase reaction at about 300 to 450 ° C., a through hole is opened, and then an adhesion layer 105 is formed by thin TiN or TiW by sputtering or a gas phase method. 450 ℃ after growing
W106 is vacuum-deposited on the entire surface at a temperature of about 800 nm under reduced pressure (FIG. 3A). Then SF6 and Cl2 with Ar
Etching back is performed by a dry etcher containing He or He. However, if the film thickness of the vapor-grown W106 is simply etched back, the adhesion layer 105 can be formed even on a step such as a space of the first metal wiring 103. And W106 that conformally conforms remain as a residue 110 (FIG. 3).
(B)). If this residue 110 is not removed, the lateral direction of the second metal wiring formed thereon will be electrically short-circuited. Therefore, in consideration of the variation in the film thickness of W106 and the uniformity of the etching rate of the apparatus for etching back, over-etching of about 50% is performed so that the residue 110 including the adhesion layer is eliminated. After that, an Al alloy is sputtered to form a second metal wiring 107 (FIG. 3C), a passivation film such as a plasma silicon nitride film is further vapor-phase grown, and finally, a bonding pad for taking out an electrode to the outside. The part is opened.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
製造方法に於いては、気相法によって全面成長したW1
06をエッチバックしてスルーホールに埋め込む形に
し、第1の金属配線103と第2の金属配線107との
接続を確実にしようとするものであるが、W106のエ
ッチバックの際の長いオーバーエッチングにより、スル
ーホール内部のW106は減り、層間絶縁膜104の表
面より下がってしまう。特にエッチバックで平坦部のW
106がなくなる段階になると、ホール領域と段差部に
だけW106が残る形になりエッチ速度が急激に増し、
スルーホール内に均一にW106を残す制御は非常に困
難となる。この結果、スルーホール領域で第2の金属配
線107の付き回りが悪く、初期歩留りの低さだけでな
く、ホール抵抗の増大やエレクトロマイグレーションに
よる断線等の信頼性問題が多く、実用化と量産安定供給
を行なう上での弊害となっていた。このことは、Al合
金を用いた2層配線間のスルーホールの問題に限られ
ず、Si基板の不純物層あるいPolySiやシリサイ
ドを含むゲート電極等から、コンタクトホール内の埋め
込み導電材を介してAl合金等で引き出し配線を行なう
場合にも同様な問題があった。
However, in the conventional manufacturing method, W1 grown entirely by the vapor phase method is used.
Although 06 is etched back so as to be embedded in the through hole to ensure the connection between the first metal wiring 103 and the second metal wiring 107, long over-etching at the time of W106 etch back is performed. As a result, W106 inside the through hole is reduced and falls below the surface of the interlayer insulating film 104. Especially for etch back W
At the stage where 106 disappears, W106 remains only in the hole region and the step portion, and the etching rate sharply increases.
It is very difficult to control the W106 to be uniformly left in the through hole. As a result, the second metal wiring 107 does not adhere well in the through-hole region, and not only the initial yield is low, but there are many reliability problems such as an increase in hole resistance and disconnection due to electromigration. It was a hindrance to supply. This is not limited to the problem of the through hole between the two-layer wiring using the Al alloy, but it is possible to use the impurity layer of the Si substrate, the gate electrode containing PolySi or silicide, or the like through the embedded conductive material in the contact hole to form the Al. The same problem occurs when the lead wiring is made of an alloy or the like.

【0005】しかるに本発明は係る問題点を解決するも
ので、スルーホールの埋め込み用導電材を成長し該導電
材の所望量をエッチバックした後に、金属配線をパター
ニングしてから、該金属配線をマスクとして再び導電材
をエッチングすることにより、デバイス特性,歩留りや
信頼性の高い微細半導体装置の実用化と安定供給を目的
とするものである。
However, the present invention solves the above problems by growing a conductive material for filling a through hole, etching back a desired amount of the conductive material, patterning the metal wiring, and then removing the metal wiring. By etching the conductive material again as a mask, it is intended for practical use and stable supply of a fine semiconductor device having high device characteristics, yield and reliability.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体素子等が形成された基板上に、少なく
とも、層間絶縁膜を形成する工程、該絶縁膜に電気的接
続を取る為の接続孔を形成する工程、下層半導体素子の
導電層もしくは金属等でなる第1の配線層と電気的接続
を行なう為の導電材を全面に成長する工程、該導電材の
所望厚みをエッチバックする工程、第2の配線層を成長
しパターニングする工程、該第2の配線層をマスクにし
て露出した導電材をエッチングする工程を具備したを特
徴とする。 又本発明の半導体装置は、第1の配線層
と、接続孔にエッチバックによって埋め込まれた導電材
を介して第2の配線層に電気的接続がなされる多層配線
構造を有する半導体装置に於いて、接続孔領域以外の第
2の配線層の下にも、該導電材を構成する少なくとも一
部材が残されていることを特徴とする。
According to the method of manufacturing a semiconductor device of the present invention, at least a step of forming an interlayer insulating film on a substrate on which a semiconductor element or the like is formed, and an electrical connection is made to the insulating film. , A step of forming a connection hole, a step of growing a conductive material for electrically connecting to the conductive layer of the lower semiconductor element or the first wiring layer made of metal or the like, and etching back the desired thickness of the conductive material. And the step of growing and patterning the second wiring layer, and the step of etching the exposed conductive material using the second wiring layer as a mask. Further, the semiconductor device of the present invention is a semiconductor device having a first wiring layer and a multilayer wiring structure in which electrical connection is made to the second wiring layer through a conductive material embedded in the connection hole by etching back. In addition, at least one member forming the conductive material is left under the second wiring layer other than the connection hole region.

【0007】[0007]

【実施例】図1は、本発明に係わる半導体装置の一実施
例をについて説明する為の工程概略断面図であり、Al
2層配線構造のSiゲートMOS−LSIに適用した場
合に於いて、MOSトランジスタや抵抗等の半導体素子
が形成されたシリコン基板101上の選択酸化や気相成
長によるシリコン酸化膜によるフィールド絶縁膜102
を介在させて、5%のCuを含むAl合金500nmと
反射防止膜108となるTiNを50nmスッパタで積
層させてから、Cl2とBCl3ガスを用いたエレクトロ
ン−サイクロトロン共鳴型(ECR)エッチャーで該積
層膜を選択エッチングし第1の金属配線103とした。
この反射防止膜108は、Al合金自身やこの上に開け
られスルーホールのフォトリソのハレーション防止の為
に用いた。次に層間絶縁膜104としてSi(OC2H
5)とO2を約4O0℃程度で気相反応させた約600n
m厚みのシリコン酸化膜を成長させ、0.5μm角の大
きさのスルーホールを開孔後、密着層105としてTi
Nを約60nm成長した後に、WF6 とH2 ,SiH4
等を主ガスとして減圧気相法でW106がスルーホール
も埋められる様に約800nmを全面成長した。(図1
(a))。次にSF6 とArガスを導入し高周波200
W,0.2torrの条件で、Wの異方性エッチバック
を行なった。この時、ドライエッチャーのプラズマ発光
終点検出を確認しオーバーエッチングは5%とした。
又、密着層のTiN105はエッチングしないで残した
ままでも良い。この結果、スルーホール表面では、層間
絶縁膜104表面とほぼ同じ高さにWの106表面が位
置し、スルーホール内に埋もれた形で残っている。又第
1の金属配線103のスペース領域や段差部にもW10
6や密着層105が残渣110として残っている(図1
(b))。続いて、Cuを含んだAl合金を800nm
の厚みで、更に反射防止膜109としてTiNを50n
mスパッタ成長後、ECRエッチャーを用い、Cl2と
BCl3ガス等を用い、反射防止膜109とAl合金を
圧力0.15torrで選択エッチングし第2の金属配
線107としてパターニング後、更に第2の金属配線1
07をマスクとしてSF6とArガスを用い0.2To
rrで、該金属配線107間に露出しているW106の
残渣110と、更にC2F6とO2ガスも添加して密着層
15のTiNを選択的にエッチングして除去した(図1
(c))。第2図は、こうした工程を経た半導体装置の
平面概略図で、例えば第1の金属配線103の特定スペ
ース領域とクロスする第2の金属配線107の下側に
は、Wの残渣110が残されている。111はスルーホ
ールである。その後、パッシベーション膜としてシリコ
ン酸化膜とプラズマシリコン窒化膜を気相成長させ、最
後に外部への電極取り出しの為にボンディングパッド部
を開孔した。この様にしてなる本発明の半導体装置は、
スルーホール部の第2の金属配線107の被覆性が改善
され、埋め込みW106との接続はほぼ平面的に行なわ
れる様になり、又第1の金属配線103のスペースや下
層のゲート電極等も含めた段差部の厳しいルール領域の
第2の金属配線の下には、TiNやWの残渣110が埋
め込まれた形となり第2の金属配線107自身の平坦性
も改善され、よって初期的にホール抵抗が低く、経時的
にはエレクトロマイグレーション等が発生しないもので
あり、初期歩留りや信頼性を高めることが出来た。又こ
の他、第2の金属配線のAl合金をスパッタする前に、
20nmのTiと50nmのTiN及びTiと50nm
のTiWを積層し、同じ工程を経たものも試作したが、
いずれもスルーホールのW106と第2の金属配線10
7間のホール抵抗を更に低下させることが出来た。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic sectional view of a process for explaining an embodiment of a semiconductor device according to the present invention.
When applied to a Si gate MOS-LSI having a two-layer wiring structure, a field insulating film 102 made of a silicon oxide film by selective oxidation or vapor phase growth on a silicon substrate 101 on which semiconductor elements such as MOS transistors and resistors are formed.
500 nm of an Al alloy containing 5% Cu and TiN to be the antireflection film 108 are laminated with a 50 nm spatter, and then the lamination is performed with an electron-cyclotron resonance (ECR) etcher using Cl2 and BCl3 gas. The film was selectively etched to form the first metal wiring 103.
The antireflection film 108 was used for preventing the halation of the photolithography of the Al alloy itself or the through holes formed on the Al alloy. Next, as the interlayer insulating film 104, Si (OC2H
5) and O2 were reacted at about 400 ℃ in the gas phase at about 600n
After a silicon oxide film having a thickness of m is grown and a through hole having a size of 0.5 μm square is formed, Ti is used as an adhesion layer 105.
After growing about 60 nm of N, WF6, H2, and SiH4
Using the above as the main gas, W106 was entirely grown to a thickness of about 800 nm by the reduced pressure vapor phase method so that the through holes were also filled. (Fig. 1
(A)). Next, SF6 and Ar gas were introduced to the high frequency 200
Anisotropic etch back of W was performed under the conditions of W and 0.2 torr. At this time, the detection of the plasma emission end point of the dry etcher was confirmed, and the overetching was set to 5%.
Further, the TiN 105 of the adhesion layer may be left without being etched. As a result, on the surface of the through hole, the W 106 surface is located at substantially the same height as the surface of the interlayer insulating film 104, and remains in the form buried in the through hole. In addition, W10 is also formed in the space area and the step portion of the first metal wiring 103.
6 and the adhesion layer 105 remain as a residue 110 (see FIG. 1).
(B)). Subsequently, the Al alloy containing Cu is 800 nm.
With a thickness of 50 n
After the sputter growth, the antireflection film 109 and the Al alloy are selectively etched at a pressure of 0.15 torr using an ECR etcher and Cl2 and BCl3 gas, etc., and patterned as the second metal wiring 107, and then the second metal wiring is further formed. 1
0.2To using SF6 and Ar gas with 07 as a mask
At rr, the residue 110 of W106 exposed between the metal wirings 107 and C2F6 and O2 gas are also added to selectively remove TiN of the adhesion layer 15 (see FIG. 1).
(C)). FIG. 2 is a schematic plan view of a semiconductor device that has undergone such steps. For example, a W residue 110 is left below the second metal wiring 107 that crosses a specific space region of the first metal wiring 103. ing. 111 is a through hole. After that, a silicon oxide film and a plasma silicon nitride film were vapor-phase grown as a passivation film, and finally a bonding pad portion was opened for taking out an electrode to the outside. The semiconductor device of the present invention thus configured is
The coverage of the second metal wiring 107 in the through-hole portion is improved, the connection with the embedded W106 is made almost flat, and the space of the first metal wiring 103 and the lower-layer gate electrode are included. The residue 110 of TiN or W is buried under the second metal wiring in the strict rule region of the step portion, and the flatness of the second metal wiring 107 itself is also improved. Is low, electromigration does not occur over time, and the initial yield and reliability could be improved. In addition, before sputtering the Al alloy of the second metal wiring,
20nm Ti and 50nm TiN and Ti and 50nm
We made a prototype by stacking the TiW of
In both cases, the through hole W106 and the second metal wiring 10
It was possible to further reduce the hole resistance between 7 and 7.

【0008】尚、本発明は実施例で示したAl2層配線
構造の半導体装置の他に、Si基板の不純物層や、Po
lySiあるいは高融点金属のシリサイドを用いたゲー
ト配線等から、気相成長したWやPolySiあるいは
WSi2をエッチバックして形成した埋め込み導電材を
介して、Al等の金属配線を引き出す場合にも適用が出
来るものである。又、残渣110のエッチングの際、第
2の金属配線107上のフォトレジストの有無やドライ
エッチャーがECRであることにも限定されず、一般の
プラズマを用いた反応性イオンチャーでも良く、異方
性,等方性かも限られず、更にドライエッチの他に、過
酸化水素水の混合液によるウェットエッチでも応用可能
である。
In addition to the semiconductor device having the Al two-layer wiring structure shown in the embodiment, the present invention is applicable to the impurity layer of the Si substrate and the Po layer.
It is also applicable to the case where metal wiring such as Al is drawn out from a gate wiring using lySi or a silicide of refractory metal through a buried conductive material formed by etching back W or PolySi or WSi2 vapor-grown. It can be done. Further, when etching the residue 110, it is not limited to the presence or absence of the photoresist on the second metal wiring 107 and the dry etcher being ECR, and a reactive ion char using general plasma may be used. In addition to dry etching, wet etching with a mixed solution of hydrogen peroxide solution is also applicable.

【0009】[0009]

【発明の効果】以上の様に本発明によれば、微細化され
た特に多層配線構造等のLSIの製造に於いて、スルー
ホール部及び金属配線自身の平坦性や付き回りを改善
し、電気特性や品質に係わる長期信頼性の向上を図り、
高品質,高集積度の半導体装置の安定供給を可能にする
ものである。
As described above, according to the present invention, in the manufacture of a miniaturized LSI such as a multilayer wiring structure, the through hole portion and the metal wiring themselves are improved in flatness and throwing power, and To improve long-term reliability related to characteristics and quality,
This enables stable supply of high-quality, highly integrated semiconductor devices.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係わる半導体装置の製造方法を示す工
程概略断面図である。
FIG. 1 is a schematic cross-sectional view of a process showing a method for manufacturing a semiconductor device according to the present invention.

【図2】本発明に係わる半導体装置を示す概略平面図で
ある。
FIG. 2 is a schematic plan view showing a semiconductor device according to the present invention.

【図3】従来の半導体装置の製造方法を示す工程概略断
面図である。
3A to 3C are schematic cross-sectional views of processes showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

101 Si基板 102 フィールド絶縁膜 103 第1の金属配線 104 層間絶縁膜 105 密着層 106 タングステン 107 第2の金属配線 108,109 反射防止膜 110 残渣 111 スルーホール 101 Si Substrate 102 Field Insulating Film 103 First Metal Wiring 104 Interlayer Insulating Film 105 Adhesion Layer 106 Tungsten 107 Second Metal Wiring 108, 109 Antireflection Film 110 Residue 111 Through Hole

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体素子等が形成された基板上に、少な
くとも、層間絶縁膜を形成する工程、該絶縁膜に電気的
接続を取る為の接続孔を形成する工程、下層半導体素子
の導電層もしくは金属等でなる第1の配線層と電気的接
続を行なう為の導電材を全面に成長する工程、該導電材
の所望厚みをエッチバックする工程、第2の配線層を成
長しパターニングする工程、該第2の配線層をマスクに
して露出している導電材をエッチングする工程を具備し
たことを特徴とする半導体装置の製造方法。
1. A step of forming at least an interlayer insulating film on a substrate on which a semiconductor element or the like is formed, a step of forming a connection hole for electrically connecting to the insulating film, and a conductive layer of a lower semiconductor element. Alternatively, a step of growing a conductive material for electrically connecting to the first wiring layer made of metal or the like on the entire surface, a step of etching back a desired thickness of the conductive material, and a step of growing and patterning the second wiring layer. And a step of etching the exposed conductive material using the second wiring layer as a mask.
【請求項2】 請求項1に於いて、少なくとも導電材が
気相法によるWでなり、TiにTiNもしくはTiWの
積層膜を介在させて、Al合金でなる第2の配線層を形
成することを特徴とする半導体装置の製造方法。
2. The second wiring layer according to claim 1, wherein at least the conductive material is W by a vapor phase method, and a laminated film of TiN or TiW is interposed in Ti to form a second wiring layer made of an Al alloy. A method for manufacturing a semiconductor device, comprising:
【請求項3】 第1の配線層と、接続孔にエッチバック
によって埋め込まれた導電材を介して第2の配線層に電
気的接続がなされる多層配線構造を有する半導体装置に
於いて、接続孔領域以外の第2の配線層の下にも、該導
電材を構成する少なくとも一部材が残されていることを
特徴とする半導体装置。
3. A semiconductor device having a first wiring layer and a semiconductor device having a multilayer wiring structure in which electrical connection is made to a second wiring layer through a conductive material embedded in a connection hole by etching back. A semiconductor device characterized in that at least one member constituting the conductive material is left under the second wiring layer other than the hole region.
JP28778091A 1991-11-01 1991-11-01 Semiconductor device and manufacture thereof Pending JPH05129445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28778091A JPH05129445A (en) 1991-11-01 1991-11-01 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28778091A JPH05129445A (en) 1991-11-01 1991-11-01 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05129445A true JPH05129445A (en) 1993-05-25

Family

ID=17721652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28778091A Pending JPH05129445A (en) 1991-11-01 1991-11-01 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05129445A (en)

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