JP2993300B2 - Digital gamma correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image digital signal processor, and more particularly to a digital gamma correction circuit for a video camera.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a digital gamma correction circuit showing an example of the prior art. As shown in FIG. 5, a conventional digital gamma correction circuit is connected to an input terminal group 1 and shifts a digital input signal by performing multiplication and shifting, and adds a coefficient to an output of the shift circuit 36. Coefficient adding circuit 3 for outputting to the output terminal group 31
7 and an input detection circuit 3 which detects an input signal from the input terminal group 1 and controls the shift circuit 36 and the coefficient addition circuit 37.
8 is provided. In particular, the input detection circuit 38 controls the shift circuit 36 and the coefficient addition circuit 37 according to the output.

In such a digital gamma correction circuit, a video signal X is input from an input terminal group 1. When the video signal X is equal to or lower than the level 21, the shift circuit 36 is controlled to multiply the video signal X by 4, and the coefficient adding circuit 37 is controlled to add 0. This control is performed by the input detection circuit 38. Next, when the video signal X has a level of 22 or more and 127 or less, the shift circuit 36
Is multiplied by 1 and the coefficient adding circuit 37 is controlled to add 64. Further, when the video signal X is at level 128 or higher, the shift circuit 36
Is multiplied by a coefficient 係数, and the coefficient adding circuit 37 is controlled to add 128. These relations are expressed as follows.

[0004] When 0≤X≤21, 4X when 22≤X≤127, X + 64 when 128≤X≤255 (X / 2) +128. FIG. 6 is an input / output characteristic diagram of the digital gamma correction circuit in FIG. As shown in FIG. 6, the input / output characteristic S4 of this digital gamma correction circuit is an ideal gamma characteristic S4.
1 is represented by three straight line portions as described above. The digital gamma correction circuit of the broken line approximation
For example, it is described in JP-A-62-289090.

[0005]

In the above-mentioned conventional digital gamma correction circuit, the input / output characteristic is a polygonal line approximation using a linear equation. Therefore, when a triangular wave is input to this correction circuit, a portion where the characteristics are switched is seen, resulting in a disadvantage that an output image becomes very unnatural.

An object of the present invention is to provide a digital gamma correction circuit capable of eliminating the unnaturalness of an output image at such a characteristic switching point.

[0007]

A digital gun according to the present invention.
The correction circuit is connected to the input terminal group and
DetectTogether with multiple control signals depending on the detection result.
Signal control circuitInput level detection
Means for the input signalAmong several coefficient levels
One selected fromcoefficientlevelSubtract the firstReductionArithmeticvessel
And the firstReductionArithmeticvesselOutputAnd the coefficient of "-1"
A signal selector for selecting one of the outputs, and an output of the first subtractor.
Force and output of said signal selectorMultiply byTo the powerArithmeticvesselAnd before
WritingArithmeticvesselGiven outputFractionMultiply coefficientsfor
Multiple connected in parallelcoefficientvesselWhen,The plurality of coefficient multipliers
The output of the selected one coefficient unit is referred to as the coefficient level and
Different from the fractional coefficientIs a given coefficientLessArithmetic,That
Subtraction result2nd output to output terminal groupReductionArithmeticvesselWith
And saidThe plurality of controls output from the control signal conversion circuit.
Your signalBy,The first and secondReductionArithmeticvesselToEach supplied
Coefficient selection control and the signal selectorAnd saidpluralPerson in charge
InstrumentSelection control and input / output characteristics to ideal gamma characteristics
To be approximated by the quadratic and linear equationsComposed
You.Further, the input level detecting means according to the present invention,
Generate one or two coefficients representing a given switching level
From the output of the one or two coefficient generators
One or two subtractions to subtract the level of the input signal
And the outputs of the one or two subtractors
2 bits or 3 bits
It is formed to output a bit control signal. Also,
The first subtractor in the present invention is configured such that the minuend input is
Provides an input signal and includes a zero level coefficient in the decrement input
A coefficient generator for generating two or three predetermined coefficients
Formed to supply one of the selected coefficients
You. Further, the signal selector according to the present invention includes the input selector.
Output from the control signal conversion circuit of the power level detection means.
NAND of the plurality of control signals with coefficients 1 and 0
It is formed so as to be selectively controlled by a logical signal.
You.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a digital gamma correction circuit diagram showing one embodiment of the present invention. In FIG. 1, the present embodiment supplies subtractors 2, 3, 4, and 9 connected to an input terminal group 1, coefficient generators 5, 6, 7, 8, 9 for generating coefficients, and a subtractor 4. A signal selector 10 for selecting a coefficient;
Coefficient generator 11 for generating a coefficient of 1 and signal selector 1
2, a multiplier 13 for multiplying the output of the subtractor 4 and the output of the signal selector 12, and a control signal conversion circuit 14 for generating a control signal from the outputs of the subtracters 2 and 3. Also,
In the present embodiment, in addition to the above, coefficient units 15, 16, 17 for multiplying the output of the multiplier 13 by coefficients, a signal selector 18 for switching the outputs of these coefficient units 15 to 17, a coefficient 1, 0, Generators 19, 20, and 21 for generating a logic signal and a NAND which takes the logic of the control signal and the coefficients 1 and 0 described above.
Circuits 22, 23, 24 and these NAND circuits 22 to
24, a subtractor 26 that receives the output of the signal selector 18, a coefficient generator 27,
28, and a signal selector 30 for switching these coefficient generators 27 to 29 and supplying the coefficients to a subtractor 26. Moreover, the output of the subtracter 26 is output to the output terminal group 31.
As a gamma correction output.

In such a digital gamma correction circuit, an input signal from the input terminal group 1 is supplied to a minuend input of the subtractor 4 and a subtraction input of the subtracters 2 and 3, respectively. The coefficients from the coefficient generators 7, 8, 9 are switched by the signal selector 10, and the output is sent to the subtraction input of the subtractor 4.
The output of the subtractor 4 is supplied to one input of a multiplier 13 and a first input of a signal selector 12. The coefficient −1 from the coefficient generator 11 is supplied to a second input of the signal selector 12. Accordingly, the multiplier 13 squares the output of the subtractor 4 or multiplies the output by -1, so that the expression becomes a quadratic expression or a linear expression.

Next, the output of the multiplier 13 is output to the coefficient units 15-1.
7 are supplied to the respective inputs, and are therefore multiplied by the respective coefficients.
The outputs of these coefficient units 15 to 17 are switched by a signal selector 18 and supplied to a subtraction input of a subtractor 26. Further, the coefficient generators 27, 28 and 29 are switched by the signal selector 30 and supplied to the minuend input of the subtractor 26. Thus, the output of the subtracter 26 is output from the output terminal group 31.

On the other hand, the coefficients of the coefficient generators 5 and 6 are supplied to the minuend inputs of the subtracters 2 and 3. As a result, the subtracters 2 and 3 perform subtraction from the input signal, and supply the sign output to the control signal conversion circuit 14. This control signal conversion circuit 1
The first output of 4 is supplied to a first input of a first control signal input and two-input NAND circuit 24 of the signal selector 10,18,30, also the second output of the control signal converting circuit 14 Are supplied to the second control signal inputs of the signal selectors 10, 18, and 30 and the first input of the two-input NAND circuit 23, respectively. Similarly, the third output of the control signal conversion circuit 14 is supplied to the third control signal input of the signal selectors 10, 18, and 30 and the first input of the two-input NAND circuit 22, respectively. The coefficient generators 21, 20, and 19 are respectively connected to the second inputs of the two-input NAND circuits 24, 23, and 22, and the outputs of the two-input NAND circuits 22 to 24 are supplied to the inputs of the three-input NAND circuit 25. Is done. This 3
The signal selector 12 is switched by the output of the input NAND circuit 25.

Next, the coefficients in this embodiment are embodied,
The circuit operation will be described. First, the coefficient generators 5, 6, 7,
8, 9 are “127”, “21”, “27”,
"200" and "0" are generated, and coefficient generators 11, 19,
20, 21 are "-1", "1", "0",
"0" is generated, and the coefficient generators 27, 28 and 29 generate "92", "212" and "128", respectively. When the video input signal X is input from the input terminal group 1,
The input level detecting means composed of the subtracters 2 and 3 and the control signal conversion circuit 14 determines whether the input signal X level is in the range of 0 to 21, 22 to 127, or 128 to 255 (highest level). Detect if it is within range. Here, when the input signal X is from 0 to 21, the first output of the control signal conversion circuit 14 is set to high, and the input signal X is changed from 22 to 1
At the time of 27, the second output of the control signal conversion circuit 14 is made high. Similarly, when the input signal X is between 128 and 255, the third output of the control signal conversion circuit 14 is made high. As described above, the gamma correction circuit switches the coefficient for calculating the input signal X according to the output signal of the control signal conversion circuit 14.

Next, the output of the subtractor 4 is (X-27) when the input signal X is 0 to 21 and (X-27) when it is 22 to 127.
-200), becomes X when 128 to 255. Also,
When the input signal X is 0 to 21, the output of the multiplier 13 is (X
-27) ² , at the time of 22 to 127, (X-200) ² ,
It becomes -X at the time of 128 to 255. Further, the output of the signal selector 18 is (X−2) when the input signal X is 0 to 21.
7) when the ^{2 / 8,22 127 (X-200} ) 2 /
It becomes (-X / 2) when the value is from 255, 256 to 255.
Therefore, the output of the subtractor 26 is such that the input signal X is 0 to 21.
When the ^{{- (X-27) 2} /8} +92,22 from 12
When the 7 {- (X-200) 2/256} +212,1
(X / 2) +128 when the value is from 28 to 255.

FIG. 2 is an input / output characteristic diagram of the gamma correction circuit shown in FIG. As shown in FIG. 2, the input / output characteristics S2 of this embodiment are very similar to the ideal gamma characteristics S1. In short, in this embodiment, smoother approximation characteristics of the gamma characteristic can be realized by switching various coefficients and combining the linear expression and the quadratic expression.

FIG. 3 is a digital gamma correction circuit diagram showing another embodiment of the present invention. As shown in FIG. 3, the present embodiment selects the subtractors 2 and 4 connected to the input terminal group 1, the coefficient generators 5, 9 and 33 for generating coefficients, respectively, and the coefficients to be supplied to the subtractor 4. , A coefficient generator 11 for generating a coefficient of -1 and a signal selector 12
And a multiplier 13 for multiplying the output of the subtractor 4 and the output of the signal selector 12, and a control signal conversion circuit 32 for generating a control signal based on the output of the subtractor 2. In addition, the present embodiment also includes coefficient units 17 and 34 for multiplying the output of the multiplier 13 by coefficients, respectively, and the coefficient units 17 and 3.
4, a signal selector 18 for switching the output of C.4, coefficient generators 19 and 20 for generating the coefficients 1 and 0, NAND circuits 22 and 23 for taking the logic of the control signal and the coefficients 1 and 0, and these NAND circuits 22 and 23. 23, a NAND circuit 25 having two outputs, a subtractor 26 receiving the output of the signal selector 18, coefficient generators 29 and 35, and switching between the coefficient generators 29 and 35 and subtracting the output. And a signal selector 30 for supplying the signal to the device 26. Moreover, the subtracter 2
6 is supplied to the output terminal group 31 as a gamma correction output.

In such a digital gamma correction circuit, the input signal from the input terminal group 1 is supplied to the minuend input of the subtractor 4 and the minuend input of the subtractor 2, respectively. The coefficients from the coefficient generators 9 and 33 are switched by the signal selector 10, and the output is supplied to the subtraction input of the subtractor 4. The output of the subtractor 4 is supplied to one input of a multiplier 13 and a first input of a signal selector 12. Further, the coefficient generator 11 is connected to a second input of the signal selector 12. Accordingly, the multiplier 13 squares the output of the subtractor 4 or multiplies the output by -1, so that the expression becomes a quadratic expression or a linear expression.

Next, the output of the multiplier 13 is output to the coefficient units 17 and 3
Since they are supplied to the inputs of 4 respectively, they are each multiplied by a coefficient. The outputs of these coefficient units 17 and 34 are switched by a signal selector 18 and supplied to a subtraction input of a subtracter 26. Further, the coefficient generators 29 and 35 are switched by the signal selector 30, and
The coefficients are provided to the minuend input of the subtractor 26. Thus, the output of the subtracter 26 is output from the output terminal group 31.

On the other hand, the coefficient of the coefficient generator 5 is supplied to the minuend input of the subtractor 2. As a result, the subtractor 2 performs subtraction with the input signal, and outputs the sign output of the subtractor 2 to the control signal conversion circuit 3.
Feed to 2. The first output of the control signal converting circuit 32 is supplied to a first input of a first control signal input and two-input NAND circuit 22 of the signal selector 10,18,30, also the control signal converting circuit 32 Are connected to the second control signal inputs of the signal selectors 10, 18, and 30 and two inputs N
The signals are supplied to first inputs of the AND circuit 23, respectively. The coefficient generator 19 is connected to a second input of a two-input NAND circuit 22, and the coefficient generator 20 is connected to a second input of an input NAND circuit 23. These two-input NAND circuits 2
Outputs of the two-input NAND circuit 25 are supplied to first and second inputs of a two-input NAND circuit 25, respectively, and an output of the two-input NAND circuit 25 is supplied to a control input of the signal selector 12.

Hereinafter, the circuit operation of this embodiment will be described.
First, the coefficients of the coefficient generators 33 and 9 are 32 and 0, respectively, and the coefficients of the coefficient generators 35 and 29 are 200 and
128. Similarly, coefficient generators 5, 11, 19, 2
Each coefficient of 0 is 127, -1, 1, 0.

Next, when the video input signal X is input from the input terminal group 1, the subtractor 2 and the control signal conversion circuit 32 determine whether the input signal X level is between 0 and 127 or between 128 and 255. Is detected. Here, when the input signal X is 0 to 127, the first output of the control signal conversion circuit 32 becomes high, and conversely, when the input signal X becomes 128 to 255
At this time, the second output of the control signal conversion circuit 32 becomes high. Thus, the coefficient for calculating the input signal X of the gamma correction circuit is switched according to the output signal of the control signal conversion circuit 32.

Next, the output of the subtractor 4 becomes (X-32) when the input signal X is 0 to 127, and becomes X when the input signal X is 128 to 255. The output of the multiplier 1 becomes (X−32) ² when the input signal X is 0 to 127, and becomes −X when the input signal X is 128 to 255. Further, the output of the signal selector 18 is the input signal X
There when 0 ^{127 (X-32) 2 /} 128,128
Becomes -X / 2 at 255. Therefore, the subtracter 2
6 is-(X-3) when the input signal X is 0 or 127.
X 2) ^2/128 + 200,128 when 255 /
2 + 128.

FIG. 4 is an input / output characteristic diagram of the gamma correction circuit shown in FIG. As shown in FIG. 4, the input / output characteristics S3 of this embodiment can obtain similar characteristics to the ideal gamma characteristics S1.

[0024]

As described above, the digital gamma correction circuit according to the present invention can eliminate a large change in the gain at the switching point of the characteristic by forming the characteristic by combining the primary expression and the secondary expression. Moreover, there is an effect that the characteristics can be freely changed by changing each coefficient.

[Brief description of the drawings]

FIG. 1 is a digital gamma correction circuit diagram showing one embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram of the correction circuit shown in FIG.

FIG. 3 is a digital gamma correction circuit diagram showing another embodiment of the present invention.

4 is an input / output characteristic diagram of the correction circuit shown in FIG.

FIG. 5 is a block diagram of a digital gamma correction circuit showing an example of the related art.

6 is an input / output characteristic diagram of the correction circuit shown in FIG.

[Explanation of symbols]

1 input terminal group 2-4,26 subtracter 5-9,11,19-21,27-29,33,35
Coefficient generator 10, 12, 18, 30 Signal selector 13 Multiplier 14, 32 Control signal conversion circuit 15-17, 34 Coefficient unit 22-25 NAND circuit 31 Output terminal group S1 Ideal gamma characteristic S2, S3 Input / output characteristic

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 9/69 H04N 5/202

Claims (4)

(57) [Claims] 1. The level of an input signal connected to an input terminal group
DetectTogether with multiple control signals depending on the detection result.
Signal control circuitInput level detection
Means for the input signalAmong several coefficient levels
One selected fromcoefficientlevelSubtract the firstReductionArithmeticvessel
And the firstReductionArithmeticvesselOutputAnd the coefficient of "-1"
A signal selector for selecting one of the outputs, and an output of the first subtractor.
Force and output of said signal selectorMultiply byTo the powerArithmeticvesselAnd before
WritingArithmeticvesselGiven outputFractionMultiply coefficientsfor
Multiple connected in parallelcoefficientvesselWhen,The plurality of coefficient multipliers
The output of the selected one coefficient unit is referred to as the coefficient level and
Different from the fractional coefficientIs a given coefficientLessArithmetic,That
Subtraction result2nd output to output terminal groupReductionArithmeticvesselWith
And saidThe plurality of controls output from the control signal conversion circuit.
Your signalBy,The first and secondReductionArithmeticvesselToEach supplied
Coefficient selection control and the signal selectorAnd saidpluralPerson in charge
InstrumentSelection control and input / output characteristics to ideal gamma characteristics
Is approximated by a quadratic expression and a linear expressionCharacterized by
Digital gamma correction circuit. 2. The method according to claim 1, wherein the input level detection unit is configured to perform predetermined switching.
One or two coefficient generators representing the levels ;
From the output of one or two coefficient generators to the input signal
One or two subtractors for subtracting the level of
One or configured by said control signal converting circuit for receiving the output of the two subtractors, 2-bit or 3-bit control
2. The digital gamma correction circuit according to claim 1, which outputs a control signal . Wherein said first subtraction unit, said the minuend input
Provides an input signal and includes a zero level coefficient in the decrement input
A coefficient generator for generating two or three predetermined coefficients
2. The digital gamma correction circuit according to claim 1, wherein one of the selected coefficients is supplied . 4. The plurality of signal selectors output from the control signal conversion circuit of the input level detection means .
NAND logic of control signal and coefficients 1 and 0
2. The digital gamma correction circuit according to claim 1, wherein the digital gamma correction circuit is selectively controlled by a signal .