JP2989939B2 - Semiconductor manufacturing management equipment - Google Patents
Semiconductor manufacturing management equipmentInfo
- Publication number
- JP2989939B2 JP2989939B2 JP3183212A JP18321291A JP2989939B2 JP 2989939 B2 JP2989939 B2 JP 2989939B2 JP 3183212 A JP3183212 A JP 3183212A JP 18321291 A JP18321291 A JP 18321291A JP 2989939 B2 JP2989939 B2 JP 2989939B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion
- region
- semiconductor manufacturing
- manufacturing management
- layer resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Bipolar Transistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造工程
の管理に利用され、特に、拡散工程の管理を行う半導体
製造管理装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing management apparatus used for managing a semiconductor device manufacturing process, and more particularly to a semiconductor manufacturing management device for managing a diffusion process.
【０００２】[0002]
【従来の技術】従来、拡散工程では拡散前のベース層抵
抗値に関係なく、品種ごとにエミッタ拡散時間を一定に
設定して拡散を行っていた。図３、表１および表２を参
照しながら従来技術を説明する。トランジスタの特性上
で極めて重要な特性要因となる電流増幅率は、ベース１
２の持つベースの層抵抗値ＲS およびベース幅ＷB によ
って決定される。すなわち、表１に示すように、層抵抗
値が小さければ電流増幅率は小さくなり、層抵抗値が大
きければ電流増幅率は大きくなるという正の相関をもつ
ことが知られている。2. Description of the Related Art Conventionally, in a diffusion step, diffusion is performed by setting an emitter diffusion time constant for each product, regardless of a resistance value of a base layer before diffusion. The prior art will be described with reference to FIG. 3, Table 1 and Table 2. The current amplification factor, which is a very important characteristic factor in transistor characteristics, is based on
It is determined by the sheet resistance of the base R S and the base width W B with the 2. That is, as shown in Table 1, it is known that there is a positive correlation that the smaller the layer resistance value is, the smaller the current amplification factor is, and the larger the layer resistance value is, the larger the current amplification factor is.
【０００３】[0003]
【表１】 [Table 1]
【０００４】[0004]
【表２】 また、表２に示すように、拡散時間が短ければエミッタ
深さＸjEが浅くなり、電流増幅率が小さくなり、拡散時
間が長ければエミッタ深さＸjEが深くなり、電流増幅率
が大きくなるという正の相関をもつことも知られてい
る。これにより、エミッタ拡散時間が一定ということは
エミッタ深さＸjEが一定ということになり、それにとも
ないベース幅ＷB も一定となってしまう。このことは、
ベース１２の持つベースの層抵抗値ＲS のばらつきによ
って電流増幅率にもばらつきがでるというトランジスタ
にとって大きな弊害となる。[Table 2] Further, as shown in Table 2, if the diffusion time is short, the emitter depth X jE becomes shallow and the current amplification factor decreases, and if the diffusion time is long, the emitter depth X jE increases and the current amplification factor increases. It is also known to have a positive correlation. Thus, the fact that emitter diffusion time constant would be that the emitter depth X jE is constant, also becomes a constant base width W B accordingly. This means
This greatly affects the transistor in which the current amplification factor also varies due to the variation in the base layer resistance R S of the base 12.
【０００５】[0005]
【発明が解決しようとする課題】前述したように、従来
技術では、エミッタ深さ、ベース幅が一定のため、ベー
スの層抵抗値のばらつきによる電流増幅率のばらつきが
発生し歩留りが低下する欠点がある。As described above, in the prior art, since the depth of the emitter and the width of the base are constant, the current amplification factor varies due to the variation in the layer resistance value of the base, and the yield decreases. There is.
【０００６】本発明の目的は、前記の欠点を除去するこ
とにより、電流増幅率のばらつきを最小とし歩留りを向
上できる半導体製造管理装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor manufacturing management apparatus capable of improving the yield by minimizing the variation of the current amplification factor by eliminating the above-mentioned disadvantages.
【０００７】[0007]
【課題を解決するための手段】 本発明は、拡散装置に
おける不純物拡散工程を管理する半導体製造管理装置に
おいて、ウェーハに形成される半導体素子の第１の領域
の第１の電気的特性を測定した結果を格納する手段と、
前記第１の電気的特性がばらついても前記第１の電気的
特性と相関関係にある該半導体素子の第２の電気的特性
が予め設定された値となるように、前記格納手段より読
み出した前記第１の電気的特性値に応じた不純物拡散を
後工程において前記第１の領域にほどこし、前記第１の
領域内に第２の領域を形成するように製造条件を前記製
造装置に設定する製造条件設定手段とを備えたことを特
徴とする。 Means for Solving the Problems The present invention relates to a diffusion device.
Semiconductor manufacturing control equipment that controls the impurity diffusion process in
The first region of the semiconductor element formed on the wafer
Means for storing the result of measuring the first electrical characteristic of
Even if the first electrical characteristics vary, the first electrical
Second electrical characteristics of the semiconductor device correlated with the characteristics
Is read from the storage means so that the value becomes a preset value.
Impurity diffusion according to the first electrical characteristic value
In a subsequent step, the first region is provided,
The manufacturing conditions are adjusted so that a second region is formed in the region.
Manufacturing condition setting means for setting the
Sign.
【０００８】[0008]
【作用】層抵抗格納手段は、ウェーハごとに測定された
ベースの層抵抗値をウェーハの識別番号と一緒にして格
納する。一方、拡散条件格納手段は、ベースの層抵抗値
と拡散時間の関係を含む拡散条件を格納しておく。そし
て拡散条件設定手段は、次に拡散装置が拡散しようとす
るウェーハについて、ウェーハの識別番号を入力するこ
とで当該ウェーハの層抵抗値を層抵抗格納手段より読み
出し、その層抵抗値に対する拡散時間を拡散条件格納手
段から読み出して、拡散装置の拡散条件を設定する。The layer resistance storing means stores the layer resistance value of the base measured for each wafer together with the identification number of the wafer. On the other hand, the diffusion condition storage means stores diffusion conditions including a relationship between the base layer resistance value and the diffusion time. Then, the diffusion condition setting means reads the layer resistance value of the wafer from the layer resistance storage means by inputting the identification number of the wafer for the wafer to be diffused next by the diffusion device, and sets the diffusion time for the layer resistance value. The diffusion condition is read from the diffusion condition storage means and the diffusion condition of the diffusion device is set.
【０００９】従って、ウェーハごとに層抵抗値に基づい
て拡散時間を設定するので、トランジスタの電流増幅率
のばらつきを最小に抑え歩留りの向上を図ることが可能
となる。Therefore, since the diffusion time is set based on the layer resistance value for each wafer, it is possible to minimize the variation in the current amplification factor of the transistor and improve the yield.
【００１０】[0010]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１は本発明の一実施例を示すブロック構
成図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
【００１２】本実施例は、拡散装置２における不純物拡
散工程を管理する手段を備えた半導体製造管理装置にお
いて、本発明の特徴とするところの、層抵抗測定装置１
によりウェーハごとにエミッタ不純物拡散前に測定され
たウェーハ中のベース領域の層抵抗値をウェーハの番号
とともに格納する層抵抗格納手段としての、データ入出
力装置３、通信回線７、ホストコンピュータ５および履
歴ファイル８と、層抵抗値と拡散時間の関係を含む拡散
条件を格納する拡散条件格納手段としての拡散時間ファ
イル６と、拡散装置で拡散しようとするウェーハについ
て、履歴ファイル８より当該ウェーハの層抵抗値を読み
出し、その層抵抗値に対する拡散時間を拡散時間ファイ
ル６より読み出して拡散装置２の拡散条件を設定する拡
散条件設定手段としての、データ入出力装置４、ホスト
コンピュータ５、および通信回線７とを備えている。The present embodiment relates to a semiconductor manufacturing management apparatus provided with a means for managing an impurity diffusion step in the diffusion apparatus 2, which is a feature of the present invention.
A data input / output device 3, a communication line 7, a host computer 5, and a history as a layer resistance storing means for storing the layer resistance value of the base region in the wafer measured before the emitter impurity diffusion for each wafer together with the number of the wafer. A file 8, a diffusion time file 6 as diffusion condition storage means for storing diffusion conditions including a relation between a layer resistance value and a diffusion time, and a history file 8 for a wafer to be diffused by a diffusion device, from a history file 8. The data input / output device 4, the host computer 5, and the communication line 7 serve as diffusion condition setting means for reading a value, reading a diffusion time corresponding to the layer resistance value from the diffusion time file 6, and setting a diffusion condition of the diffusion device 2. It has.
【００１３】次に、本実施例の動作について図２に示す
流れ図を参照して説明する。図２において、ステップＳ
１からステップＳ３までは前段の作業で、ステップＳ４
からステップＳ８までは後段の作業である。Next, the operation of this embodiment will be described with reference to the flowchart shown in FIG. In FIG. 2, step S
Steps S1 to S3 are performed in the preceding stage, and are performed in step S4.
Pressurized et until the step S8 is subsequent work.
【００１４】まず、ウェーハが層抵抗値を測定する工程
に送られてくる。これを層抵抗測定装置１において、層
抵抗値を測定し、測定値をウェーハ識別番号とともにデ
ータ入出力装置３より入力し（ステップＳ１）、通信回
線７を介してホストコンピュータ５に送信する（ステッ
プＳ２）。送信されたデータはウェーハの加工履歴とし
て履歴ファイル８に格納される。次に、ウェーハが拡散
工程に送られてくる。ここで、データ入出力装置４を介
してウェーハ識別番号を入力すると（ステップＳ４）、
通信回線７を介してホストコンピュータ５に送信され、
ホストコンピュータ５は識別番号により履歴ファイル８
を検索し、当該層抵抗値を読み出し（ステップＳ５）、
当該層抵抗値をもとに拡散時間ファイル６を検索し、所
望の拡散時間を読み出す（ステップＳ６）。ホストコン
ピュータ５は通信回線７およびデータ入出力装置４を介
して、拡散装置２に所望の拡散時間を設定する（ステッ
プＳ７、Ｓ８）。First, the wafer is sent to a step of measuring a layer resistance value. This is measured in the layer resistance measuring device 1, the measured value is input from the data input / output device 3 together with the wafer identification number from the data input / output device 3 (step S1), and transmitted to the host computer 5 via the communication line 7 (step S1). S2). The transmitted data is stored in the history file 8 as a wafer processing history. Next, the wafer is sent to a diffusion process. Here, when a wafer identification number is input via the data input / output device 4 (step S4),
Transmitted to the host computer 5 via the communication line 7,
The host computer 5 uses the identification number to record the history file 8
And reads the layer resistance value (step S5).
The diffusion time file 6 is searched based on the layer resistance value, and a desired diffusion time is read (step S6). The host computer 5 sets a desired spreading time in the spreading device 2 via the communication line 7 and the data input / output device 4 (steps S7, S8).
【００１５】[0015]
【発明の効果】以上説明したように、本発明は、拡散時
間を変化させることで、層抵抗値のばらつきによる電流
増幅率のばらつきを最小に抑え、特性不良となる素子を
少なくすることができ、歩留り向上と拡散作業の能率向
上とを図ることができる効果がある。As described above, according to the present invention, by changing the diffusion time, the variation in the current amplification factor due to the variation in the layer resistance can be minimized, and the number of elements having poor characteristics can be reduced. This has the effect of improving the yield and the efficiency of the diffusion work.
【００１６】従って、本発明によれば、半導体装置の品
質を向上させ、製造コストを低減できる半導体製造管理
装置を得ることができ、その効果は大である。Therefore, according to the present invention, it is possible to obtain a semiconductor manufacturing management apparatus capable of improving the quality of a semiconductor device and reducing the manufacturing cost, and the effect is great.
【図１】本発明の一実施例を示すブロック構成図。FIG. 1 is a block diagram showing an embodiment of the present invention.
【図２】その動作を示す流れ図。FIG. 2 is a flowchart showing the operation.
【図３】トランジスタの電流増幅率を決定する要因の説
明図。FIG. 3 is an explanatory diagram of a factor that determines a current amplification factor of a transistor.
１ 層抵抗測定装置 ２ 拡散装置 ３、４ データ入出力装置 ５ ホストコンピュータ ６ 拡散時間ファイル ７ 通信回線 ８ 履歴ファイル １１ エミッタ １２ ベース Ｓ１〜Ｓ８ ステップ ＲS 層抵抗値 ＷB ベース幅 ＸjE エミッタ深さ12 base S1~S8 step R S layer resistance W B base width X jE emitter depth first layer resistance measuring device 2 diffusers 3,4 data input-output device 5 a host computer 6 diffusion time file 7 communication line 8 history file 11 emitter
Claims (2)
する半導体製造管理装置において、ウェーハに形成され
る半導体素子の第１の領域の第１の電気的特性を測定し
た結果を格納する手段と、前記第１の電気的特性がばら
ついても前記第１の電気的特性と相関関係にある該半導
体素子の第２の電気的特性が予め設定された値となるよ
うに、前記格納手段より読み出した前記第１の電気的特
性値に応じた不純物拡散を後工程において前記第１の領
域にほどこし、前記第１の領域内に第２の領域を形成す
るように製造条件を前記製造装置に設定する製造条件設
定手段とを有することを特徴とする半導体製造管理装
置。 An impurity diffusion process in a diffusion device is controlled.
Semiconductor manufacturing management equipment
Measuring a first electrical characteristic of a first region of the semiconductor device.
Means for storing the results obtained, and wherein the first electrical characteristics are different.
The semiconductor having a correlation with the first electrical characteristic.
The second electrical characteristic of the body element has a preset value.
As described above, the first electrical characteristic read from the storage means
In the subsequent process, the first region
Forming a second region in the first region.
The semiconductor manufacturing management system characterized by having a production condition setting means for setting the processing conditions the manufacturing apparatus as that.
する半導体製造管理装置において、ウェーハに形成され
るトランジスタのベース領域の層抵抗値を測定した結果
を格納する手段と、前記ベース層抵抗値がばらついても
前記ベース層抵抗値と相関関係にある電流増幅率が予め
設定された値となるように、前記格納手段より読み出し
た前記ベース層抵抗値に応じた不純物拡散を後工程にお
いて前記ベース領域にほどこしてエミッタ領域を形成す
るように製造条件を前記製造装置に設定する製造条件設
定手段とを有することを特徴とする半導体製造管理装
置。2. An impurity diffusion process in a diffusion device is controlled.
Semiconductor manufacturing management equipment
Of the layer resistance of the base region of a transistor
Means for storing the resistance of the base layer,
The current amplification rate correlated with the base layer resistance value is
Read from the storage means so that the set value is obtained
Impurity diffusion in accordance with the resistance value of the base layer in a subsequent process.
To form an emitter region by applying to the base region.
A production condition setting means for setting production conditions in the production apparatus as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3183212A JP2989939B2 (en) | 1991-06-26 | 1991-06-26 | Semiconductor manufacturing management equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3183212A JP2989939B2 (en) | 1991-06-26 | 1991-06-26 | Semiconductor manufacturing management equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH056861A JPH056861A (en) | 1993-01-14 |
| JP2989939B2 true JP2989939B2 (en) | 1999-12-13 |
Family
ID=16131745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3183212A Expired - Fee Related JP2989939B2 (en) | 1991-06-26 | 1991-06-26 | Semiconductor manufacturing management equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2989939B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6148927A (en) * | 1984-08-16 | 1986-03-10 | Matsushita Electronics Corp | Semiconductor device |
| JPS6164138A (en) * | 1984-09-06 | 1986-04-02 | Nec Corp | Monolithic integrated circuit |
| JPS61150324A (en) * | 1984-12-25 | 1986-07-09 | Toshiba Corp | Diffusion control equipment |
| JPS6222471A (en) * | 1985-07-22 | 1987-01-30 | Nec Corp | Semiconductor integrated circuit |
| JPS6316619A (en) * | 1986-07-08 | 1988-01-23 | Yokogawa Electric Corp | Control of semiconductor diffusion furnace |
-
1991
- 1991-06-26 JP JP3183212A patent/JP2989939B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH056861A (en) | 1993-01-14 |
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