JPS5967638A - Manufacturing system of semiconductor device - Google Patents
Manufacturing system of semiconductor deviceInfo
- Publication number
- JPS5967638A JPS5967638A JP17799982A JP17799982A JPS5967638A JP S5967638 A JPS5967638 A JP S5967638A JP 17799982 A JP17799982 A JP 17799982A JP 17799982 A JP17799982 A JP 17799982A JP S5967638 A JPS5967638 A JP S5967638A
- Authority
- JP
- Japan
- Prior art keywords
- manufacturing
- lot
- central processing
- processing unit
- terminal device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 71
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000004886 process control Methods 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 8
- 238000007689 inspection Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Factory Administration (AREA)
- Multi-Process Working Machines And Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
木琴ＢＡは、複数の製造工程を有し、それぞれ前記複数
の製造工程の工程順序と製造条件の異なる複数のロット
を並行して流すことによって多種類の半導体装置を製造
する半導体装置の製造システムに関する。[Detailed Description of the Invention] [Technical Field of the Invention] Xylophone BA has a plurality of manufacturing steps, and can be produced by producing multiple lots by running in parallel a plurality of lots having different process orders and manufacturing conditions in the plurality of manufacturing steps. The present invention relates to a semiconductor device manufacturing system for manufacturing various types of semiconductor devices.
第１図に従来の半導体装置の製造システムを示す。半導
体基板（以下「ウェハ」とじう）を出発材料として第１
工桿、第２工程、第３工程、第≠工程、第３工程まで経
ることにより半導体装置、例えば、ダイオード、トラン
ジスタ、ＩＣ５ＬＳＩなどを製造する。各工程は、例え
ば熱酸化、不純物拡散、イオン注入、レジスト塗布、露
光、現像゛なとである。FIG. 1 shows a conventional semiconductor device manufacturing system. First, using a semiconductor substrate (hereinafter referred to as "wafer") as a starting material
A semiconductor device, such as a diode, a transistor, an IC5LSI, etc., is manufactured by going through the steps of the process, the second step, the third step, the ≠ step, and the third step. Each process includes, for example, thermal oxidation, impurity diffusion, ion implantation, resist coating, exposure, and development.
一般に半導体装置の場合には上述した製造装置で一種類
の半導体装置だけ製造するのではなく、多ｆｌｕの半導
体装置を同時に製造するのが通例である。したがって各
ロット毎に名称を付与し、これらの名称に基づいてあら
かじめ定めである製造工程の手順や製造条件によシ製造
をおこなう。しかしながら、このような工程管理は複雑
であシ、製造すべき半導体装置の種類が増えると工程の
順序や製造条件を間違えたり検査の合否を間違えたシす
る場合も少なくなく問題となっていた。In general, in the case of semiconductor devices, it is customary to not only manufacture one type of semiconductor device using the above-mentioned manufacturing apparatus, but to simultaneously manufacture multiple flu semiconductor devices. Therefore, each lot is given a name, and the product is manufactured according to predetermined manufacturing process procedures and manufacturing conditions based on these names. However, such process control is complicated, and as the number of types of semiconductor devices to be manufactured increases, there are many cases where the order of the steps or manufacturing conditions are incorrect, or the test results are incorrect.
本発明は上記事情を考属してなされたもので、多種類の
半導体装置をひとつの製造システムで同時に並行して製
造する場合の製造工程や製造条件のミスを低減する半導
体装置の製造システムを提供することを目的とする。The present invention has been made in consideration of the above circumstances, and provides a semiconductor device manufacturing system that reduces errors in manufacturing processes and manufacturing conditions when multiple types of semiconductor devices are manufactured simultaneously in parallel using one manufacturing system. The purpose is to
この目的を達成するために、本発明による半導体装置の
製造システムは、複数のロットにイ＼］されたロット番
号を人力する製造工程毎の’７ｉｌａ末装匝と、各ロッ
ト毎に予め定められた工程順序、製造条件に従い、前記
端末装置から人力されたロット番号のロットの工程順序
、製造条件を前記端末装置に出力する中央処理装置とを
備え、複数の製造工程の工程管理をおこなうことを特徴
とする。In order to achieve this objective, the semiconductor device manufacturing system according to the present invention includes a '7ila end casing for each manufacturing process in which lot numbers are manually assigned to a plurality of lots, and a predetermined lot number for each lot. and a central processing unit that outputs the process order and manufacturing conditions of the lot of the lot number manually input from the terminal device to the terminal device according to the process order and manufacturing conditions determined by the terminal device, and performs process control of a plurality of manufacturing processes. Features.
本発明の一実施例による半導体装置の製造システムを第
一図に示す。第１工程から第ｊ工程棟であるものとし、
各工程には端末装置／／、／、２．／、３゜ｌ弘、／ｊ
と、これら各端１末装置を：１ｊｌＪ御する中央処理装
Ｎ２０が設けである。本製造システムで実際に製造をお
こなう前に、中央処理装置ユ０にデータ人力をする等の
準備が必要である。FIG. 1 shows a semiconductor device manufacturing system according to an embodiment of the present invention. From the first process to the jth process building,
Each process has a terminal device //, /, 2. /, 3゜lhiro, /j
A central processing unit N20 is provided to control each of these terminal devices. Before actually manufacturing with this manufacturing system, preparations such as inputting data to the central processing unit 0 are necessary.
■ まず各ロット毎に記号名を刊与し、各ウェー・また
はウェハな格納する容器にその記号名を書込む。■ First, a symbol name is issued for each lot, and the symbol name is written on each wafer or the container in which the wafers are stored.
■ 各ロット毎に予め定められている製造工程の順序、
および製造条件を、先の記号名と対応させて中央処理装
置２０に人力する。■ The order of manufacturing processes predetermined for each lot,
and the manufacturing conditions are manually entered into the central processing unit 20 in correspondence with the symbol name.
■ 各ロットの各製造工程毎に、その製造工程における
処理の結果が所望のものであるかの検査方法、検査条件
と判定基準を中央処理装置す０に入力する。笠だ検査が
不合格の場合の処理方法も中央処理装置にあらかじめ入
力する。(2) For each manufacturing process of each lot, the inspection method, inspection conditions, and criteria for determining whether the processing results in that manufacturing process are as desired are input into the central processing unit 0. The processing method in case the Kasada test fails is also input into the central processing unit in advance.
次に本製造システムを用いて製造する場合の動作につい
て第３図を用いて説明する。Next, the operation when manufacturing using this manufacturing system will be explained using FIG. 3.
第３図は１番目の工程における動作を示したものである
。この動作は検索ステップと実行ステップと報告ステッ
プとからなっている。まず１番目の工程の端末装置から
製造するロットの記号名を入力する（ブロック１０／）
。そしてその記号名のロットのこれまでの実行完了デー
タをチェックして製造工程の順序が正しいか否かを判定
しくブロック７０．２）、正しくない場合は正しい製造
工程を端末装置に出力しくブロック１０３）、ウェー・
を指示ちれた製造工程へ送る（ブロック／θ４ｔ）。正
しい場合には製造条件を端末装置に表示する（ブロック
１０よ）。FIG. 3 shows the operation in the first step. This operation consists of a search step, an execution step, and a report step. First, enter the symbol name of the lot to be manufactured from the terminal device of the first process (block 10/)
. Then, check the execution completion data of the lot with that symbol name to determine whether the order of manufacturing steps is correct (block 70.2), and if it is not correct, output the correct manufacturing process to the terminal device (block 103). ), way
is sent to the specified manufacturing process (block/θ4t). If correct, the manufacturing conditions are displayed on the terminal device (block 10).
ここまでが検索ステップである。次に実行ステップに移
り、指示された製造条件によシ製造工程を実行する（ブ
ロックｌｏ＆）。次に報告ステップに移る。まず製造工
程実行完了をｙｊ！ａ末装置１Ｊに入力し、実行完了デ
ータを記号名別に記憶する（ブロック／θ７）。製造工
程における処理が終わったウェー・を検査する検査方法
を端末装置に出力しくブロック７ｏｇ ） 、４’ａ＞
ｔ＜された検査方法でウェー・の検査を実行し、その結
果を九′ｊ末装置に人力する（ブロック１０ｙ）。This is the search step. Next, the process moves to an execution step, and the manufacturing process is executed according to the instructed manufacturing conditions (block lo&). Next, move on to the reporting step. First of all, please complete the manufacturing process! The execution completion data is input to the a-terminal device 1J and stored by symbol name (block/θ7). Output the inspection method for inspecting the processed wafer in the manufacturing process to the terminal device. Block 7og), 4'a>
The inspection of the wafer is carried out using the inspection method specified by t<t, and the results are manually input to the end device (block 10y).
検査結果は中央処理装置ユ０のメモリに記憶される。The test results are stored in the memory of the central processing unit unit 0.
次にこの検査結果が判定基準に合致しているかどうか判
定しくブロック１ｌＱ）、合致していない場合には、そ
の処理方法を端末装置へ出力しくブロック／／／）、ウ
ェー・を指示された処理をする（ブロック／／、２ ）
。検査結果が判定基準に合致している場合には、次の製
造工程（１＋／１目）を端末装置に出力しくブロックｌ
／３）、ウェー・を１十／番目の製造工程へ送り（ブロ
ックｉｎ） 、本工程での処理を終了する。Next, it is determined whether this test result matches the judgment criteria (Block 1lQ), and if it is not, the processing method is output to the terminal device (Block ///), and the method is specified. (block //, 2)
. If the inspection result matches the judgment criteria, block l to output the next manufacturing process (1+/1st) to the terminal device.
/3), the wafer is sent to the 10/th manufacturing process (block in), and the processing in this process is completed.
このように本実施例によれば、複雑な工程管理をミスな
くおこ１．ｌ：うことができる。In this way, according to this embodiment, complicated process management can be performed without mistakes. l: I can.
なお、ウニノ・またはウェー・を格納した容器に記載さ
れたロットの記号名を、周知の方法に従ってイメージセ
ンサにより読みと９端末装置または中央処理装置でパタ
ーン認識することによシ自励的に人力するようにしても
よい。また製造条件についても、中央処理装置から直接
製造条件をその工程における製造装置に人力して自動的
に宋件設定をおこなってもよい。In addition, the symbol name of the lot written on the container containing UNINO or WEI is read by an image sensor according to a well-known method, and pattern recognition is performed by a terminal device or a central processing unit. You may also do so. Further, regarding the manufacturing conditions, the manufacturing conditions may be automatically set by manually inputting the manufacturing conditions directly from the central processing unit to the manufacturing equipment in the process.
また、先の実施例では、各工程が直列に続いていたが、
半導体装置の製造工程では、むしろ酸化工程やイオン注
入工程やパターニング工程などの工程を複数回必要とす
る場合が多い。これに対しては第≠図に示すように端末
装置／／、 ／２． ／３． ／’Ａと中央処理装置、
２０を設ければよい。一般にこのような製造工程におい
てはミスが起きやすく・本発明はより有効であると言え
る。In addition, in the previous example, each process continued in series, but
In the manufacturing process of a semiconductor device, processes such as an oxidation process, an ion implantation process, and a patterning process are often required multiple times. For this purpose, as shown in Figure ≠, the terminal device //, /2. /3. /'A and the central processing unit,
20 may be provided. Generally, mistakes are likely to occur in such a manufacturing process, so the present invention can be said to be more effective.
更に、εＦＧ ’図に示ずようにウェー・まブこはウェ
ー・を収納した容器を搬送する周知の搬送路１５を各り
・１品末装置間に設け、各端末装置に前述した記号名の
自動読取り機能をイτＪ加すれば、自動的な工程管理が
おこなえ、ミスが起きることがない。Furthermore, as shown in the figure εFG', a well-known conveyance path 15 for conveying containers containing wafers and wafers is provided between each terminal device, and each terminal device is given the above-mentioned symbol name. By adding the automatic reading function of τJ, automatic process control can be performed and mistakes will not occur.
以上の通り、本発明によれば、多沖類の半導体装置を並
行して製造する場合でも製造工程や製造条件をミスなく
おこなうことができる。またロット毎の過去の実行完了
データや検査結果データを系統的に中央処理装置から得
ることができるので、生産計画や製造ラインの品質管理
な容易におこなうことができ、製造工程や製造条件の変
更に対しても容易に対処することができる。As described above, according to the present invention, even when multiple types of semiconductor devices are manufactured in parallel, the manufacturing process and manufacturing conditions can be performed without mistakes. In addition, since past execution completion data and inspection result data for each lot can be systematically obtained from the central processing unit, production planning and quality control of the manufacturing line can be easily performed, and changes in the manufacturing process and manufacturing conditions can be made easily. can also be easily dealt with.
第１図は従来の半導体装置の製造システムを示すブロッ
ク図、
第２図は本発明の一実施例による半導体装置の製造シス
テムを示すブロック図、
第３図は同システムの動作を示すフローチャート、
第μ図、第３図はそれぞれ本発明の他の実施例による半
導体装置の製造システムを示すブロック図である。
／／、 ／２． ／３． ／４４． ／３・・・端末装
置６、．２０・・用コ央処理装置、 ／ざ・・・搬送路
。FIG. 1 is a block diagram showing a conventional semiconductor device manufacturing system; FIG. 2 is a block diagram showing a semiconductor device manufacturing system according to an embodiment of the present invention; FIG. 3 is a flowchart showing the operation of the system; FIG. 3 is a block diagram showing a semiconductor device manufacturing system according to another embodiment of the present invention. //, /2. /3. /44. /3...terminal device 6, . 20...Central processing device, /Z...Transport path.
Claims (1)
る半導体装置の製造システムにおいて、前記複数のロッ
）Ｋ付されたロット番号を人力する製造工程毎の端末装
置と、 前記各ロット毎に予め定められた工程順序、製造条件に
従い、前記端末装置から人力されたロット番号のロット
の工程順序、製造条件を前記端末装置に出力する中央処
理装置とを備え、前記複数の製造工程の工程管理をおこ
なうことを特徴とする半導体装置の製造システム。[Scope of Claims] In a semiconductor device manufacturing system that has a plurality of manufacturing processes and each manufactures the plurality of products, a terminal device for each manufacturing process manually inputs lot numbers with K attached to the plurality of lots. , a central processing unit that outputs the process order and manufacturing conditions of the lot having the lot number manually inputted from the terminal device to the terminal device according to the process order and manufacturing conditions predetermined for each of the lots; A semiconductor device manufacturing system characterized by performing process control of the manufacturing process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17799982A JPS5967638A (en) | 1982-10-09 | 1982-10-09 | Manufacturing system of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17799982A JPS5967638A (en) | 1982-10-09 | 1982-10-09 | Manufacturing system of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5967638A true JPS5967638A (en) | 1984-04-17 |
Family
ID=16040770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17799982A Pending JPS5967638A (en) | 1982-10-09 | 1982-10-09 | Manufacturing system of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5967638A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6453554A (en) * | 1987-08-25 | 1989-03-01 | Sony Corp | Assembly system for semiconductor device |
| JPH0344054A (en) * | 1989-07-12 | 1991-02-25 | Hitachi Ltd | Inspection data analysis system |
| JPH03214743A (en) * | 1990-01-19 | 1991-09-19 | Nec Corp | Manufacturing system of semiconductor device |
| JPH08227925A (en) * | 1995-12-27 | 1996-09-03 | Tokyo Electron Ltd | Probing method |
| US6404911B2 (en) | 1989-07-12 | 2002-06-11 | Hitachi, Ltd. | Semiconductor failure analysis system |
-
1982
- 1982-10-09 JP JP17799982A patent/JPS5967638A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6453554A (en) * | 1987-08-25 | 1989-03-01 | Sony Corp | Assembly system for semiconductor device |
| JPH0344054A (en) * | 1989-07-12 | 1991-02-25 | Hitachi Ltd | Inspection data analysis system |
| JP2941308B2 (en) * | 1989-07-12 | 1999-08-25 | 株式会社日立製作所 | Inspection system and electronic device manufacturing method |
| US6185322B1 (en) | 1989-07-12 | 2001-02-06 | Hitachi, Ltd. | Inspection system and method using separate processors for processing different information regarding a workpiece such as an electronic device |
| US6330352B1 (en) | 1989-07-12 | 2001-12-11 | Hitachi, Ltd. | Inspection data analyzing system |
| US6339653B1 (en) | 1989-07-12 | 2002-01-15 | Hitachi, Ltd. | Inspection data analyzing system |
| US6404911B2 (en) | 1989-07-12 | 2002-06-11 | Hitachi, Ltd. | Semiconductor failure analysis system |
| US6529619B2 (en) | 1989-07-12 | 2003-03-04 | Hitachi, Ltd. | Inspection data analyzing system |
| US6628817B2 (en) | 1989-07-12 | 2003-09-30 | Hitachi, Ltd. | Inspection data analyzing system |
| JPH03214743A (en) * | 1990-01-19 | 1991-09-19 | Nec Corp | Manufacturing system of semiconductor device |
| JPH08227925A (en) * | 1995-12-27 | 1996-09-03 | Tokyo Electron Ltd | Probing method |
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