JP2983406B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device which suppresses and reduces synchronous noise generated in a reproduced image of an object.

[0002]

2. Description of the Related Art To increase the resolution of a CCD image pickup device, it is necessary to increase the number of pixels of the device. Increasing the number of pixels requires a higher pixel signal reading speed. For example, in a high-definition imaging device having 2 million pixels, the number of horizontal pixels is 2,000 and the number of vertical pixels is 1.
000. The horizontal read speed is about 74 MH
z. When the speed is increased as described above, problems such as power consumption and speeding up of a circuit arise.

As a method for solving this problem, horizontal CC
A method of changing D from a conventional one-wire system to a two-wire system is known. According to this method, the horizontal reading speed can be reduced by half to about 37 MHz, which is 1/2 of the conventional one, and the problems of power consumption and speeding up of the circuit can be reduced. However, there is a problem that the synchronizing noise superimposed on the clock pulse is mixed into the reproduced image to deteriorate the image quality.

FIG. 8 is a configuration diagram of a conventional solid-state imaging device of a two-line horizontal CCD system. The signal charge Q obtained by the photoelectric conversion unit PD is supplied to a vertical CCD (VCCD) by φV1,
Horizontal CCD (HC) with 4-phase drive of φV2, φV3, φV4
CD). And HCCD _A , HCCD
_The signal charge Q received by the two-line horizontal CCD composed of _B is
After being added by the addition circuit 80 through the output units OS _A and OS _B , the clock noise component is removed by a low-pass filter (LPF) 81.

[0005] HCCD _A and HCCD _B of two-line horizontal CCD
Are separated by a horizontal separation gate HG, and the odd-numbered pixel signals P1, P3, and P5 are transferred to the HCCD _A side, and the even-numbered pixel signals P2 and P4 are transferred to the HCCD _B side. Each HCCD is driven by two-phase clock pulses of φH1 and φH2. On the HCCD _B side, the pixel signal is output from the transfer unit 82 which shifts the pixel signal by half a pixel.

FIG. 9 shows the relationship between the synchronization noise and the signal band in the CCD image pickup device shown in FIG. This CCD
The signal band of the imaging device is １ ／ of the horizontal clock frequency F1
It becomes F2 of place. This point is the signal Nyquist limit. When the configuration of the two-line horizontal CCD is adopted, if the leakage amount of the clock pulse differs between the two lines, the leakage amount of the reset pulse differs, or a difference occurs in the gain of the amplifier between the two lines, Even if the signal outputs of the two wires are added by the adder circuit 80, the difference component appears at the location of F2 as synchronous noise.

Usually, a low-pass filter (LPF) is used to remove the synchronizing noise Nc.
If the phase characteristic is not sufficiently considered, ringing occurs in the signal, so that a steep attenuation characteristic cannot be obtained, and the PF has a shape as shown by a broken line in the figure. For this reason, the synchronization noise Nc in the LPF
Is removed, a considerable noise Nc still remains. This will be noticeable on the reproduced image.

This will be described in more detail with reference to a timing waveform chart of FIG. φH1, φH2
Is the clock pulse waveform of the two-line horizontal CCD, OS _A , OS
_{B is} the waveform of the signal outputs OS _A and OS _B , OS _A + OS _B
Represents the output waveform of the adder circuit 80. P1, P2, ~, P
9 is a pixel signal, N _A is a signal output of HCCD _A , S _B is H
The signal output of the CCD _B , Nc, represents a clock noise component (synchronous noise) when OS _A and OS _B are added.

[0009] CCD output signal in synchronism with the clock pulses, OS _A at the output P1, P3, ... it becomes, OS in _B P2, P4, ... becomes. Here, if the clock noises included in OS _A and OS _B are different, even if the signals of both are added (OS _A + OS _B ), the difference between the noises becomes Nc and appears in the signal waveform. If the addition gain is changed, the noise Nc can be reduced, but in this case, the signal output is different and cannot be used. This noise Nc appears as a synchronizing noise on the reproduced image.

[0010]

As described above, in the conventional solid-state imaging device of the two-line horizontal CCD system, synchronizing noise due to a clock pulse or a reset pulse appears at the Nyquist limit. If an LPF is used to remove this noise, the resolution will be reduced. Further, if an output image is obtained by increasing the output signal of the CCD for noise reduction, the sensitivity will be reduced. Therefore, there is a problem that a solid-state imaging device with high resolution and high sensitivity cannot be realized.

The present invention has been made in consideration of the above circumstances, and has as its object to suppress and reduce synchronization noise generated by clock pulses, reset pulses, and the like, and to achieve high resolution and high resolution. An object of the present invention is to provide a solid-state imaging device having high sensitivity.

[0012]

The gist of the present invention is to transfer the pixel signals of the two-line horizontal CCD to the A-register for odd-numbered pixels on the n-th line and to the B-register for even-numbered pixels on the n + 1-th line. To the B register and the even pixels to the A register so that clock noise (synchronous noise) is inverted for each line, and signals are output in phase. Another problem is that clock noise is removed from the obtained signal output by using a 1H (one horizontal scanning period) delay line.

That is, the present invention provides a two-dimensionally arranged signal charge storage section, a plurality of columns of vertical transfer sections for vertically transferring and reading the signal charges stored in these signal charge storage sections, A two-row horizontal transfer unit for transferring and reading signal charges read from the vertical transfer unit in the horizontal direction, and a means for adding the signal charges read from the horizontal transfer unit to obtain an image signal for one line In the solid-state imaging device including the pixel signals of the odd-numbered vertical transfer units among the pixel signals of one row obtained from the vertical transfer unit, the pixel signals of the even-numbered vertical transfer units are input to one of the horizontal transfer units. A signal is input to the other of the horizontal transfer units, and the horizontal transfer unit that inputs the odd-numbered and even-numbered pixel signals is switched every time a row changes. The following are preferred embodiments of the present invention.

(1) The horizontal CCD transfers signal charges in synchronization with the horizontal transfer clock pulse and the reset pulse. The pulse phase of the horizontal transfer clock pulse and the reset pulse is shifted by 180 ° in synchronization with the switching of the horizontal CCD. Stagger alternately.

(2) Means are provided for delaying the image signal for one line by one line time, and for obtaining an output signal by adding the delayed one-line signal and the next undelayed one-line signal. Was it.

(3) Means for delaying an image signal for one line by one line time and removing signal components other than noise, and a signal for one line delayed and a signal for one line not delayed
Means for obtaining an output signal by adding signals for lines is provided. (4) When an image signal for one line is delayed by one line time, an analog output signal is A / D converted and digitally performed. (5) Pixel signal switching is performed between the vertical CCD final stage and horizontal CC
Perform bottom gate provided between D. (6) Switching of pixel signals should be performed by controlling a field shift gate that reads out signal charges from a signal charge storage unit to a vertical transfer vertical transfer unit. (7) The switching of the pixel signals should be performed by controlling two horizontal division gates provided between two horizontal transfer units.

[0017]

According to the structure of the present invention, the switching of the horizontal transfer unit for each line causes the synchronization noise due to the clock pulse, the reset pulse, and the like to be inverted and output for each scanning line. It becomes hard to see. In this case, unlike the conventional method, the resolution and the sensitivity are not reduced.

The image signal for one line is delayed by one line time (and signal components other than noise are removed), and the delayed signal for one line and the signal for the next one line which are not delayed are separated. By adding and obtaining an output signal, only the synchronizing noise can be suppressed and reduced.
Higher resolution and higher sensitivity can be realized.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a schematic configuration diagram showing a solid-state imaging device of a two-line horizontal CCD system according to a first embodiment of the present invention.

The signal charges Q accumulated in the photoelectric conversion unit PD
Is a vertical CCD (VCCD) with four-phase drive φV1 and φV
2, φV3, φV4 and transferred to the bottom gate BG1. Then, the bottom gate BG2 which is a feature of the present invention is provided.
And the bottom gate GB3, the odd-numbered pixels and the even-numbered pixels in the horizontal direction of the PD are divided into two horizontal CCDs (HCCDs).
Is switched for each line. Two HCCD _A and HCCD _B
Are separated by a horizontal separation gate HG. On the HCCD _B side, a register HP for delaying the pixel signal by a half pixel is provided. Then, each is connected to the reset drain RD through the reset gate.

These series of operations are performed based on the pulses obtained by the timing pulse generation circuit 10. That is, R
S _A , RS _{B The} driver 11 reset electrodes RS _A , RS
Drive _B. On the other hand, the horizontal CCD is a φH1, φH2 driver 12, and the horizontal separation gate HG is an HG driver 13
The bottom gates BG2 and BG3 are BG2 and GB3 drivers 14 and the bottom gate BG1 is a BG1 driver 15
It is driven by.

The signal output obtained by the two-wire horizontal CCD is, OS _A terminal through the amplifier (AMP1, AMP2), it is taken out from the OS _B terminal. Then, each signal is added to the addition circuit 1
6 and the signal is divided into two systems. One of the divided signals passes through a band-pass filter (BPF) 17 and is input to an adder 19 through a delay circuit (1HDL) 18 that delays by one scanning period. The other signal is
Then, it is input to the addition circuit 19. Then, the adder circuit 19 adds the pixel signal of one line delayed by one scanning period to the pixel signal of the next line that is not delayed to obtain an output signal 20.

Next, the operation of the pixels on the nth line and the pixels on the (n + 1) th line in the vertical pixel array direction will be described with reference to FIG. FIG. 2A shows the case of n-line pixels.
(B) shows the case of pixels on the (n + 1) th line. P1, P
2, P3,... Indicate a pixel array in the horizontal direction. Here, HCCD _A is called an A register, and HCCD _B is called a B register.

As shown in FIG. 2A, in the case of n-line pixels, pixels P1, P3, and P5 are stored in the A register,
The pixels of P2 and P4 are transferred to the B register. And FIG.
As shown in (b), in the case of the pixel of the (n + 1) th line, P
The pixels P1, P2, and P4 are transferred to the A register, and the pixels P3 and P5 are transferred to the B register. The switching of the image signals to the A and B registers is performed by the bottom gates BG1 and BG described with reference to FIG.
The control is performed at the high and low levels of G3. This operation is performed alternately on each vertical line.

FIG. 3 shows specific operation waveforms. The left side of the figure shows the case of n lines, and the right side shows the case of n + 1 lines. R
S _A and RS _B are reset pulses at the end of the horizontal register, OS _A and OS _B are signal outputs, OS _A + OS _B are addition outputs, N _A1 , N _B1 , N _A2 , N _B2 , N _C1 and N _C2 are Clock noises S _A1 , S _B1 , S _A2 , S _B2 , S _C1 , S _C2 indicate signal components.

The pixel signals on the nth line and the (n + 1) th line are output in the same phase, and the clock noise is output in the opposite phase. Therefore, when the output of the n-th line passes through the BPF, only the clock noise is generated. When this signal is delayed by 1H line and added with the clock noise of the (n + 1) -th line and the signal including the signal component, the clock noise component is canceled and the signal component Only S _C2 is obtained.

FIG. 4 is a diagram showing the above results in a frequency spectrum. The clock noise N is removed by the inverted clock noise N ', and the reproduced signal S (OS _A + O
The signal frequency band of S _B ) extends to the Nyquist limit determined by the number of pixels. As a result, high resolution can be obtained even when two horizontal CCDs are used. Also, since the synchronizing noise generated by the clock noise hardly appears on the reproduced image,
A high-sensitivity CCD camera can also be realized.

FIGS. 5A and 5B illustrate a second embodiment of the present invention. FIG. 5A shows a signal waveform, and FIG. 5B shows a circuit configuration. Here, the operation of the 1HDL circuit is performed by a digital signal. By using a digital signal, the delay of 1H can be achieved with high accuracy and high stability, and the suppression of the synchronizing noise can be realized more effectively.

The output signals OS _A (n lines) and OS _B (n + 1 lines) of the two-line horizontal CCD are added by the adder circuit 51 to form a waveform shown in FIG. Then, the A / D converter 52 converts the analog signal into a digital signal,
HDL 53 delays by one line period. Further, the signal is converted back to an analog signal again by the D / A converter 54,
At 5, the signal is added to the original signal. The obtained output signal 56 has signal components (S _C1 , S _C1 , S 2) as shown in the addition output of FIG.
_C2 ) are added to form a signal in which the synchronizing noise (N _C1 , N _C2 ) is canceled.

FIG. 6 shows a second embodiment according to the third embodiment of the present invention.
FIG. 2 is a schematic configuration diagram illustrating a line-horizontal CCD type solid-state imaging device. This embodiment uses two horizontal CCDs to select a pixel signal.
In this example, the horizontal division gates HG1 and HG2 provided between them are used. Various symbols have the same names as the signals described so far.

In this embodiment, in the case of n lines, HG1
Is closed and HG2 is opened, so that the pixels of P1, P3, and P5 are stored in the A register as indicated by solid arrows in the figure, and P2,
The pixel at P4 is transferred to the B register. In the case of the (n + 1) th line, by opening HG1 and closing HG2, the pixels P1, P3, and P5 are transferred to the B register, and the pixels P2 and P4 are transferred to the A register, as indicated by the dashed arrows in the figure. Thus, as in the first embodiment, the odd-numbered and even-numbered pixel signals of the pixel signals for one row can be transferred to different registers, and the registers can be switched line by line. Therefore, the same effects as in the first embodiment can be obtained.

FIG. 7 shows a second embodiment according to the fourth embodiment of the present invention.
FIG. 2 is a schematic configuration diagram illustrating a line-horizontal CCD type solid-state imaging device. In this embodiment, the pixel number to be selected is set to the photoelectric conversion unit PD.
Signal read gates for each line (n, n + 1,...)
The vertical CCDs provided on the left and right of D can be read alternately. Various symbols have the same names as the signals described so far.

A horizontal division gate HG is provided between the A register and the B register, and the HG is opened every other one in the horizontal direction. Then, the odd-numbered pixel signals of the vertical CCD are transferred to the A register, and the even-numbered pixel signals are transferred to the B register.
The data is transferred to the register.

In this case, since the n-th line is read out to the left vertical CCD, the pixels P1, P3 and P5 are transferred to the A register, and the pixels P2 and P4 are transferred to the B register. Since the (n + 1) th line is read out to the right vertical CCD, the pixels P1, P3 and P5 are transferred to the B register,
The pixels P2 and P4 are transferred to the A register.

Therefore, as in the first embodiment, of the pixel signals for one row, the odd-numbered and even-numbered pixel signals can be transferred to different registers, and the registers can be exchanged line by line. The same effects as those of the first embodiment can be obtained.

The present invention is not limited to the above embodiments. Although the embodiment has been described using 1HDL, even if 1HDL is not used, since the synchronizing noise has an anti-phase relationship in each line, an effect is produced in which the reproduced image looks like a checkered pattern and is difficult to understand. Therefore, 1HDL can be omitted.

In the embodiment, one of the two horizontal CCDs is delayed by half a clock in the CCD. However, the same effect can be obtained by outputting the signals in the same phase and delaying one externally by half a clock. . In addition, various modifications can be made without departing from the scope of the present invention.

[0038]

As described above in detail, according to the present invention, 2
For the transfer of the pixel signals of the line horizontal CCD, the odd-numbered pixels are transferred to the first horizontal CCD and the even-numbered pixels are transferred to the second horizontal CCD in the n-th line.
In the (n + 1) th line, odd-numbered pixels are replaced with the second horizontal CC.
By applying the even-numbered pixels to the first horizontal CCD to D, the clock noise (synchronous noise) is inverted for each line, and the signals are output in phase. Further, clock noise is removed from the obtained signal output using a 1H (one horizontal scanning period) delay line. Therefore, it is possible to prevent a decrease in resolution due to the LPF used for suppressing the synchronization noise in the two-line horizontal CCD configuration, and to realize a solid-state imaging device with high resolution and high sensitivity.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a solid-state imaging device according to a first embodiment.

FIG. 2 is a diagram for explaining a pixel signal separating operation in the first embodiment.

FIG. 3 is a specific operation waveform diagram in the first embodiment.

FIG. 4 is a diagram showing a frequency relationship between a signal component and noise in the first embodiment.

FIG. 5 is a diagram for explaining a main part configuration and operation of the second embodiment.

FIG. 6 is a schematic configuration diagram illustrating a solid-state imaging device according to a third embodiment.

FIG. 7 is a schematic configuration diagram showing a solid-state imaging device according to a fourth embodiment.

FIG. 8 is a schematic configuration diagram showing a conventional solid-state imaging device.

FIG. 9 is a diagram showing the relationship between noise and signal components in a conventional device.

FIG. 10 is an operation waveform diagram in the conventional device.

[Explanation of symbols]

 PD: photoelectric conversion unit VCCD: vertical CCD (vertical transfer unit) HCCD: horizontal CCD (horizontal transfer unit) BG: bottom gate HG: horizontal separation gate HP: register RD: reset drain RS: reset electrode 10: timing pulse generation circuit 11 ... 15 Drivers 16, 19, 51, 55 Adder circuit 17 Band-pass filter (BPF) 18 Analog delay circuit (1HDL) 52 A / D converter 53 Digital delay circuit (1HDL) 54 D / A converter

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Otake 2-2-1 Jinnan, Shibuya-ku, Tokyo Japan Broadcasting Corporation (72) Inventor Masahide Abe 2-2-1 Jinnan, Shibuya-ku, Tokyo Japan Broadcasting Corporation (72) Inventor Yukio Endo 1st Toshiba-cho, Komukai, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba R & D Center Co., Ltd. Inside the Development Center (72) Inventor Souhei Manabe 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Research and Development Center Co., Ltd. Toshiba R & D Center (58) Fields surveyed (Int.Cl. ⁶ , DB name) H04N 5/30-5/335

Claims (2)

(57) [Claims] 1. A two-dimensional array of signal charge storage units, a plurality of columns of vertical transfer units for vertically transferring and reading signal charges stored in these signal charge storage units, Two rows of horizontal transfer units for transferring and reading the signal charges read out from the horizontal direction, and one row of pixel signals obtained from the vertical transfer unit.
Pixel signals of odd-numbered vertical transfer units are input to one of the horizontal transfer units, pixel signals of even-numbered vertical transfer units are input to the other of the horizontal transfer units, and each time a row changes, the odd-numbered and even-numbered Means for switching a horizontal transfer unit for inputting a pixel signal, and means for adding a signal charge read from the horizontal transfer unit to obtain an image signal for one line. Imaging device. 2. A two-dimensionally arranged signal charge storage unit, a plurality of columns of vertical transfer units for vertically transferring and reading out signal charges stored in these signal charge storage units, and a plurality of vertical transfer units. Two rows of horizontal transfer units for transferring and reading the signal charges read out from the horizontal direction, and one row of pixel signals obtained from the vertical transfer unit.
Pixel signals of odd-numbered vertical transfer units are input to one of the horizontal transfer units, pixel signals of even-numbered vertical transfer units are input to the other of the horizontal transfer units, and each time a row changes, the odd-numbered and even-numbered Means for switching a horizontal transfer unit for inputting a pixel signal, means for adding a signal charge read from the horizontal transfer unit to obtain an image signal for one line, and image signal for one line for one line time Means for delaying, the delayed one-line signal and the next one which is not delayed
Means for obtaining an output signal by adding signals for the lines to obtain a solid-state imaging device.