JP2976926B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an inductor element formed on a semiconductor substrate, and more particularly to a semiconductor device suitable for use as an analog filter, an oscillator, or the like.

[0002]

2. Description of the Related Art In recent years, with the speeding up and economy of the communication field, technical progress has been remarkable regarding high speed and high functioning of an LSI which is a basic technology thereof.

A first prior art of a semiconductor device having an inductor element formed on a semiconductor substrate will be described with reference to the drawings.

FIG. 5 shows a conventional two-dimensional spiral inductor. FIG. 5A is a three-dimensional view, and FIG. 5B is a plan view. The inductor element formed on the semiconductor substrate having the structure shown in FIG.
liam. B. Kuhn et al. (WB Kuh)
n, F. W. Stephenson, A .; Elshab
mini-Rad, "A 200MHz CMOS Q
-EnhancedLC Bandpass Filt
er ”, IEEE JOURNAL OFSOLID-
STATE CIRCUITS, VOL. 31, NO.
8, AUGUST 1996) describes its characteristics in detail.

According to the above-mentioned paper, the following equation (1) holds for the inductance (L _s ) in FIG.

L _s ≒ αDNβ (1)

Here, D is the length of the longest side of the inductance element, N is the number of turns, and α and β are empirical values. Where α
Is determined by the magnetic permeability of the material, that is, the process, and β is determined by the shape of the inductor element.

FIG. 6 is a sectional view of a semiconductor device on which the inductor element of FIG. 5 is formed. In FIG. 6, 1 indicates a first aluminum wiring layer, and 2 indicates a second aluminum wiring layer. Since this semiconductor device can be manufactured by a general CMOS process, the manufacturing method is omitted.

The conventional inductor element having this structure is most commonly used as an inductor element formed on a semiconductor substrate.

However, since a single wiring layer has a structure in which the inductor element is formed in a spiral shape (spiral), the area increases as the L (inductance) increases, and a relatively large inductance is integrated in the LSI. It was difficult to convert.

Therefore, the inductor having the structure shown in FIG. 5 is designed so that the current flowing through each of the plurality of wiring layers, that is, the wiring layers which are vertically related when viewed from the sectional view of FIG. Elements are stacked vertically on a semiconductor substrate,
An inductor element has also been trial manufactured in consideration of the effect of mutual inductance between different wiring layers. FIG. 7 shows this structure as a second conventional technique. This second conventional technique will be described with reference to the drawings.

First, β in the above-mentioned paper describing the first conventional technique is 1.8, but for simplicity, it is β〜2 when D is sufficiently large.

When the inductance L _s in the above equation (1) when D is sufficiently large is L ₁ , the following equation (2) can be obtained.

L ₁ ≒ αDN ² (2)

The inductance (L ₂ ) of the second prior art inductor element shown in FIG. 7 is generally given by the following equation (3).

L ₂ = L _1A1 + L _2A1 + kM ₁₂ + kM ₂₁ (3)

Here, L _1A1 is the self-inductance of the portion constituted by the _1Al layer (first aluminum wiring layer), and L _2Al
Mutual inductance of self-inductance of portions constituted by 2Al layer (second aluminum wiring layer), M ₁₂ is the configured part 2Al layer from the configuration portions in 1Al layer,
M ₂₁ is the mutual inductance, k from the configured part 2Al layer to the configuration portions in 1Al layer is the coupling coefficient.

It is also assumed that the same area (D ² ) and the same process as in FIG. 5 are used, and that there is no magnetic flux leakage (the magnetic flux passing through the 1Al surface in FIG. 7 always passes through the 2Al surface, and vice versa). , since the put and _{k ≒ 1, L 1Al = L} 2Al = M 12 = M 21 ≒ L 1, the inductance (L ₂₎ which is determined from the shape of the inductor element of Figure 7 is the _{L 2 ≒ 4L 1 ... (4} ) .

However, in order to obtain a large L (inductance), the wiring length of the wiring forming the inductor element is inevitably increased, and the effect of the transmission delay (electron transmission speed) cannot be ignored.

Next, the influence of the transmission delay of the inductor element of the second prior art shown in FIG. 7 will be described.

FIG. 8 is a simplified diagram of the second prior art inductor element shown in FIG. Here, small portions of FIG. 8 ΔZ1, ..., ΔZk, ... , in the region of the respective DerutaZN, the sum [Phi ₂ flux sum, the self-inductance per unit length Lo, the mutual inductance per unit length Mo age,
By taking out only the influence of the magnetic field in the vicinity, it can be expressed by the following equation (5).

[0022]

(Equation 1)

Here, I ₁ , I _k , I _N ,... Respectively represent ΔZ1, ΔZk, ΔZN,.
The currents flowing through the sections, I ′ ₁ , I ′ _k , I ′ _N, are at any time:
These are currents flowing through ΔZ′1, ΔZ′k, and ΔZ′N in FIG. 8, and all have the same value if there is no transmission delay.

Further, {} _a magnetic flux sum of ΔZ1 parts, {} _b respectively represent the magnetic flux sum ΔZk part, {} _c is the magnetic flux sum ΔZN portion.

Here, considering the transmission delay, the current I is a function of time and the distance over which the signal is transmitted, and can be generally expressed by the following equation (6).

[0026]

(Equation 2)

Where ω is the frequency of the signal, Z is the distance over which the signal is transmitted, and v is the transmission speed of the electron, v = 1 / √ (LC)
(Where L is the inductance per unit length of the wiring, and C is the capacitance per unit length of the wiring).

Now, let Z be the length of all the wires forming the inductor element, Z _{O be} the length of the outermost turn of the inductor element, and N be the number of turns.

Here, considering the signal transmission path of FIG. 9, it can be seen that the above equation (5) can be written as follows.
FIG. 9 is a diagram showing a signal transmission path of the simplified diagram shown in FIG.

However, t2 = t1 + {2, t3 = t1 +}
3: ψ2 and ψ3 are phase differences with t1, but here, since only the interaction of the proximity part is considered, the following description is given. Further, the ΔZk portion is set between the ΔZ1 portion and the ΔZN portion.

[0031]

(Equation 3)

Here, Lo ≒ Mo, Z / v << 1, Z >>
Z _o ,

[0033]

(Equation 4)

If (where Re indicates the real part), the right side of the above equation (7) is expressed by the following equation (8).

[0035]

(Equation 5)

Therefore, considering the transmission delay from the first and second terms of the above equation (8), the local magnetic flux is reduced.

That is, the total inductance (L _eff2 ) of the effective inductor element having the structure shown in FIG. 7 is reduced.

L _eff2 (ω) <L ₂ (≒ 4L ₁ ) (9)

[0039]

As described above,
In order to obtain a large inductance,
If the length of the wiring forming the inductor element is made sufficiently long, there is a problem that the effective total inductance is reduced, particularly in a high frequency range.

The reason is that a long wiring causes a transmission delay, and the influence of the mutual inductance is reduced depending on the frequency.

Accordingly, the present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to achieve high integration by using a multi-layer wiring technique and to achieve the above-described signal transmission delay. In particular, it is an object of the present invention to provide a semiconductor device having an inductor element having good inductance characteristics with good high frequency characteristics.

[0042]

In order to achieve the above object, the present invention provides a semiconductor substrate, a plurality of first conductor layers arranged in parallel on the substrate, and an insulating layer on the conductive layer. A plurality of second conductor layers arranged side by side, wherein the first conductor layer and the second conductor layer are selectively electrically connected in a helical manner via via holes formed in an insulating layer; The first of
The inductor is configured such that the conductor layer is two-dimensionally spiral and the plurality of second conductor layers are also two-dimensionally spiral, and the first and second conductor layers are formed between different layers. The configuration is such that the signal propagation distance up to the interaction is shortened.

[Operation] The operation of the present invention will be described. In the present invention having the above-described structure, a semiconductor substrate, a plurality of first conductor layers arranged in parallel on the substrate, and A plurality of second conductor layers juxtaposed via an insulating layer;
The first conductor layer and the second conductor layer are selectively and electrically connected in a helical manner via via holes formed in the insulating layer, and the plurality of first conductor layers spirally two-dimensionally. And the plurality of second conductor layers also have an inductor configured to be two-dimensionally swirled, so that when signals are transmitted, transmission delay of signals contributing to close interaction can be reduced, High frequency characteristics can be improved.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the inductor element of the present invention will be described below. FIG. 1 is a diagram for describing an embodiment of the present invention. In the embodiment of the present invention, the inductor element can be realized by using a general CMOS process technology used in the conventional technology shown in FIG.

Here, an inductor determined by the shape of the inductor element in the embodiment of the present invention is obtained from FIG. 2 and the above equation (2). 2A is a plan view as viewed from the 2Al layer, and FIG. 2B is a plan view as viewed from the 1Al layer.

Referring to FIG. 2 (b), the m-th loop 4 and the (m + 1) -th loop 5 counted from the outside of the
It can be considered that the m-th loop 6 counted from the outside of the Al layer is inserted. When this is sequentially inserted from m = 1 to N, it can be considered that the number of turns N of the inductor element in FIG. 6 is equivalently doubled to 2N.

Therefore, if N in the above equation (2) is replaced with 2N, the inductance (L ₃ ) of the embodiment of the present invention determined from the shape is as follows:

L ₃ ≒ αD (2N) ² = 4αDN ² = 4L ₁ (10)

Next, the effect of the propagation delay will be considered in the same manner as in the second conventional technique.

FIG. 3 is a simplified diagram of the inductor element according to the embodiment of the present invention shown in FIG. Here, the minute portion Δ in FIG.
The sum Φ ₃ of the magnetic flux sums at the respective portions of Z1,..., ΔZk,..., ΔZN is expressed as follows: Lo is the self-inductance per unit length, and Mo is the mutual inductance per unit length. , Can be expressed by the following equation (11).

[0051]

(Equation 6)

Here, I ₁ , I _k , I _{N ,.}
At any time, the currents flowing through the parts ΔZ1, ΔZk, ΔZN,... In FIG. 3, I ′ ₁ , I ′ _k , and I ′ _N become ΔZ′1, ΔZ′k, ΔZ ′ of FIG. All values are the same if there is no transmission delay in the current flowing through N.

[0053] Further, {} _a magnetic flux sum of ΔZ1 parts, {} _b is the magnetic flux sum ΔZk part, {} _c represents the magnetic flux sum of ΔZN portion.

Using the above equation (6) and considering the signal transmission path of FIG. 4, it can be seen that the above equation (11) can be expressed as the following equation (12). FIG. 4 is a diagram showing signal transmission paths in the simplified diagram of FIG.

[0055]

(Equation 7)

Here, an approximation similar to the above equation (8) is performed, and
Assuming that the magnitude of Z ₀ / v is sufficiently small, the following equation (13)
Is derived.

[0057]

(Equation 8)

Therefore, in the present invention, there is no term where the local magnetic flux decreases.

That is, there is no _effective decrease in the total inductance (L _eff3 ) of the inductor element having the structure of FIG.

L _eff3 ≒ L ₃ (≒ 4L ₁ ) (14)

From the above equations (4) and (10), the inductance determined by the shape is almost the same as that of the prior art and the present invention.

However, from the above equations (8) and (14), considering the transmission delay (the transmission speed of electrons), the present invention is a signal transmission path that is not easily affected by the transmission delay.

Therefore, in the present invention, since there is no frequency-dependent decreasing term in the inductance coefficient, the present invention is particularly excellent in high frequency characteristics.

In the present invention, since an inductor element having a large L (inductance) can be formed on a semiconductor substrate, the number of components can be reduced, and the communication device can be reduced in size and economy, and the high-frequency characteristics can be improved.

[0065]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

Embodiment 1 FIG. 1 is a three-dimensional view showing an embodiment of an inductor element to which the present invention is applied. The inductor element of the present invention can be realized by using a general CMOS process technology used in the conventional technology of FIG.

For example, Al, Cu, an Al alloy (Al-Si-) for connecting the inductor element to another circuit element.
A first wiring layer 1 formed of a material such as Cu) by a sputtering technique and an exposure / etching technique using a resist, and an insulating layer 2 such as SiO ₂ formed thereon by a plasma oxide film growth technique. Al insulating layer 2 has Al reflow, single crystal Al substitution, blanket W (tungsten)
A through-hole formed on a selected portion of the first wiring layer 1 so as to have conductivity with the selected portion of the first wiring layer 1 by using CVD, selective W-CVD technology, or the like; Al, C on which the through hole 3 and a selected part thereof are electrically connected to each other on the insulating layer 2.
The wiring layer 1 and the wiring layer 4 are formed by the second wiring layer 4 patterned by using a material such as u, Al alloy (Al-Si-Cu) by a sputtering technique and an exposure / etching technique using a resist. As shown in FIG.
As shown in (b), one end of the m-th loop counted from the outside of the 2Al layer is connected to one end of the m-th loop counted from the outside of the 1Al layer, and the m-th loop counted from the outside of the 1Al layer. The other end of the loop is formed by sequentially connecting one end of the m-th loop counted from the outside of the 2Al layer for the number of turns from m = 1 to N.

Next, an inductor determined by the shape of the inductor element of this embodiment is obtained from FIG. 2 and the above equation (2).

In FIG. 2B, when the m-th loop counted from the outside of the 2Al layer and the m + 1-th loop are counted from the outside of the 1Al layer and the m-th loop is sequentially inserted from m = 1 to N, the equivalent is obtained. It can be considered that the number N of turns of the inductor element in FIG. 6 is doubled to 2N.

Here, N = 48, α = 9 × 10 ⁻⁷ , D =
When N is 1000 μm and N in the above equation (2) is replaced with 2N, the inductance (L ₃ ) of the present embodiment determined from the shape
Is given by the following equation (15).

L ₃ ≒ αD (2B) ² = 4 × 9 × 10 ⁻⁷ × 10 ⁻³ × (48) ² = 8 μH (15)

Next, similarly to the second conventional technique, the influence of the propagation delay will be considered.

FIG. 3 is a simplified diagram of one embodiment of the inductor element of the present invention shown in FIG. Here, the minute portion ΔZ in FIG.
1,..., ΔZk,..., ΔZN, the sum Φ ₃ of the magnetic flux sums is such that the self inductance per unit length is Lo, the mutual inductance per unit length is Mo, and only the influence of the proximity part is taken out. , Equation (11).

[0074]

(Equation 9)

Here, I ₁ , I _k , I _{N ,.}
At any time, the currents flowing through the parts ΔZ1, ΔZk, ΔZN,..., I ′ ₁ , I ′ _k , and I ′ _N become ΔΔ at FIG.
The currents flowing through the Z′1, ΔZ′k, and ΔZ′N sections have the same value unless there is a transmission delay. Also, {} _a magnetic flux sum of ΔZ1 parts, {} _b is the magnetic flux sum ΔZk part, {} _c represents the magnetic flux sum of ΔZN portion.

Using the above equation (6) and considering the signal transmission delay of FIG. 4, it can be seen that the above equation (11) is expressed as follows.

[0077]

(Equation 10)

Here, Zo is on the order of 10 ⁻³ m, and v is 1
Since the order of about 0 ⁸ s / m, regarded as Z size of ₀ / v is sufficiently small becomes about 10ps becomes the order of 10 ^-11 delay.

However, in the case of the second prior art, the distance between the input and output sections is on the order of 10 ^-1 m at the maximum, and is 1 ns.
Can not be ignored because of the delay. That is, the following equation described in the embodiment section of the present invention is introduced.

[0080]

[Equation 11]

Therefore, in this embodiment, there is no term where the local magnetic flux decreases.

That is, there is no _effective reduction in the total inductance (L _eff3 ) of the inductor element having the structure shown in FIG.

L _eff3 ≒ L ₃ (≒ 4L ₁ ) (14)

The inductance determined from the shapes according to the above equations (4) and (10) is almost the same as that of the prior art and the present invention.

However, from the above equations (8) and (13), when the transmission delay (electron transmission speed) is considered, the present embodiment is a signal transmission path which is hardly affected by the transmission delay.

Thus, in this embodiment, since there is no frequency-dependent decreasing term in the inductance coefficient, the present embodiment is particularly excellent in high frequency characteristics.

[0087]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that high integration of an inductor element formed on a semiconductor substrate can be achieved.

The reason is that, in the present invention, a multi-layer wiring technique can be used, and can be juxtaposed to a semiconductor substrate.

The second effect of the present invention is that high frequency characteristics are good.

The reason is that, in the present invention, the signal path is less affected by the signal transmission delay.

[Brief description of the drawings]

FIG. 1 is a three-dimensional view showing a configuration of a first embodiment of the present invention.

FIG. 2 is a plan view showing the configuration of the first exemplary embodiment of the present invention. (A) is the figure seen from the 2Al layer surface.
(B) is a diagram when viewed from the 1Al layer surface.

FIG. 3 is a simplified diagram of the inductor element according to the first embodiment of the present invention.

FIG. 4 is a signal transmission path diagram of the simplified diagram of FIG. 3;

FIG. 5 is a diagram showing a configuration of a first conventional technique;
(A) is a three-dimensional view, (b) is a plan view.

FIG. 6 is a sectional view of a first conventional technique.

FIG. 7 is a three-dimensional view of a second conventional technique.

FIG. 8 is a simplified diagram of a second prior art inductor element.

FIG. 9 is a signal transmission path diagram of the simplified diagram of FIG. 8;

[Explanation of symbols]

 Reference Signs List 1 1Al layer 2 2Al layer 3 Through hole (or via hole) 4 m-th 2Al layer loop 5 m + 1-th 2Al layer loop 6 m-th 1Al layer loop

Claims (2)

(57) [Claims] A semiconductor substrate, a plurality of first conductor layers arranged in parallel on the substrate, and a plurality of second conductor layers arranged in parallel on the conductive layer via an insulating layer; The first conductor layer and the second conductor layer are selectively and electrically connected to each other via a via hole formed in the insulating layer so as to be spiral, so that the plurality of first conductor layers are two-dimensionally spiral. And a plurality of the second
The inductor is configured so that the conductor layer also has a two-dimensional spiral shape, and the first and second conductor layers are formed between different layers.
A semiconductor device having a configuration in which a signal propagation distance until an interaction is reduced. 2. A semiconductor substrate, a first plurality of conductor layers juxtaposed on the substrate, a second plurality of conductor layers juxtaposed on the layer via an insulating layer, A via hole in the layer, a selected one end of a third conductive layer selected from the first plurality of conductive layers, and a selected one of the second conductive layers from the second plurality of conductive layers A selected one end of a fourth conductor layer is electrically connected through a first via hole opened in the insulating layer, and the other end of the fourth conductor layer is connected to the first plurality of conductors. Electrically connecting one end of a fifth conductor layer selected from the layers via a second via hole formed in the insulating layer, and sequentially performing the first plurality of conductors. An inductor element in which a layer has a two-dimensional spiral shape and the plurality of second conductor layers also have a two-dimensional spiral shape. The semiconductor device characterized by Bei was.