TW557583B - A multi-layer inductor formed in a semiconductor substrate - Google Patents

A multi-layer inductor formed in a semiconductor substrate Download PDF

Info

Publication number
TW557583B
TW557583B TW091121020A TW91121020A TW557583B TW 557583 B TW557583 B TW 557583B TW 091121020 A TW091121020 A TW 091121020A TW 91121020 A TW91121020 A TW 91121020A TW 557583 B TW557583 B TW 557583B
Authority
TW
Taiwan
Prior art keywords
layer
conductive
patent application
item
scope
Prior art date
Application number
TW091121020A
Other languages
Chinese (zh)
Inventor
Samir Chaudhry
Paul Arthur Layman
J Ross Thomson
Mohamed Laradji
Michelle D Griglione
Original Assignee
Agere Syst Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Syst Guardian Corp filed Critical Agere Syst Guardian Corp
Application granted granted Critical
Publication of TW557583B publication Critical patent/TW557583B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A thin-film multi-layer high Q inductor spanning at least three metal layers is formed by forming a plurality of parallel first metal runners on the semiconductor substrate. A plurality of first and second vertical conductive vias are formed in electrical communications with each end of the plurality of metal runners. A plurality of third and fourth conductive vias are formed over the plurality of first and second conductive vias and a plurality of second metal runners are formed interconnecting the plurality of third and fourth conductive vias. The plurality of first metal runners are in a different vertical than the plurality of second metal runners such that the planes intersect. Thus one end of a first metal runner is connected to an overlying end of a second metal runner by way of the first and third vertical conductive vias. The other end of the second metal runner is connected to the next metal one runner by way of the second and fourth vertical conductive vias, forming a continuously conductive structure having a generally helical shape.

Description

557583 A7 _B7__ 五、發明説明（彳） 發明領域 (請先閱讀背面之注意事項再填寫本頁) 本發明是關於一種形成在積體電路基體上的電感，更 具體而言是關於一種其核心跨距積體電路之至少三個金屬 層的電感。 發明背景 目前在對於無線通信與較小無線通信裝置之需要的革 新上針對於無線電通信電子裝置的最佳化與微型化有著相 當的進步。在裝置的操作上這些裝置的被動元件（諸如電 感、電容器與變壓器）扮演一個必須的角色，因此必須努 力去減小此類元件的尺寸並改良其製造效率。 經濟部智慧財產局員工消費合作社印製 在電子通信裝置之效能中扮演不可或缺角色的電感是 一種包含複數個繞線的電磁元件，其通常是由磁金屬或是 絕緣器所組成的核心所圈住。磁核心的使用得到較高的電 感値。該電感係數也會受到線圈匝數目的影響；具體而言 ，電感係數與匝的數目平方成比例。此電感値也受到核心 的半徑與其他物理因素的影響。習知的電感是以螺旋狀的 方式形成（也可稱爲螺線管形）或是環形管。 將操作通信頻率持續配置到較高的頻寬中，電感損耗 會因提高的漩渦電流與集膚效應損耗而增加。爲了使用於 以較低頻率操作的裝置中，可藉由應用特定主動裝置來模 擬電感。但模擬電感在較高頻率上比較困難實現，其具有 有限的動態範圍且會將額外且不理想的雜訊注入操作電路 中 0 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -4- 557583 A7 B7 五、發明説明（2 ) (請先閲讀背面之注意事項再填寫本頁} Q (或是品質因素）是重要的電感價値特徵。Q測量出 電感電抗對有感電阻的比率。當電感電流圖示爲輸入信號 頻率的函數時，高Q電感表現出狹窄的峰値，其中峰値代 表在電感共振時的頻率。高Q電感通常在以窄頻寬操作之 頻率決定電路中是相當重要的。因爲Q値爲有感電阻的反 函數，所以將電阻最小化以提高Q是相當重要的。 經濟部智慧財產局員工消費合作社印製 大部分的個人通信裝置組合有利用半導體技術所製造 的積體電路主動元件，諸如矽或鎵砷化物。先前技藝教導 所發展之特定整合平面電感（包括環形或螺旋形）以達成 與矽爲基礎之積體電路製造處理的相容性。然而，此類平 面電感傾向於在操作頻率上遭受到高度損耗與低Q因素。 這些損耗與低Q因素一般是歸因於因使用薄且相當高電阻 率的導體，而因寄生電容與電阻性損耗所造成的介電損耗 。習知平面電感的另一個缺點是因垂直於半導體基體表面 的磁場線。這些封閉環路磁場線進入該電感之上、之旁與 之下的材料中。介電材料的穿透力提高了電感損耗與降低 了電感的Q因素。同時，除非電感是置於與形成於矽中之 下層主動電路元素有相當距離之處，電感磁場會感生進入 電流而因此瓦解了下層主動元件的操作。 隨著積體電路主動裝置越發展越小且越高速地操作， 互連系統不應增加對裝置信號的處理延遲。當較長的互連 與較小的互連斷面提高了互連電阻時，習知鋁互連金屬化 的使用限制了電路的操作速度。同時，當電路元件數目增 加時，在鋁與矽表面之間的相當小接觸阻抗會產生相當大 本紙張尺度適用中國國家標準（ CNS ) A4規格（210X297公釐) ' " -5- 經濟部智慧財產局員工消費合作社印製 557583 A7 _B7_ 五、發明説明（3 ) 的整體電阻。另外也難以將鋁以高寬高比沉積於穿孔與插 塞中，其中寬高比被界定爲穿孔厚度對直徑的比率。 給定這些缺點，銅便成爲互連的選擇，因爲銅是優於 銘的導體（相較於銘的3.1 micro-ohm其電阻爲1.7 microohm) ， 較不易 受到電子遷移 ，能夠被以較低 的溫度 來沉積 (所以避免裝置參雜物輪廓上的介電效應），且在高寬高 比的插塞中適用爲插塞材料。能夠藉由化學蒸氣沉積、濺 射、電鍍與電解電鍍來形成銅互連。 波紋處理是一種形成主動裝置銅互連的技術。先將溝 形成於介電層的表面中，再將銅材料沉積於其中。通常溝 會被塡滿，需要化學與機械拋光步驟以將表面再平面化。 此處理提供較好的尺寸控制，因爲其可消除在傳統圖樣與 蝕刻互連處理中所產生的尺寸變化。雙波紋處理將波紋處 理延伸，同時從銅中形成下層穿孔與互連溝。先形成穿孔 插塞再形成金屬溝。隨後的金屬沉積步驟塡充穿孔與溝， 形成一完整的金屬層。化學與機械拋光步驟將頂面或是基 體進行平面化。 美國專利案號第6,008，102說明用以形成三度或螺旋狀 電感的處理，其藉由習知的及多個圖樣、鈾刻與沉積步驟 所形成的銅層來形成該電感。利用與溝之形成與塡充不同 的步驟形成有多個互連穿孔並塡充以金屬。 發明槪述 爲了提供進一步半導體基體上與主動裝置相關之電感 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇><297公釐） τγ Λ------IT------ (請先閱讀背面之注意事項再填寫本頁) -6 - 557583 A7 ___ B7_ 五、發明説明（4 ) 的製造發展，提供有用以形成在習知積體電路之金屬層間 電感的架構與處理，其中電感核心區域大於先前技藝的電 感，其導致較高的電感係數値及較高優點的Q特徵。同時 ，根據本發明之學說所形成的電感在積體電路之相當微小 的區域中具有理想的低電阻（及所以高Q )。一種用以形 成此類電感的技術爲雙波紋處理。 根據本發明的一實施例，複數個平行的下方導電條形 成在半導體基體上方，其中已先形成主動元件。第一與第 二垂直導電穿孔口形成在每個下方導電條之第一與第二的 相對邊緣上，且將導電材料沉積於穿孔口中以形成第一與 第二導電穿孔。將兩個額外的穿孔口形成於與第一與第二 導電穿孔的垂直對準中並塡充以金屬以形成第三與第四導 電穿孔。然後形成複數個上方導電條，其中上方導電條的 平面與下方導電條的平面相交，因此一上導電條的第一邊 緣位在下方導電條之第一邊緣的上方，且兩個邊緣是藉由 第一與第三導電穿孔而互連。上方導電條的第二邊緣位在 下個平行下方導電條之第二邊緣的上方，且這些邊緣是藉 由第二與第四導電穿孔成電性連接。所以該電感包含各別 繞線的螺旋。 根據本發明的另一個實施例，複數個平行的下方波紋 溝或窗形成在置於現存基體上之介電層的第一多層堆疊中 。該溝塡充以銅。兩個垂直的導電穿孔形成於與每個下方 波紋溝之每個邊緣的電性通信中，且銅沉積於其中。接著 ，根據雙波紋處理，一另外複數個穿孔與上方溝形成於置 本紙張尺度適用中國國家標準（ CNS ) A4規格（210 X 297公釐） ' -7- I"^--:‘-----Λ-- (請先閲讀背面之注意事項再填寫本頁) 、1Τ 經濟部智慧財產局員工消費合作社印製 557583 A7 B7 五、發明説明（5 ) (請先閲讀背面之注意事項再填寫本頁) 於第一堆疊上之絕緣層的第二多層堆疊中。下方波紋溝的 垂直平面與上方波紋溝的垂直平面相交。與每個上方溝相 關的一對穿孔垂直對準於先前形成之連接於下方溝的穿孔 。此另外的複數個穿孔與上方溝被塡充以銅，最好是利用 電鍍，然後將該表面進行化學與機械拋光步驟。因爲下方 與上方波紋溝的平面相交，所以形成由導電穿孔所互連之 上方與下方波紋溝的螺旋狀接續。 簡單圖示說明 鑒於以下的本發明說明與附圖可使本發明得到更輕易 的了解以及進一步的優點與使用，其中： 圖1至圖9爲根據本發明連續製造步驟中一製造實施 例的電感結構斷面圖。 圖10至圖12顯示根據本發明學說所形成之替代電感 結構的俯視圖。 經濟部智慧財產局員工消費合作社印製 根據一般實際操作，並未限制各種裝置特徵，但強調 與本發明相關的特定特徵。在整個圖形與內文中參考符號 代表相似的元素。 元件對照表 20 阻障層 22 絕緣層 24 硬遮罩層 3〇 溝（窗） 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -8 - 557583 A7 B7 五、發明説明（6 ) 經濟部智慧財產局員工消費合作社印製 32 阻障與種晶層 34 金屬-1澆道層 40 阻障層 42 絕緣層 48 蝕刻停止層 50 絕緣層 52 硬遮罩層 60 穿孔口 62 穿孔口 64 阻障與種晶層 65 導電穿孔 66 導電穿孔 67 金屬-2穿孔層 68 金屬-2穿孔層 70 阻障層 72 絕緣層 74 鈾刻停止層 76 絕緣層 78 硬遮罩層 84 穿孔口 86 穿孔口 100 溝 101 端 102 端 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -9- 557583 A 7 B7 五、發明説明（7 ) 106 導 電 穿 孔 107 導 電 穿 孔 108 金 屬 -3 穿 孔 層 109 金 屬 -3 穿 孔 層 110 金 屬 -3 澆 道 120 導 電 堆 疊 122 導 電 堆 疊 (請先閲讀背面之注意事項再填寫本頁) 本發明的詳細說明 經濟部智慧財產局員工消費合作社印製 用以形成根據本發明之電感的處理開始於圖1，其中複 數個絕緣層形成在現有的積體電路基體上，其傳統上包括 複數個主動元件。典型而言，在習知製造處理的此時，主 動裝置沒有形成金屬互連層；只有形成用以存取主動裝置 區的穿孔或窗。阻障層20置於半導體基體的表面上，且最 好是以鉬、鉬氮化物、鈦或鈦氮化物所形成。其次在阻障 層2〇上形成絕緣層22，其最好是從相當低的介電常數材料 所形成。低介電的二氧化矽、黑鑽石與珊瑚適用於作爲絕 緣層22。二氧化矽的相關介電常數爲約3.9。所以低的介電 常數一般被視爲小於3.〇。此低介電常數材料會減少內層的 電容以及信號間的電位串音，雖然在另一個實施例中能夠 使用習知的二氧化矽。能夠利用化學蒸氣沉積來形成阻障 層2 0與絕緣層2 2。 絕緣層22上方之層24包含一個二氧化矽的硬遮罩。 爲了蝕刻硬遮罩下方的一層或多層，將光阻施加在硬遮罩 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -10- 557583 A7 B7 五、發明説明（8 (請先閲讀背面之注意事項再填寫本頁} 上，圖樣出光阻，然後將該圖樣從光阻轉移到硬遮罩。將 光阻移除並利用硬遮罩圖樣執行蝕刻步驟。此處理有利於 提供較好之蝕刻特徵的尺寸控制。除了硬遮罩，能夠利用 習知的光阻圖樣與鈾刻步驟。如圖2中所示，在任一例中 ,利用適當的蝕刻劑將窗或溝3 0形成於絕緣層22與硬遮 罩層24中。然後藉由蝕刻將在溝30底部之阻障層20的暴 露區移除。一般而言，圖樣與蝕刻步驟不會允許尖角結構 形狀的形成，所以從上方俯視來看，窗與溝是典型的圓形 、橢圓形、或具有相當直的邊緣且在邊緣間具有圓角。 回到圖3，沉積出阻障與種晶層32。典型而言，這是 由兩個步驟所完成的。首先將阻障材料濺射到溝30中。鉬 、鉬氮化物、鈦與鈦氮化物爲阻障層的適用材料。其次， 最好是利用濺射沉積出薄的銅種晶層。該種晶層必須作爲 電鍍銅的開始層。也可以利用習知的化學蒸氣沉積與電鍍 處理來沉積阻障與種晶層32的阻障材料與種晶材料。最好 是利用電鍍銅來形成金屬-1澆道層3 4。電鍍特別有益處， 經濟部智慧財產局員工消費合作社印製 因爲它能夠在低溫以及相當低的成本下執行。此低溫沉積 的特徵是有利的，它可避免半導體基體之主動區中參雜物 輪廓的改變。然後將此基體進行化學機械拋光以從除了金 屬-1澆道34內之外的所有區中移除電鍍銅。用以在絕緣層 中沉積銅層的處理是爲熟知的波紋處理。其提供良好的尺 寸控制，因爲其消除了習知金屬圖樣與蝕刻處理中產生的 變化，其中穿孔與互連是形成於兩個分開的步驟中。波紋 處理與雙波紋處理的細節將於以下的參考中討論，結合於 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -11 - 557583 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（9 ) 文中作爲參考：C. K. Hu et. al.，Proceedings MRS Symposium on VLSI, vol. 5，p.369 ( 1990) ; B. Luther et. al·，Proceedings VMIC, vol.10,p.1 5 ( 1994 ) ； D. Edelstein, Proceedings ECS Mtg.，νο1·96-2，ρ· 33 5 ( 1 995 ) o 在特定電路組態中，必須將金屬-1澆道34連接到基體 中的底層主動裝置區。例如金屬-1澆道的一端作爲用以連 接到電路中之其他元件的電感終端。這可藉由先形成穿孔 口的雙波紋處理來完成，該口是用以將金屬-1澆道的一端 連接到底層裝置區的。第二個步驟形成窗30，第三個步驟 同時塡充穿孔口與溝30以形成導電穿孔與金屬-1澆道34 。藉由此技術，金屬-1澆道34會連接到底層裝置區。此導 電穿孔也可藉由習知的處理來形成，然後將金屬-1澆道34 形成於其中的電性接點中。 如圖4中所示，在金屬-1澆道34與層20、22與24的 鄰近區上形成一個四層的堆疊。如圖所示先沉積阻障層40 (最好是鈦氮化物）。最好具有相當低介電常數的絕緣層 42形成在阻障層40上，且包含低介電常數的二氧化矽、黑 鑽石或珊瑚。低介電常數材料的使用有利於減少內層的電 容以及內層串音，但是絕緣層不需要包含低介電材料。例 如由氮化矽所形成的蝕刻停止層48形成在絕緣層42的上 方。另一個絕緣層5 0 (最好具有低介電常數）形成在蝕刻 停止層48上方。硬遮罩層52形成在絕緣層50的上方。如 上文所述，可以利用習知的光阻與遮罩材料來取代硬遮罩 層5 2 〇 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） —AwIT (請先閲讀背面之注意事項再填寫本頁) -12- 557583 A7 B7 五、發明説明（1〇 ) 來到圖5，應用硬遮罩層52的遮罩步驟定義出穿孔口 60與62形成的區域，向下延伸至阻障層40。藉由蝕刻將 阻障層40之暴露於穿孔口 60與62的區移除掉。此時在製 造處理中，積體電路可能有其他區域需要金屬-2層與底層 裝置區互連，所以當形成穿孔口 60與62時，會圖樣與蝕 刻出這些用於互連的穿孔口。應該注意到的是此時如圖5 中的金屬-1澆道34可能被定位平行於半導體基體的正面（ 雖然並不一定需要），所以穿孔口 60 (以及以下將討論的 所有元素）與穿孔口 62 (以及所有形成於其上的元素）是 位於相同的垂直平面中。見圖1 〇。 如圖6中所示，阻障與種晶層64沉積於穿孔口 60與 62中。此處理與材料和圖3有關的阻障與種晶層32相同。 然後最好是在穿孔口 60與62中電鍍銅，藉由化學與機械 拋光步驟以將頂面平面化。此時，穿孔口 60與62之下部 的銅區可稱爲導電穿孔65與66。穿孔口 60與62之上部中 的銅材料被稱爲金屬-2穿孔層67與68。 如圖7中所示，多層的堆疊形成在現存的層上，其中 各層的材料最好是與圖4相關之多層堆疊所使用的相同。 特別的是，隨後形成的層包括阻障層70、絕緣層72 (最好 是包含具有低介電常數的材料）、蝕刻停止層74、絕緣層 76 (最好是包含具有低介電常數的材料）與硬遮罩層78。 穿孔口 84與86形成於其中，利用硬遮罩層78來圖樣與蝕 刻表面。將阻障層70之暴露於穿孔口 84與86的區移除掉 。此時金屬-2穿孔層67與68的頂面分別與穿孔口 84與 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' "~ -13- (請先閲讀背面之注意事項再填寫本頁) 、π557583 A7 _B7__ V. Description of the invention (彳) Field of invention (please read the notes on the back before filling out this page) The present invention relates to an inductor formed on the integrated circuit substrate, and more specifically to a core circuit Inductance from at least three metal layers of the integrated circuit. BACKGROUND OF THE INVENTION There is currently considerable progress in the optimization and miniaturization of radio communication electronic devices in the need for wireless communication and smaller wireless communication devices. The passive components of these devices (such as inductors, capacitors, and transformers) play a necessary role in the operation of the devices, and efforts must be made to reduce the size of such components and improve their manufacturing efficiency. Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, an inductor that plays an integral role in the performance of electronic communication devices is an electromagnetic component containing multiple windings, which is usually composed of magnetic metal or insulators. Encircle. The use of a magnetic core results in a higher inductance. The inductance is also affected by the number of turns in the coil; specifically, the inductance is proportional to the square of the number of turns. This inductance is also affected by the core's radius and other physical factors. Conventional inductors are formed in a spiral shape (also known as a solenoid shape) or a toroidal tube. If the operating communication frequency is continuously configured to a higher bandwidth, the inductance loss will increase due to the increased eddy current and skin effect loss. For use in devices operating at lower frequencies, the inductance can be simulated by applying a specific active device. However, analog inductors are more difficult to implement at higher frequencies. They have a limited dynamic range and inject additional and undesired noise into the operating circuit. 0 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm). -5- 557583 A7 B7 V. Description of the invention (2) (Please read the precautions on the back before filling out this page} Q (or quality factor) is an important value and inductance characteristic of the inductor. Q measures the inductance and inductance of the inductor against the inductive resistance When the inductor current is plotted as a function of the frequency of the input signal, the high-Q inductor exhibits a narrow peak chirp, where the peak chirp represents the frequency at which the inductor resonates. The high-Q inductor is usually determined at a frequency that operates with a narrow bandwidth. It is very important in the circuit. Because Q 値 is the inverse function of the inductive resistance, it is very important to minimize the resistance to improve Q. The Intellectual Property Bureau of the Ministry of Economic Affairs, the employee consumer cooperative, printed most of the personal communication device combinations for use. Active semiconductor integrated circuit components such as silicon or gallium arsenide. Specific integrated planar inductors (including toroidal or (Spin) to achieve compatibility with silicon-based integrated circuit manufacturing processes. However, such planar inductors tend to suffer from high losses and low Q factors at operating frequencies. These losses and low Q factors are generally attributed to Dielectric losses due to parasitic capacitance and resistive losses due to the use of thin and relatively high resistivity conductors. Another disadvantage of the known planar inductor is due to the magnetic field lines perpendicular to the surface of the semiconductor substrate. These closed loops The magnetic field lines of the circuit enter the material above, beside and below the inductor. The penetration of the dielectric material increases the inductance loss and reduces the Q factor of the inductance. At the same time, unless the inductor is placed in and formed in silicon There is a considerable distance between the elements of the lower active circuit, the inductive magnetic field will induce the incoming current and thus disrupt the operation of the lower active components. As the integrated circuit active device becomes smaller and smaller and operates at higher speeds, the interconnect system should not increase Delay in processing device signals. The use of conventional aluminum interconnect metallization limits the circuit when longer interconnects and smaller interconnect sections increase interconnect resistance Operating speed. At the same time, when the number of circuit components increases, the relatively small contact resistance between the aluminum and silicon surfaces will produce a considerable paper size. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) '" -5 -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 557583 A7 _B7_ V. The overall resistance of the invention description (3). In addition, it is difficult to deposit aluminum in the perforations and plugs with an aspect ratio, where the aspect ratio is defined as Ratio of perforation thickness to diameter. Given these shortcomings, copper becomes the interconnect of choice because copper is a better conductor than Ming (its resistance is 1.7 microohm compared to Ming's 3.1 micro-ohm) and is less susceptible to electron migration. , Can be deposited at a lower temperature (so avoid the dielectric effect on the contours of device impurities), and is suitable as a plug material in plugs with high aspect ratio. Copper interconnects can be formed by chemical vapor deposition, sputtering, electroplating, and electrolytic plating. Corrugation is a technique for forming copper interconnects for active devices. Trenches are formed in the surface of the dielectric layer before a copper material is deposited therein. The trenches are usually filled and chemical and mechanical polishing steps are required to re-planarize the surface. This process provides better dimensional control because it eliminates dimensional changes that occur in traditional pattern and etch interconnect processes. The double corrugation process extends the corrugation process while forming lower layers of perforations and interconnect trenches from the copper. A perforated plug is formed before a metal groove is formed. The subsequent metal deposition step is filled with perforations and trenches to form a complete metal layer. Chemical and mechanical polishing steps planarize the top surface or substrate. U.S. Patent No. 6,008,102 describes a process for forming a three-degree or spiral inductor which is formed by a conventional copper layer formed by a plurality of patterning, uranium engraving, and deposition steps. A plurality of interconnected through-holes are formed and filled with metal using steps different from the formation of trenches and filling. Description of the invention In order to provide further inductors related to active devices on the semiconductor substrate, the paper size applies the Chinese National Standard (CNS) A4 specification (21〇 > < 297 mm) τγ Λ ------ IT --- --- (Please read the precautions on the back before filling out this page) -6-557583 A7 ___ B7_ V. Manufacturing development of invention description (4) provides a framework useful for forming the interlayer metal inductors in conventional integrated circuits And processing, where the core area of the inductor is larger than the inductance of the prior art, which results in a higher inductance coefficient and higher Q characteristics. At the same time, the inductance formed according to the teachings of the present invention has ideally low resistance (and therefore high Q) in a relatively small area of the integrated circuit. One technique used to form such inductors is double ripple processing. According to an embodiment of the present invention, a plurality of parallel lower conductive strips are formed above the semiconductor substrate, and an active device has been formed first. First and second vertical conductive perforations are formed on the opposite edges of the first and second conductive strips below, and conductive material is deposited in the perforations to form the first and second conductive perforations. Two additional perforations are formed in vertical alignment with the first and second conductive vias and are filled with metal to form the third and fourth conductive vias. A plurality of upper conductive strips are then formed, wherein the plane of the upper conductive strip and the plane of the lower conductive strip intersect, so the first edge of an upper conductive strip is positioned above the first edge of the lower conductive strip, and the two edges are formed by The first and third conductive vias are interconnected. The second edge of the upper conductive strip is located above the second edge of the next parallel lower conductive strip, and these edges are electrically connected through the second and fourth conductive vias. So the inductor contains spirals that are individually wound. According to another embodiment of the invention, a plurality of parallel lower corrugated trenches or windows are formed in a first multilayer stack of dielectric layers placed on an existing substrate. The gully was filled with copper. Two vertical conductive vias are formed in electrical communication with each edge of each underlying corrugated trench, and copper is deposited therein. Next, according to the double corrugation treatment, a plurality of other perforations and upper grooves are formed on the paper. The standard of the Chinese paper (CNS) A4 (210 X 297 mm) is applied. '-7- I " ^-:'- --- Λ-- (Please read the precautions on the back before filling out this page), Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 557583 A7 B7 V. Description of the invention (5) (Please read the precautions on the back before (Fill in this page) in a second multilayer stack with an insulating layer on the first stack. The vertical plane of the lower corrugated groove intersects the vertical plane of the upper corrugated groove. A pair of perforations associated with each of the upper trenches is aligned vertically with the previously formed perforations connected to the lower trenches. The additional plurality of perforations and upper trenches are filled with copper, preferably by electroplating, and the surface is then subjected to chemical and mechanical polishing steps. Because the planes of the lower and upper corrugated grooves intersect, a spiral connection of the upper and lower corrugated grooves interconnected by conductive vias is formed. In view of the following description of the present invention and the accompanying drawings, the present invention can be more easily understood, and further advantages and applications can be obtained, in which: FIGS. 1 to 9 are inductors according to a manufacturing embodiment in the continuous manufacturing steps of the present invention. Sectional view of structure. Figures 10 to 12 show top views of alternative inductor structures formed in accordance with the teachings of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs According to general practical operations, various device features are not limited, but specific features related to the present invention are emphasized. Reference symbols represent similar elements throughout the figures and text. Component comparison table 20 Barrier layer 22 Insulation layer 24 Hard mask layer 30 grooves (windows) This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) -8-557583 A7 B7 V. Description of the invention (6 ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 32 Barrier and seed layer 34 Metal-1 sprue layer 40 Barrier layer 42 Insulating layer 48 Etching stop layer 50 Insulating layer 52 Hard mask layer 60 Perforated opening 62 Perforated opening 64 Barrier and seed layer 65 Conductive perforation 66 Conductive perforation 67 Metal-2 perforated layer 68 Metal-2 perforated layer 70 Barrier layer 72 Insulating layer 74 Uranium etch stop layer 76 Insulating layer 78 Hard mask layer 84 Perforation opening 86 Perforation Mouth 100 Ditch 101 End 102 End (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) -9- 557583 A 7 B7 V. Description of the invention (7 ) 106 conductive perforation 107 conductive perforation 108 metal-3 perforated layer 109 metal-3 perforated layer 110 metal-3 runner 120 conductive stack 122 conductive stack (please read the note on the back first Please fill in this page again) Detailed description of the present invention The process printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to form an inductor according to the present invention begins in FIG. 1 in which a plurality of insulating layers are formed on an existing integrated circuit substrate , Which traditionally includes a plurality of active elements. Typically, at the time of the conventional manufacturing process, the active device does not form a metal interconnect layer; only a through-hole or window is formed to access the active device area. The barrier layer 20 is placed on the surface of the semiconductor substrate, and is preferably formed of molybdenum, molybdenum nitride, titanium, or titanium nitride. Next, an insulating layer 22 is formed on the barrier layer 20, which is preferably formed of a relatively low dielectric constant material. Low dielectric silicon dioxide, black diamond and coral are suitable for use as the insulating layer 22. The relative dielectric constant of silicon dioxide is about 3.9. Therefore, a low dielectric constant is generally regarded as less than 3.0. This low dielectric constant material reduces the capacitance of the inner layer and the potential crosstalk between the signals, although conventional silicon dioxide can be used in another embodiment. The barrier layer 20 and the insulating layer 22 can be formed by chemical vapor deposition. The layer 24 above the insulating layer 22 contains a hard mask of silicon dioxide. In order to etch one or more layers under the hard mask, a photoresist is applied to the hard mask. The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -10- 557583 A7 B7 V. Description of the invention (8 (Please First read the precautions on the back before filling out this page}, the pattern is a photoresist, and then transfer the pattern from the photoresist to the hard mask. Remove the photoresist and use the hard mask pattern to perform the etching step. This process is helpful Better size control of etching features. Except for hard masks, conventional photoresist patterns and uranium etch steps can be used. As shown in Figure 2, in either case, a window or trench 30 is formed with a suitable etchant. In the insulating layer 22 and the hard mask layer 24. Then, the exposed area of the barrier layer 20 at the bottom of the trench 30 is removed by etching. In general, the pattern and etching steps do not allow the formation of sharp-cornered structures, So when viewed from above, windows and trenches are typically round, oval, or have fairly straight edges with rounded corners. Back to Figure 3, a barrier and seed layer 32 is deposited. Typical and In other words, this is done in two steps First, the barrier material is sputtered into the trench 30. Molybdenum, molybdenum nitride, titanium, and titanium nitride are suitable materials for the barrier layer. Second, it is preferable to deposit a thin copper seed layer by sputtering. The seed layer must be used as the starting layer for electroplating copper. The conventional chemical vapor deposition and electroplating processes can also be used to deposit the barrier material and seed material for the barrier layer and seed layer 32. It is preferable to use electroplating copper to form Metal-1 sprue layer 3. 4. Electroplating is particularly beneficial. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics because it can be performed at low temperatures and at a relatively low cost. This low temperature deposition feature is advantageous and it avoids semiconductor Changes in the profile of the impurities in the active area of the substrate. The substrate is then chemically mechanically polished to remove electroplated copper from all areas except the metal-1 runner 34. Used to deposit a copper layer in the insulating layer The treatment is a well-known corrugation treatment. It provides good dimensional control because it eliminates the changes in the conventional metal pattern and etching process, where the perforations and interconnections are formed in two separate steps Medium. The details of the corrugation treatment and the double corrugation treatment will be discussed in the following references, combined with the paper standard applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -11-557583 Staff Consumption of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative A7 B7 V. Description of the invention (9) The text is for reference: CK Hu et. Al., Proceedings MRS Symposium on VLSI, vol. 5, p.369 (1990); B. Luther et. Al., Proceedings VMIC , vol.10, p. 1 5 (1994); D. Edelstein, Proceedings ECS Mtg., νο 1.96-2, ρ · 33 5 (1 995) o In a specific circuit configuration, metal-1 must be cast The track 34 is connected to the underlying active device area in the matrix. For example, one end of a metal-1 runner is used as an inductor termination for connecting to other components in the circuit. This can be accomplished by a double corrugation process that first forms a perforated opening that connects one end of the metal-1 runner to the underlying device area. The second step forms the window 30, and the third step simultaneously fills the perforated opening and the trench 30 to form a conductive perforation and a metal-1 sprue 34. With this technique, the metal-1 runner 34 is connected to the underlying device area. This conductive electroporation can also be formed by a conventional process, and then a metal-1 runner 34 is formed in the electrical contact therein. As shown in Fig. 4, a four-layer stack is formed on the vicinity of the metal-1 runner 34 and layers 20, 22, and 24. As shown, a barrier layer 40 (preferably titanium nitride) is deposited first. It is preferable that an insulating layer 42 having a relatively low dielectric constant is formed on the barrier layer 40 and contains silicon dioxide, black diamond, or coral having a low dielectric constant. The use of a low dielectric constant material is beneficial to reduce the capacitance of the inner layer and the crosstalk of the inner layer, but the insulating layer does not need to contain a low dielectric material. An etch stop layer 48 made of, for example, silicon nitride is formed above the insulating layer 42. Another insulating layer 50 (preferably having a low dielectric constant) is formed over the etch stop layer 48. A hard mask layer 52 is formed above the insulating layer 50. As mentioned above, conventional photoresist and masking materials can be used to replace the hard masking layer 5 2 〇 This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) —AwIT (please read the back first Please note this page and fill in this page again) -12- 557583 A7 B7 V. Description of the invention (10) Come to Figure 5, apply the masking step of the hard masking layer 52 to define the area formed by the perforations 60 and 62, downward Extends to the barrier layer 40. The areas of the barrier layer 40 exposed to the through holes 60 and 62 are removed by etching. At this time in the manufacturing process, there may be other areas of the integrated circuit that require the metal-2 layer to be interconnected with the underlying device area, so when the perforations 60 and 62 are formed, these perforations for interconnection are patterned and etched. It should be noted at this time that the metal-1 sprue 34 as shown in FIG. 5 may be positioned parallel to the front surface of the semiconductor substrate (though not necessarily required), so the perforation 60 (and all elements discussed below) and the perforation The port 62 (and all elements formed thereon) is located in the same vertical plane. See Figure 10. As shown in FIG. 6, a barrier and seed layer 64 is deposited in the perforations 60 and 62. This process is the same as the material and the barriers related to FIG. 3 are the same as the seed layer 32. Copper is then preferably plated in the perforations 60 and 62, and the top surface is planarized by chemical and mechanical polishing steps. At this time, the copper areas under the perforations 60 and 62 may be referred to as conductive perforations 65 and 66. The copper material in the upper portions of the perforations 60 and 62 is referred to as metal-2 perforated layers 67 and 68. As shown in FIG. 7, a multi-layer stack is formed on an existing layer, and the materials of each layer are preferably the same as those used in the multi-layer stack related to FIG. In particular, the subsequently formed layers include a barrier layer 70, an insulating layer 72 (preferably containing a material having a low dielectric constant), an etch stop layer 74, and an insulating layer 76 (preferably containing a material having a low dielectric constant) Material) with hard mask layer 78. Perforations 84 and 86 are formed therein, and a hard mask layer 78 is used to pattern and etch the surface. The areas of the barrier layer 70 exposed to the perforations 84 and 86 are removed. At this time, the top surfaces of the metal-2 perforated layers 67 and 68 and the perforated opening 84 and the paper size are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) '" ~ -13- (Please read the note on the back first (Please fill in this page again), π

Aw. 經濟部智慧財產局員工消費合作社印製 557583 A7 B7 五、發明説明（H ) (請先閱讀背面之注意事項再填寫本頁) 86對準。接著如圖8中所示在基體中形成溝100。溝100 向下延伸至蝕刻停止層74。在較佳實施例中，爲了在蝕刻 停止層74有效地停止蝕刻處理，應監督蝕刻處理以分析從 材料所蝕刻出來的副產品。在此例中，當偵測到蝕刻停止 層74的材料時便結束蝕刻處理。因此，溝1 00僅向下延伸 至蝕刻停止層74。應該注意到的是溝100與金屬_1澆道34 不在同一個平面中。溝100的一端101反而在圖8的前景 中，而一端102在背景中。此方位淸楚地顯示於圖10中。 所以可以看到在溝1 00中後來形成的導電材料，如下文中 所述，將互連兩個連續的金屬-1澆道。 經濟部智慧財產局員工消費合作社印製 如圖9中所示，阻障與種晶層1 04被沉積以限制銅擴 散進入絕緣層以及提供隨後之銅電鍍處理的種晶材料。當 蝕刻停止層74作爲阻障用途時，並不需要沿著溝100的底 面形成阻障層，且不需要電鍍種晶層，因爲銅將橫向地從 第三階穿孔84與86的側壁進行電鍍。然後沉積銅，最好 是利用電鍍，如圖9中所示，塡充穿孔口 84與86以形成 導電穿孔106與107、金屬-3穿孔層108與10 9及金屬-3 澆道1 1 〇。然後將此結構進行化學機械拋光以從不理想的區 域移除銅並將頂面平面化。 如上文中所述，金屬-3穿孔層108與金屬-1澆道34不 在同一個垂直平面中。再者，如圖10的俯視圖中所示，有 複數個平行定位的金屬-1澆道34與金屬-3澆道110，其中 互連的結構形成一個Z形的結構。在此實施例中，金屬-1 澆道34爲I形，根據上文，金屬-1與金屬-3澆道34與 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐厂 -14 - 557583 A7 B7 五、發明説明（12 ) 108的組合代表了字母“Z” 。所以金屬-3澆道108透過垂 (請先閲讀背面之注意事項再填寫本頁) 直的導電堆疊120 (包含導電穿孔66、金屬-2穿孔層68、 導電穿孔107以及金屬-3穿孔層109)以及垂直的導電堆 疊122 (包含導電穿孔65、金屬-2穿孔層67、導電穿孔 106以及金屬-3穿孔層108)作爲連接連續金屬-1澆道34 的互連結構。在另一個實施例中，金屬-1與金屬-3澆道34 與1 08是互連於Z字形圖樣中以形成連續的導電結構。見 圖1 1 〇 在圖12的實施例中，金屬-1澆道34爲L形，其短段 向後延伸以接觸到金屬-3澆道108，藉由垂直的導電堆疊 120，其包含導電穿孔66、金屬-2穿孔層68、導電穿孔 107以及金屬_3穿孔層109。金屬-3澆道108也爲L形，其 短段電性連接於鄰近的金屬-1澆道34，透過垂直的導電堆 疊122，其包含導電穿孔65、金屬-2穿孔層67、導電穿孔 106以及金屬-3穿孔層108。 經濟部智慧財產局員工消費合作社印製 雖然圖形與文中的附屬說明顯示出在積體電路中，金 屬-1與金屬_3層中電感之底部與頂部金屬層的配置，也能 夠應用本發明的發明特徵以使得電感跨距其它的金屬層， 例如繞線的底段能夠置於金屬-2層間，而繞線的頂段能夠 置於金屬-4層或金屬-5層之間。其他的實施例中，其中跨 距不同的金屬層與不同數量的金屬層被視爲屬於本發明的 範圍內。再者，雖然在一實施例中，根據本發明的電感是 利用波紋處理所形成的，但本發明不受限於此技術的使用 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15- 557583 A7 B7 五、發明説明（13 ) (請先閲讀背面之注意事項再填寫本頁) 雖然根據本發明的電感已說明是以波紋處理所形成的 ，但本發明不受限於此。也可以利用習知的金屬沉積與触 刻步驟來形成電感，其中形成頂部與底部繞線段的金屬層 是藉由跨距至少3個金屬層的垂直穿孔來互連，即至少一 個金屬層沒有被用來形成繞線段的頂部或底部。 有利的是，根據本發明之學說所形成的多層電感與習 知的CMOS逆流（即互連）處理相容，且在CMOS裝置的 製造處理期間不需要任何另外的遮罩步驟。因爲該導體結 構是由銅所形成，所得到的導體會比以鋁所形成的導體具 有較低的電阻以及較高的Q。較大的電感斷面區域導因於 在基體之不同階上金屬層的使用（例如金屬-1至金屬-3或 金屬-3至金屬-5)且會產生較高的電感係數値。如上文之 處理步驟所顯示，該電感可高度整合於具有其他主動元素 的晶片上或是整合爲一般基體上架構之多模組裝置的一部 份。在電感結構中較少導電材料的使用會降低漩渦電流的 損耗。同時，磁性電路線會因精巧的電感結構而更集中， 而因此提高其電感係數並減少積體電路之最近區上的效應 經濟部智慧財產局員工消費合作社印製 〇 一種建構與處理已說明用以形成半導體基體上之薄膜 多層高Q電感是有用的。雖然已說明本發明的特定應用， 文中所揭露的原則提供一個用以藉由各種方式與各種電路 結構來實施本發明的基礎。在本發明的範圍內可進行各種 修改， 包括使用任何兩金屬層來形成電感導體。本發明只受 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' -16· 557583 A7 B7 五、發明説明（14 到以下申請專利範圍的限制。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -17-Aw. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 557583 A7 B7 V. Description of Invention (H) (Please read the precautions on the back before filling this page) 86 Alignment. Grooves 100 are then formed in the matrix as shown in FIG. 8. The trench 100 extends down to the etch stop layer 74. In the preferred embodiment, in order to effectively stop the etching process at the etch stop layer 74, the etching process should be monitored to analyze by-products etched from the material. In this example, when the material of the etch stop layer 74 is detected, the etching process is ended. Therefore, the trench 100 only extends down to the etch stop layer 74. It should be noted that the trench 100 and the metal_1 runner 34 are not in the same plane. One end 101 of the trench 100 is in the foreground in Fig. 8 and the other end 102 is in the background. This orientation is clearly shown in FIG. 10. So it can be seen that the conductive material formed later in the trench 100 will interconnect two consecutive metal-1 sprues as described below. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs As shown in Figure 9, a barrier and seed layer 104 is deposited to limit the diffusion of copper into the insulating layer and to provide a seed material for subsequent copper electroplating. When the etch stop layer 74 is used as a barrier, there is no need to form a barrier layer along the bottom surface of the trench 100, and no plating seed layer is needed, because copper will be plated laterally from the sidewalls of the third-stage perforations 84 and 86. . Copper is then deposited, preferably by electroplating. As shown in FIG. 9, perforated openings 84 and 86 are filled to form conductive perforations 106 and 107, metal-3 perforated layers 108 and 109, and metal-3 runner 1 1 〇 . This structure is then chemically mechanically polished to remove copper from undesired areas and planarize the top surface. As described above, the metal-3 perforated layer 108 and the metal-1 runner 34 are not in the same vertical plane. Furthermore, as shown in the top view of Fig. 10, there are a plurality of metal-1 runners 34 and metal-3 runners 110 positioned in parallel, wherein the interconnected structure forms a Z-shaped structure. In this embodiment, the metal-1 sprue 34 is I-shaped. According to the above, the metal-1 and metal-3 sprues 34 and the paper size apply the Chinese National Standard (CNS) A4 specification (210X297 mm factory-14). -557583 A7 B7 V. Description of the invention (12) The combination of 108 represents the letter "Z". Therefore, the metal-3 runner 108 is vertical (please read the precautions on the back before filling this page) straight conductive stack 120 (including Conductive via 66, metal-2 via layer 68, conductive via 107, and metal-3 via layer 109) and vertical conductive stack 122 (including conductive via 65, metal-2 via layer 67, conductive via 106, and metal-3 via layer 108) as an interconnect structure connecting continuous metal-1 runners 34. In another embodiment, metal-1 and metal-3 runners 34 and 108 are interconnected in a zigzag pattern to form a continuous conductive structure See Figure 1 10. In the embodiment of FIG. 12, the metal-1 runner 34 is L-shaped and its short section extends backward to contact the metal-3 runner 108. The vertical conductive stack 120 contains conductive Perforation 66, metal-2 perforated layer 68, conductive perforation 107, and metal_3 perforated layer 109. Metal- The runner 3 is also L-shaped, and its short section is electrically connected to the adjacent metal-1 runner 34. Through the vertical conductive stack 122, it includes a conductive via 65, a metal-2 via layer 67, a conductive via 106, and a metal. -3 perforated layer 108. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, although the graphics and the accompanying instructions in the text show the configuration of the bottom and top metal layers of the inductor in the metal-1 and metal_3 layers, The inventive features of the present invention can also be applied so that the inductor spans other metal layers, for example, the bottom section of the winding can be placed between the metal-2 layers, and the top section of the winding can be placed on the metal-4 layer or metal-5 layer. In other embodiments, metal layers with different spans and different numbers of metal layers are considered to be within the scope of the present invention. Furthermore, although in one embodiment, the inductor according to the present invention uses ripples Formed by processing, but the present invention is not limited to the use of this technology. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -15- 557583 A7 B7 V. Description of the invention (13) (Please read first Note on the back Please fill in this page again) Although the inductor according to the present invention has been described as being formed by a corrugation process, the present invention is not limited to this. The inductor can also be formed by the conventional metal deposition and etching steps, in which the top is formed The metal layer with the bottom winding segment is interconnected by vertical perforations spanning at least 3 metal layers, ie at least one metal layer is not used to form the top or bottom of the winding segment. Advantageously, according to the teachings of the present invention The resulting multilayer inductor is compatible with conventional CMOS countercurrent (ie, interconnect) processing and does not require any additional masking steps during the manufacturing process of the CMOS device. Because the conductor structure is formed of copper, the resulting conductor will have a lower resistance and a higher Q than a conductor made of aluminum. The larger inductance cross-sectional area is due to the use of metal layers (eg, metal-1 to metal-3 or metal-3 to metal-5) at different steps of the substrate and will result in higher inductance 値. As shown in the processing steps above, the inductor can be highly integrated on a chip with other active elements or integrated as part of a multi-module device structured on a general substrate. The use of less conductive materials in inductive structures reduces the losses in eddy currents. At the same time, magnetic circuit lines will be more concentrated due to the delicate inductive structure, thus increasing its inductance and reducing the effect on the nearest area of the integrated circuit. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is useful to form thin film multilayer high Q inductors on a semiconductor substrate. Although specific applications of the invention have been described, the principles disclosed herein provide a basis for implementing the invention in various ways and various circuit structures. Various modifications are possible within the scope of the invention, including the use of any two metal layers to form the inductive conductor. The present invention is only subject to the Chinese standard (CNS) A4 size (210X297 mm) of this paper size. '-16 · 557583 A7 B7 V. Description of the invention (14 to the following patent application limits. (Please read the precautions on the back first) (Fill in this page again) The paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to the Chinese National Standard (CNS) A4 (210X 297 mm) -17-

Claims (1)

557583 A8 B8 C8 D8 六、申請專利範圍1 1. 一種形成積體電路結構的方法，包含： 形成具有上表面的半導體基體； 在上表面上形成多個導體層；及 將兩個導體層互連以形成螺旋狀電感結構，其中在兩 個互連的導體層之間至少有一個未連接的導體層。 2. 根據申請專利範圍第1項所述之方法，其中互連的兩 個導體層包含複數個上方與下方導電條，及其中複數個上 方與下方導電條是位於相交的垂直平面中，其中複數個上 方導電條之第一條的第一端置於複數個下方導電條之第一 條的第一端上方，及其中複數個上方導電條之第一條的第 二端置於複數個下方導電條之第二條的第一端上方，進一 步包含第一垂直導電穿孔的形成，其用以將複數個上方導 電條之第一條的第一端與複數個下方導電條之第一條的第 一端互連，且進一步包含第二垂直導電穿孔的形成，其用 以將複數個上方導電條之第一條的第二端與複數個下方導 電條之第二條的第一端互連。 3. 根據申請專利範圍第1項所述之方法，其中將兩個互 連導體層中的一層形成於積體電路結構的第一金屬層中， 且將兩個互連導體層中的另一層形成於積體電路結構的至 少第三金屬層中。 4 .根據申請專利範圍第3項所述之方法，其中在第一金 屬層中之導體層的一端與在至少第三金屬層中的上層導體 層互連，其中第一導電穿孔從積體電路結構的第一金屬層 延伸至第二金屬層，且進一步有一些另外的導電穿孔，其 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐1 I"T--------Λ-- (請先聞讀背面之注意事項再填寫本頁) 、1Τ 經濟部智慧財產局員工消費合作社印製 -18· 557583 A8 B8 C8 D8 六、申請專利範圍2 每個都與第一導電穿孔垂直對準以到達形成在至少第三金 屬層中的導體層。 (請先聞讀背面之注意事項再填寫本頁} 5. —種在半導體基體中形成多層電感的方法，包含： 提供半導體基體； 在半導體基體上形成第一絕緣層； 在第一絕緣層中形成複數個平行的第一階金屬澆道； 在第一絕緣層上形成第二絕緣層； 在第二絕緣層中形成複數個第一與第二導電穿孔，其 中在其底端，複數個第一與第二導電穿孔的每一個穿孔皆 分別與複數個第一階金屬澆道之每一個的第一端段與第二 端段呈電性接觸； 在第二絕緣層上形成至少第三絕緣層； 在該至少第三絕緣層中形成複數個第三與第四導電穿 孔，其中複數個第三與第四導電穿孔的每一個穿孔皆垂直· 對準且分別與複數個第一與第二導電穿孔中的一個穿孔呈 電性接觸； 經濟部智慧財產局員工消費合作社印製 形成複數個平行第二階金屬澆道，其將在上端的複數 個第三與第四導電穿孔互連； 其中包括複數個第一階金屬澆道之每一個澆道的垂直 平面相交於包括複數個第二階金屬澆道之每一個澆道的垂 直平面，及其中複數個第二階金屬澆道的每一個澆道藉由 第一與第三導電穿孔以及第二與第四導電穿孔互連於連續 的第一階金屬澆道。 6. —種在半導體基體中形成多層電感的方法，包含： 本&張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 一 -19- 557583 A8 B8 C8 D8 六、申請專利範圍3 提供半導體基體； 在半導體基體上形成絕緣層的第一堆疊； 在絕緣層之第一堆疊的一層或多層中形成複數個平行 的第一溝； 在複數個第一溝的每一溝中形成導電材料；以形成複 數個第一階金屬澆道； 在絕緣層的第一堆疊之上形成絕緣層的第二堆疊； 在第二絕緣層的第二堆疊中形成複數個第一與第二導 電穿孔，其中在其底端，複數個第一與第二導電穿孔·的每 一個穿孔皆分別與複數個第一階金屬澆道之每一個的第一 端段與第二端段呈電性接觸； 在絕緣層的第二堆疊之上形成絕緣層的第三堆疊； 在絕緣層的第三堆疊中形成複數個第三與第四穿孔口 ，其中複數個第三與第四穿孔口的每一個皆分別垂直對準· 於複數個第一與第二導電穿孔中的一個穿孔； 在絕緣層之第三堆疊的一些預定層中形成複數個平行 的第二溝，其中複數個第二溝之每一溝的第一端段與第二 端段皆分別對準於複數個第三與第四穿孔口的每一個穿孔 □； 在複數個第三與第四穿孔口及第二溝中形成導電材料 以形成複數個第三與第四導電穿孔以及複數個與其電性接 觸的第二階金屬澆道，其中複數個第三與第四導電穿孔的 每一個皆分別與複數個第一與第二導電穿孔的一個呈電性 接觸； 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） I-^---、-----9 — I (請先閲讀背面之注意事項再填寫本頁) 、1T- 經濟部智慧財產局員工消費合作社印製 -20- 557583 A8 B8 C8 - ^^ D8 、申請專利範圍4 其中包括複數個第一階金屬澆道之每一個澆道的垂直 平li丨相交於包括複數個第二階金屬澆道之每一個澆道的垂 直平面，及其中複數個第二階金屬澆道的每一個澆道藉由 第〜與第三導電穿孔以及第二與第四導電穿孔互連於連續 白勺/第〜階金屬澆道。 7 ·根據申請專利範圍第6項所述之方法，其中該第一絕 緣堆疊包含底部阻障層與中間介電層。 8 .根據申請專利範圍第7項所述之方法，其中該阻障層 的材料選自鉬、鉬氮化物、鈦與鈦氮化物。 9.根據申請專利範圍第7項所述之方法，其中該中間介 電層的材料包含具有大約小於3 . 〇之相關介電常數的材料。 I 〇.根據申請專利範圍第7項所述之方法，其中該中間 層的材料包含二氧化砂。 II .根據申請專利範圍第7項所述之方法，其中該第一· 絕緣堆疊進一步包含置於中間介電層之上的硬遮罩層，及 其中複數個第一溝是透過該硬遮罩層藉由圖樣與蝕刻所形 成。 1 2 .根據申請專利範圍第6項所述之方法，進一步包含 在該絕緣層的第一堆疊上形成光阻層，及其中複數個第一 溝是透過該光阻層藉由圖樣與蝕刻所形成。 1 3 ·根據申請專利範圍第6項所述之方法，其中形成複 數個第一階金屬澆道的步驟進一步包含： 沿著複數個第一溝之每一溝的內部形成阻障層； 形成鄰接該阻障層的種晶層； 本紙張尺度適用中國國家標準（CNS ) A4規格（21ϋΧ297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -21 - 557583 A8 B8 C8 D8 六、申請專利範圍5 在複數個第一溝的每一溝中電鍍金屬；及 將基體的頂面平面化。 14.根據申請專利範圍第13項所述之方法，其中該阻障 層的材料選自钽、組氮化物、鈦與鈦氮化物，及其中阻障 層是藉由化學蒸氣沉積所形成的。 15·根據申請專利範圍第13項所述之方法，其中該種晶 層的材料包含銅，及其中種晶層是藉由化學蒸氣沉積所形 成的。 16.根據申請專利範圍第13項所述之方法，其中該金屬 包含銅。 I7·根據申請專利範圍第6項所述之方法，其中第二與 第三絕緣堆疊包含： 底部阻障層； 置於底部阻障層之上的第一介電層； 置於第一介電層之上的蝕刻停止層；及 置於蝕刻停止層之上的第二介電層。 18. 根據申請專利範圍第17項所述之方法，其中該底部 阻障層的材料選自鉅、鉅氮化物、鈦與鈦氮化物。 19. 根據申請專利範圍第17項所述之方法，其中該第一 與第二介電層的材料包含具有大約小於3.0之相關介電常數 的材料。 2〇·根據申請專利範圍第17項所述之方法，其中該第一 與第二介電層的材料包含二氧化矽。 21·根據申請專利範圍第17項所述之方法，其中該第二 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） --^--------0-- (請先閲讀背面之注意事項再填寫本頁：> 訂· 經濟部智慧財產局員工消費合作社印製 -22- 經濟部智慧財產局員工消費合作社印製 557583 A8 B8 C8 D8 TV、申請專利範圍6 與第三絕緣堆疊進一步包含置於第二介電層之上的硬遮罩 層，及其中第二與第三溝是透過該硬遮罩層藉由圖樣與蝕 刻所形成。 22. 根據申請專利範圍第17項所述之方法，其中該第二 與第三絕緣堆疊進一步包含置於第二介電層上方的光阻層 ，及其中第二與第三溝是透過該光阻層藉由圖樣與蝕刻所 形成。 23. 根據申請專利範圍第17項所述之方法，其中該絕緣 層之第三堆疊的一些預定層包含該第二介電層。 24. 根據申請專利範圍第6項所述之方法，其中形成該 複數個第一與第二導電穿孔的步驟進一步包含： 在絕緣層的第二堆疊上形成遮罩層； 圖樣及蝕刻該遮罩層以形成複數個第一與第二穿孔口 9 在複數個第一與第二穿孔口中形成阻障層； 在該阻障層上形成種晶層； 在複數個第一與第二穿孔口的每一個穿孔口中電鍍金 屬；及 將基體的頂面平面化。 25. 根據申請專利範圍第24項所述之方法，其中該阻障 層的材料選自鉬、鉅氮化物、鈦與鈦氮化物，及其中該阻 障層是藉由化學蒸氣沉積所形成。 26. 根據申請專利範圍第24項所述之方法，其中該種晶 層的材料包含銅，及其中該種晶層是藉由化學蒸氣沉積所 i氏張尺度適用中國國家榇準（CNS) A4^ (210χ297公釐） 1 -23- (請先聞讀背面之注意事項再填寫本頁)557583 A8 B8 C8 D8 VI. Application for Patent Scope 1 1. A method for forming an integrated circuit structure, comprising: forming a semiconductor substrate having an upper surface; forming a plurality of conductor layers on the upper surface; and interconnecting two conductor layers To form a spiral inductor structure in which there is at least one unconnected conductor layer between two interconnected conductor layers. 2. The method according to item 1 of the scope of the patent application, wherein the two conductor layers interconnected include a plurality of upper and lower conductive stripes, and the plurality of upper and lower conductive stripes are located in an intersecting vertical plane, wherein the plurality of The first end of the first strip of the upper conductive strips is placed above the first end of the first strip of the plurality of lower conductive strips, and the second end of the first strip of the plurality of top conductive strips is placed above the plurality of lower conductive strips. Above the first end of the second strip, further includes the formation of a first vertical conductive perforation, which is used to connect the first end of the first strip of the plurality of upper conductive strips and the first strip of the first strip of the plurality of lower conductive strips. One end is interconnected, and further includes the formation of a second vertical conductive via for interconnecting the second end of the first one of the plurality of upper conductive strips and the first end of the second one of the plurality of lower conductive strips. 3. The method according to item 1 of the scope of patent application, wherein one of the two interconnected conductor layers is formed in the first metal layer of the integrated circuit structure, and the other of the two interconnected conductor layers is formed It is formed in at least a third metal layer of the integrated circuit structure. 4. The method according to item 3 of the scope of patent application, wherein one end of a conductor layer in the first metal layer is interconnected with an upper conductor layer in at least a third metal layer, wherein the first conductive via is from the integrated circuit The first metal layer of the structure extends to the second metal layer, and further has some additional conductive perforations, the paper size of which is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm 1 I " T ------- -Λ-- (Please read the precautions on the back before filling out this page), 1T Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-18 · 557583 A8 B8 C8 D8 VI. Scope of patent application 2 The conductive vias are aligned vertically to reach the conductor layer formed in at least the third metal layer. (Please read the precautions on the back before filling out this page} 5.-A method for forming a multilayer inductor in a semiconductor substrate, including: Provide Semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a plurality of parallel first-stage metal runners in the first insulating layer; forming a second insulating layer on the first insulating layer; in the second insulating layer A plurality of first and second conductive perforations are formed, wherein at the bottom end, each of the plurality of first and second conductive perforations is respectively connected to the first end section of each of the plurality of first-stage metal runners and The second end section is in electrical contact; forming at least a third insulating layer on the second insulating layer; forming a plurality of third and fourth conductive vias in the at least third insulating layer, wherein the plurality of third and fourth conductive vias are formed Each of the perforations is vertically aligned and in electrical contact with one of the plurality of first and second conductive perforations, respectively; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to form a plurality of parallel second-order metal pouring Which interconnects a plurality of third and fourth conductive through holes at the upper end; a vertical plane including each of the plurality of first-stage metal runners intersects each of the plurality of second-stage metal runners The vertical plane of a runner and each of the plurality of second-stage metal runners are interconnected to a continuous first-stage metal by first and third conductive vias and second and fourth conductive vias. Sprue 6. —A method for forming a multilayer inductor in a semiconductor substrate, including: This & Zhang scale is applicable to Chinese National Standards (CNS > A4 specifications (210X297 mm) -1-19- 557583 A8 B8 C8 D8 Six, Patent application scope 3 provides a semiconductor substrate; forming a first stack of insulating layers on the semiconductor substrate; forming a plurality of parallel first trenches in one or more layers of the first stack of insulating layers; each of the plurality of first trenches A conductive material is formed in the trench; to form a plurality of first-order metal runners; a second stack of insulating layers is formed on the first stack of insulating layers; a plurality of first and The second conductive perforation, wherein at the bottom end, each of the plurality of first and second conductive perforations is respectively corresponding to the first end section and the second end section of each of the plurality of first-stage metal runners. Electrical contact; forming a third stack of insulating layers on the second stack of insulating layers; forming a plurality of third and fourth perforations in the third stack of insulating layers, wherein the plurality of third and fourth perforations Each of the apertures is vertically aligned with one of the plurality of first and second conductive vias; a plurality of parallel second trenches are formed in some predetermined layers of the third stack of the insulating layer, among which a plurality of The first end section and the second end section of each groove of the second groove are respectively aligned with each of the plurality of third and fourth perforations; in the plurality of third and fourth perforations and the second A conductive material is formed in the trench to form a plurality of third and fourth conductive perforations and a plurality of second-stage metal runners in electrical contact therewith, wherein each of the plurality of third and fourth conductive perforations is respectively associated with a plurality of first One is in electrical contact with one of the second conductive perforations; This paper size applies to China National Standard (CNS) A4 specification (210 × 297 mm) I-^ ---, ----- 9 — I (Please read the back first (Please note this page before filling in this page), 1T- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-20- 557583 A8 B8 C8-^^ D8, patent application scope 4 including each of a plurality of first-stage metal runners The vertical flat li of the runner intersects A vertical plane including each of the plurality of second-stage metal runners, and each of the plurality of second-stage metal runners includes first to third conductive perforations and second and fourth conductive perforations. Interconnected with continuous / first-order metal runners. 7. The method according to item 6 of the scope of patent application, wherein the first insulating stack includes a bottom barrier layer and an intermediate dielectric layer. 8. The method according to item 7 of the patent application, wherein the material of the barrier layer is selected from molybdenum, molybdenum nitride, titanium, and titanium nitride. 9. The method according to item 7 of the scope of patent application, wherein the material of the intermediate dielectric layer comprises a material having a relative dielectric constant of less than about 3.0. I. The method according to item 7 of the scope of patent application, wherein the material of the intermediate layer comprises sand dioxide. II. The method according to item 7 of the scope of patent application, wherein the first insulation stack further comprises a hard mask layer disposed on the intermediate dielectric layer, and the plurality of first trenches are through the hard mask The layer is formed by patterning and etching. 1 2. The method according to item 6 of the scope of the patent application, further comprising forming a photoresist layer on the first stack of the insulating layer, and the plurality of first grooves are passed through the photoresist layer through patterning and etching. form. 1 3. The method according to item 6 of the scope of patent application, wherein the step of forming a plurality of first-stage metal runners further comprises: forming a barrier layer along the inside of each of the plurality of first grooves; forming an abutment The seed layer of the barrier layer; This paper size is applicable to Chinese National Standard (CNS) A4 specification (21ϋ × 297 mm) (Please read the precautions on the back before filling this page) Order printed by the Intellectual Property Bureau's Consumer Cooperatives -21-557583 A8 B8 C8 D8 6. Scope of patent application 5 Metal plating in each groove of the plurality of first grooves; and planarize the top surface of the substrate. 14. The method according to item 13 of the patent application, wherein the material of the barrier layer is selected from the group consisting of tantalum, group nitride, titanium and titanium nitride, and the barrier layer is formed by chemical vapor deposition. 15. The method according to item 13 of the scope of the patent application, wherein the material of the seed layer comprises copper, and the seed layer is formed by chemical vapor deposition. 16. The method according to item 13 of the patent application, wherein the metal comprises copper. I7. The method according to item 6 of the scope of patent application, wherein the second and third insulation stacks include: a bottom barrier layer; a first dielectric layer disposed on the bottom barrier layer; and a first dielectric layer An etch stop layer over the layer; and a second dielectric layer disposed over the etch stop layer. 18. The method according to item 17 of the application, wherein the material of the bottom barrier layer is selected from the group consisting of giant, giant nitride, titanium, and titanium nitride. 19. The method according to item 17 of the patent application, wherein the material of the first and second dielectric layers comprises a material having a relative dielectric constant of less than about 3.0. 20. The method according to item 17 of the scope of patent application, wherein the material of the first and second dielectric layers comprises silicon dioxide. 21 · The method described in item 17 of the scope of the patent application, wherein the second paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)-^ -------- 0-- ( Please read the notes on the back before filling out this page: > Order · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-22-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 557583 A8 B8 C8 D8 TV, Patent Application Scope 6 The stack with the third insulation further includes a hard mask layer disposed on the second dielectric layer, and the second and third trenches are formed through the hard mask layer through patterning and etching. 22. According to the patent application The method according to item 17, wherein the second and third insulating stacks further include a photoresist layer disposed above the second dielectric layer, and wherein the second and third trenches pass through the photoresist layer through the pattern And etching. 23. The method according to item 17 of the scope of patent application, wherein some predetermined layers of the third stack of the insulating layer include the second dielectric layer. 24. The method according to item 6 of scope of patent application Method in which the plural is formed The steps of the first and second conductive perforations further include: forming a masking layer on the second stack of insulating layers; patterning and etching the masking layer to form a plurality of first and second perforations 9 between the plurality of first and Forming a barrier layer in the second perforation opening; forming a seed layer on the barrier layer; electroplating metal in each of the plurality of first and second perforations; and planarizing the top surface of the substrate. 25. According to The method of claim 24, wherein the material of the barrier layer is selected from the group consisting of molybdenum, giant nitride, titanium and titanium nitride, and the barrier layer is formed by chemical vapor deposition. 26. According to The method described in item 24 of the scope of the patent application, wherein the material of the seed layer includes copper, and wherein the seed layer is in accordance with China National Standards (CNS) A4 ^ (210χ297) by the chemical vapor deposition institute's I-scale. Mm) 1 -23- (Please read the notes on the back before filling out this page) 經濟部智慧財產局員工消費合作社印製 557583 A8 B8 C8 _ D8 六、申請專利範圍7 形成。 27.根據申請專利範圍第6項所述之方法，其中在該複 數個第三與第四穿孔口及第二溝之中形成導電材料的步驟 進一步包含： 在該複數個第三與第四穿孔口的每一個穿孔口及第二 溝之中形成阻障層； 在該阻障層之上形成種晶層； 在該複數個第三與第四穿孔口的每一個穿孔口以及第 二溝中電鍍金屬；及 將該基體的頂面平面化。 28·根據申請專利範圍第27項所述之方法，其中該阻障 層的材料選自鉅、鉬氮化物、鈦與鈦氮化物，及其中該阻 障層是藉由化學蒸氣沉積所形成。 29. 根據申請專利範圍第27項所述之方法，其中該種晶_ 層的材料包含銅，及其中該種晶層是藉由化學蒸氣沉積所 形成。 30. 根據申請專利範圍第6項所述之方法，其中該複數 個第一階金屬澆道與第二階金屬澆道的每一個澆道從俯視 電感的角度來看包含一 L形結構，及其中每個L形結構包 含一短腳段與一長腳段。 31. 根據申請專利範圍第30項所述之方法，其中藉由一 個或多個的第一、第二、第三與第四導電穿孔，該複數個 第一階金屬澆道之其一的短腳段電性連接於複數個第二階 金屬澆道之鄰近一澆道的長腳段。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^ 1T^91 (請先聞讀背面之注意事項再填寫本頁) -24- 557583 A8 B8 C8 __D8 六、申請專利範圍8 3 2 ·根據申請專利範圍第6項所述之方法，其中包含該 複數個第一階金屬澆道之其一的平面與包含第二階金屬澆 道之其一的平面相交於銳角。 3 3 ·根據申請專利範圍第6項所述之方法，其中該複數 個互連的第一階金屬澆道與第二階金屬澆道形成具有非零 電感係數的導電螺旋狀結構。 34. —種積體電路結構，包含： 半導體基體； 複數個置於半導體基體上方的第一導電條； 導電穿孔的第一堆疊電性連接於複數個第一導電條之 每一條的第一端； 導電穿孔的第二堆疊電性連接於複數個第二導電條之 每一條的第二端；及 複數個第二導電條，其第一端電性連接於導電穿孔之· 第一堆疊的最上方穿孔，而其第二端電性連接於導電穿孔 之第二堆疊的最上方穿孔，其中複數個第二導電條中的一 條置於兩個連續的第一導電條之間，用以將兩個連續的第 一導電條互連。 35. —種多階積體電路結構，包含： 具有複數個絕緣層與複數個導電層於其中的半導體基 iM · 體， 澆道導電部分； 垂直導電部分； 其中下方澆道部分形成於半導體基體的下方導電層中 本紙張尺度適用中國國家標準（CNS ) A4規格（210X：297公釐） —^---:.·-----Λ — (請先閲讀背面之注意事項再填寫本頁) 訂 ir. 經濟部智慧財產局員工消費合作社印製 -25- 557583 A8 B8 C8 D8 穴、申請專利乾圍9 J 其中在下方澆道部分上方的至少兩個或多個導電層以 上形成上方澆道部分； 其中兩個或多個垂直對準的第一穿孔部分在第一下方 澆道部分之第一端與第一上方澆道部分之上層第一端之間 產生電性連接；及 其中兩個或多個垂直對準的第二穿孔部分在第二下方 澆道部分之第一端與第一上方澆道部分之上層第二端之間 產生電性連接。 —7----7----會------1T------#1 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -26-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 557583 A8 B8 C8 _ D8 6. The scope of patent application 7 was formed. 27. The method according to item 6 of the scope of patent application, wherein the step of forming a conductive material in the plurality of third and fourth perforations and the second groove further comprises: in the plurality of third and fourth perforations A barrier layer is formed in each of the perforated openings and the second groove; a seed layer is formed on the barrier layer; in each of the plurality of third and fourth perforated openings and in the second groove Electroplating metal; and planarizing the top surface of the substrate. 28. The method according to item 27 of the scope of patent application, wherein the material of the barrier layer is selected from the group consisting of giant, molybdenum nitride, titanium, and titanium nitride, and wherein the barrier layer is formed by chemical vapor deposition. 29. The method according to item 27 of the scope of the patent application, wherein the material of the seed layer comprises copper, and wherein the seed layer is formed by chemical vapor deposition. 30. The method according to item 6 of the scope of the patent application, wherein each of the plurality of first-stage metal runners and the second-stage metal runners include an L-shaped structure from the perspective of the inductor in plan view, and Each L-shaped structure includes a short leg section and a long leg section. 31. The method according to item 30 of the scope of patent application, wherein by one or more of the first, second, third and fourth conductive perforations, one of the plurality of first-stage metal runners is short. The leg section is electrically connected to the long leg section of a plurality of second-stage metal runners adjacent to a runner. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) ^ 1T ^ 91 (please read the precautions on the back before filling out this page) -24- 557583 A8 B8 C8 __D8 VI. Range of patent application 8 3 2. The method according to item 6 of the scope of patent application, wherein a plane including one of the plurality of first-stage metal runners and a plane including one of the second-stage metal runners intersect at an acute angle. 3 3. The method according to item 6 of the scope of patent application, wherein the plurality of interconnected first-stage metal runners and second-stage metal runners form a conductive spiral structure having a non-zero inductance. 34. A integrated circuit structure comprising: a semiconductor substrate; a plurality of first conductive strips disposed above the semiconductor substrate; a first stack of conductive perforations electrically connected to a first end of each of the plurality of first conductive strips The second stack of conductive perforations is electrically connected to the second end of each of the plurality of second conductive strips; and the second end of the plurality of second conductive strips is electrically connected to the first end of the first stack An upper hole, and a second end of which is electrically connected to the uppermost hole of the second stack of conductive holes, wherein one of the plurality of second conductive strips is placed between two consecutive first conductive strips for connecting the two Consecutive first conductive strips are interconnected. 35. A multi-level integrated circuit structure comprising: a semiconductor-based iM body having a plurality of insulating layers and a plurality of conductive layers therein, a runner conductive portion; a vertical conductive portion; wherein a lower runner portion is formed on the semiconductor substrate In the lower conductive layer of this paper, the size of this paper applies the Chinese National Standard (CNS) A4 specification (210X: 297 mm) — ^ --- :. · ----- Λ — (Please read the precautions on the back before filling in this Page) Order ir. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -25- 557583 A8 B8 C8 D8 cavity, patent application Ganwei 9 J where at least two or more conductive layers above the lower runner part are formed above A runner portion; wherein two or more vertically aligned first perforated portions create an electrical connection between a first end of a first lower runner portion and a first end of a layer above a first upper runner portion; and Two or more vertically aligned second perforated portions are electrically connected between the first end of the second lower runner portion and the second end of the upper layer of the first upper runner portion. —7 ---- 7 ---- 会 ------ 1T ------ # 1 (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm) -26-
TW091121020A 2001-10-05 2002-09-13 A multi-layer inductor formed in a semiconductor substrate TW557583B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/972,482 US6639298B2 (en) 2001-06-28 2001-10-05 Multi-layer inductor formed in a semiconductor substrate

Publications (1)

Publication Number Publication Date
TW557583B true TW557583B (en) 2003-10-11

Family

ID=25519707

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091121020A TW557583B (en) 2001-10-05 2002-09-13 A multi-layer inductor formed in a semiconductor substrate

Country Status (5)

Country Link
US (1) US6639298B2 (en)
JP (1) JP4903971B2 (en)
KR (1) KR100939648B1 (en)
GB (1) GB2381130B (en)
TW (1) TW557583B (en)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573148B1 (en) * 2000-07-12 2003-06-03 Koninklljke Philips Electronics N.V. Methods for making semiconductor inductor
US6635948B2 (en) * 2001-12-05 2003-10-21 Micron Technology, Inc. Semiconductor device with electrically coupled spiral inductors
US7129561B2 (en) * 2003-11-19 2006-10-31 International Business Machines Corporation Tri-metal and dual-metal stacked inductors
US7262680B2 (en) 2004-02-27 2007-08-28 Illinois Institute Of Technology Compact inductor with stacked via magnetic cores for integrated circuits
DE102004014752B4 (en) * 2004-03-25 2008-11-20 Infineon Technologies Ag Semiconductor device with coreless converter and half-bridge
JP4541847B2 (en) * 2004-11-22 2010-09-08 Ｏｋｉセミコンダクタ株式会社 Alignment accuracy detection method
US7714688B2 (en) * 2005-01-20 2010-05-11 Avx Corporation High Q planar inductors and IPD applications
US7867787B2 (en) * 2007-12-31 2011-01-11 Intel Corporation Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits
WO2010035481A1 (en) * 2008-09-26 2010-04-01 ローム株式会社 Semiconductor device and semiconductor device manufacturing method
US8410576B2 (en) * 2010-06-16 2013-04-02 National Semiconductor Corporation Inductive structure and method of forming the inductive structure with an attached core structure
US8692608B2 (en) 2011-09-19 2014-04-08 United Microelectronics Corp. Charge pump system capable of stabilizing an output voltage
US9030221B2 (en) 2011-09-20 2015-05-12 United Microelectronics Corporation Circuit structure of test-key and test method thereof
US8395455B1 (en) 2011-10-14 2013-03-12 United Microelectronics Corp. Ring oscillator
US8421509B1 (en) 2011-10-25 2013-04-16 United Microelectronics Corp. Charge pump circuit with low clock feed-through
US8588020B2 (en) 2011-11-16 2013-11-19 United Microelectronics Corporation Sense amplifier and method for determining values of voltages on bit-line pair
US8493806B1 (en) 2012-01-03 2013-07-23 United Microelectronics Corporation Sense-amplifier circuit of memory and calibrating method thereof
US8970197B2 (en) 2012-08-03 2015-03-03 United Microelectronics Corporation Voltage regulating circuit configured to have output voltage thereof modulated digitally
US8724404B2 (en) 2012-10-15 2014-05-13 United Microelectronics Corp. Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array
US8669897B1 (en) 2012-11-05 2014-03-11 United Microelectronics Corp. Asynchronous successive approximation register analog-to-digital converter and operating method thereof
US8711598B1 (en) 2012-11-21 2014-04-29 United Microelectronics Corp. Memory cell and memory cell array using the same
US8873295B2 (en) 2012-11-27 2014-10-28 United Microelectronics Corporation Memory and operation method thereof
US8643521B1 (en) 2012-11-28 2014-02-04 United Microelectronics Corp. Digital-to-analog converter with greater output resistance
US9030886B2 (en) 2012-12-07 2015-05-12 United Microelectronics Corp. Memory device and driving method thereof
US8953401B2 (en) 2012-12-07 2015-02-10 United Microelectronics Corp. Memory device and method for driving memory array thereof
US8917109B2 (en) 2013-04-03 2014-12-23 United Microelectronics Corporation Method and device for pulse width estimation
US9577023B2 (en) * 2013-06-04 2017-02-21 Globalfoundries Inc. Metal wires of a stacked inductor
US9105355B2 (en) 2013-07-04 2015-08-11 United Microelectronics Corporation Memory cell array operated with multiple operation voltage
US8859384B1 (en) 2013-08-01 2014-10-14 International Business Machines Corporation Inductor formation with sidewall image transfer
US8947911B1 (en) 2013-11-07 2015-02-03 United Microelectronics Corp. Method and circuit for optimizing bit line power consumption
US8866536B1 (en) 2013-11-14 2014-10-21 United Microelectronics Corp. Process monitoring circuit and method
US9143143B2 (en) 2014-01-13 2015-09-22 United Microelectronics Corp. VCO restart up circuit and method thereof
CN105742251B (en) 2014-12-09 2019-10-18 联华电子股份有限公司 Structure with inductance and metal-insulating layer-metal capacitor
JP6507027B2 (en) * 2015-05-19 2019-04-24 新光電気工業株式会社 Inductor and method of manufacturing the same
CN106876253B (en) * 2017-03-10 2019-06-04 成都海威华芯科技有限公司 A kind of acute angle metallic pattern stripping means
US10672704B2 (en) * 2017-11-30 2020-06-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device with polygonal inductive device
US10672859B2 (en) * 2018-06-27 2020-06-02 Intel Corporation Embedded magnetic inductor

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614554A (en) 1968-10-24 1971-10-19 Texas Instruments Inc Miniaturized thin film inductors for use in integrated circuits
NL7900244A (en) 1979-01-12 1980-07-15 Philips Nv FLAT TWO-LAYER ELECTRICAL COIL.
JPH0269971A (en) * 1988-09-05 1990-03-08 Seiko Epson Corp Inductance-containing type semiconductor device
JPH02181961A (en) * 1989-01-09 1990-07-16 Nec Corp Integrated circuit device
JPH0377360A (en) 1989-08-18 1991-04-02 Mitsubishi Electric Corp Semiconductor device
JP3048592B2 (en) 1990-02-20 2000-06-05 ティーディーケイ株式会社 Laminated composite parts
US5227659A (en) 1990-06-08 1993-07-13 Trustees Of Boston University Integrated circuit inductor
JPH04335531A (en) * 1991-05-10 1992-11-24 Mitsubishi Electric Corp Semiconductor device
US5336921A (en) 1992-01-27 1994-08-09 Motorola, Inc. Vertical trench inductor
US5610433A (en) 1995-03-13 1997-03-11 National Semiconductor Corporation Multi-turn, multi-level IC inductor with crossovers
US5541442A (en) 1994-08-31 1996-07-30 International Business Machines Corporation Integrated compact capacitor-resistor/inductor configuration
US5446311A (en) * 1994-09-16 1995-08-29 International Business Machines Corporation High-Q inductors in silicon technology without expensive metalization
US5559360A (en) 1994-12-19 1996-09-24 Lucent Technologies Inc. Inductor for high frequency circuits
EP0725407A1 (en) 1995-02-03 1996-08-07 International Business Machines Corporation Three-dimensional integrated circuit inductor
US5717243A (en) 1996-04-24 1998-02-10 Harris Corporation Integrated circuit with an improved inductor structure and method of fabrication
US5861647A (en) * 1996-10-02 1999-01-19 National Semiconductor Corporation VLSI capacitors and high Q VLSI inductors using metal-filled via plugs
US5736749A (en) 1996-11-19 1998-04-07 Lucent Technologies Inc. Integrated circuit device with inductor incorporated therein
TW308741B (en) 1996-11-22 1997-06-21 United Microelectronics Corp Micro-coil structure of integrated circuit and process thereof
EP0862218B1 (en) 1997-02-28 2007-02-28 Telefonaktiebolaget LM Ericsson (publ) An improved-q inductor with multiple metalization levels
US6160303A (en) 1997-08-29 2000-12-12 Texas Instruments Incorporated Monolithic inductor with guard rings
KR100268906B1 (en) 1997-09-29 2000-10-16 김영환 Method for forming inductor of semiconductor device
FR2771843B1 (en) * 1997-11-28 2000-02-11 Sgs Thomson Microelectronics INTEGRATED CIRCUIT TRANSFORMER
TW363278B (en) 1998-01-16 1999-07-01 Winbond Electronics Corp Preparation method for semiconductor to increase the inductive resonance frequency and Q value
US6008102A (en) 1998-04-09 1999-12-28 Motorola, Inc. Method of forming a three-dimensional integrated inductor
US6166422A (en) 1998-05-13 2000-12-26 Lsi Logic Corporation Inductor with cobalt/nickel core for integrated circuit structure with high inductance and high Q-factor
JPH11354330A (en) * 1998-06-08 1999-12-24 Mitsubishi Materials Corp Laminated chip parts and its usage
JP3578644B2 (en) * 1998-10-12 2004-10-20 Ｎｅｃエレクトロニクス株式会社 Semiconductor device
US6249191B1 (en) 1998-11-23 2001-06-19 Micron Technology, Inc. Monolithic integrated circuit oscillators, complementary metal oxide semiconductor (CMOS) voltage-controlled oscillators, integrated circuit oscillators, oscillator-forming methods, and oscillation methods
JP2000232202A (en) * 1998-12-11 2000-08-22 Matsushita Electric Ind Co Ltd High q inductor for high frequency
US6083802A (en) 1998-12-31 2000-07-04 Winbond Electronics Corporation Method for forming an inductor
JP2000269418A (en) * 1999-03-17 2000-09-29 Sony Corp Wiring structure, inductor and formation method therefor
US6037649A (en) 1999-04-01 2000-03-14 Winbond Electronics Corp. Three-dimension inductor structure in integrated circuit technology
US6255714B1 (en) 1999-06-22 2001-07-03 Agere Systems Guardian Corporation Integrated circuit having a micromagnetic device including a ferromagnetic core and method of manufacture therefor
US6240622B1 (en) 1999-07-09 2001-06-05 Micron Technology, Inc. Integrated circuit inductors
US6140197A (en) 1999-08-30 2000-10-31 Chartered Semiconductor Manufacturing Ltd. Method of making spiral-type RF inductors having a high quality factor (Q)
US6187647B1 (en) 1999-10-12 2001-02-13 Lucent Technologies Inc. Method of manufacturing lateral high-Q inductor for semiconductor devices
KR20010075974A (en) * 2000-01-21 2001-08-11 이서헌 Semiconductor Integrated Inductor
US6429504B1 (en) * 2000-05-16 2002-08-06 Tyco Electronics Corporation Multilayer spiral inductor and integrated circuits incorporating the same
WO2002013271A2 (en) 2000-08-04 2002-02-14 Infineon Technologies Ag Integrated electronic circuit with at least one inductor and method for producing the same
US6420773B1 (en) * 2000-10-04 2002-07-16 Winbond Electronics Corp. Multi-level spiral inductor structure having high inductance (L) and high quality factor (Q)

Also Published As

Publication number Publication date
US6639298B2 (en) 2003-10-28
KR20030029491A (en) 2003-04-14
GB2381130B (en) 2006-02-01
US20030001231A1 (en) 2003-01-02
GB0221301D0 (en) 2002-10-23
GB2381130A (en) 2003-04-23
JP2003179151A (en) 2003-06-27
JP4903971B2 (en) 2012-03-28
KR100939648B1 (en) 2010-02-03

Similar Documents

Publication Publication Date Title
TW557583B (en) A multi-layer inductor formed in a semiconductor substrate
JP4948756B2 (en) Inductor formed in integrated circuit and method of manufacturing the same
US7381607B2 (en) Method of forming a spiral inductor in a semiconductor substrate
US7969274B2 (en) Method to improve inductance with a high-permeability slotted plate core in an integrated circuit
US6031445A (en) Transformer for integrated circuits
TWI279009B (en) A thin film multi-layer high Q transformer formed in a semiconductor substrate
US11393787B2 (en) Conductor design for integrated magnetic devices
EP0902974A1 (en) Conductors for integrated circuits
TW478135B (en) Lateral high-q inductor for semiconductor devices
US20080120828A1 (en) High Density Planarized Inductor And Method Of Making The Same
US8004061B1 (en) Conductive trace with reduced RF impedance resulting from the skin effect
US6864581B1 (en) Etched metal trace with reduced RF impendance resulting from the skin effect
US7223680B1 (en) Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin effect
KR100818994B1 (en) Fabricating method for semiconductor device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent