JP2976718B2 - Magnetic tape recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic tape recording and reproducing apparatus for recording and reproducing information such as audio.

[0002]

2. Description of the Related Art In recent years, a high quality sound recording / reproducing apparatus for converting an audio signal into a digital signal and recording / reproducing on a magnetic tape has been commercialized. Therefore, a high-performance recording / reproducing apparatus with a simpler configuration is desired.

A conventional magnetic tape recording / reproducing apparatus will be described below. FIG. 7 is a block diagram of a conventional magnetic tape recording / reproducing apparatus.

In FIG. 7, 1 is a magnetic tape, 2 is a capstan, 3 is a pinch roller, 4 is a capstan motor for rotating the capstan by a drive circuit 5, and 5 is a target to which the rotation speed of the capstan 2 is inputted. A driving circuit for driving the capstan motor 4 so that the speed becomes 31;
Is a subtractor that calculates the difference between the rotation speed of the capstan 2 and its target speed 31. The method of detecting the rotation speed of the capstan 2 is based on the method of detecting from the back electromotive force of the capstan motor and the rotation speed. For example, a method of generating a shifted frequency is used. 7 is an adder for adding the output of the D / A converter 16 and the output of the subtractor 6, 8 is a magnetic head for recording and reproducing digital signals on the magnetic tape 1, and 9 is a reproduced signal reproduced by the magnetic head 8. A demodulation circuit 10 demodulates the digital signal into a digital signal, a phase error detection circuit 10 detects a synchronizing signal and an address signal from an output of the demodulation circuit 9, and detects a phase error with a reproduction reference signal. A phase gain multiplication circuit 16 multiplies a gain for feeding back the detected phase error to the drive circuit 5, and a D / A converter 16 converts a digital output of the phase gain multiplication circuit 11 into an analog voltage.

The operation of the conventional magnetic tape recording / reproducing apparatus configured as described above will be described below.

At the time of recording, the capstan 2 is driven by the magnetic tape 1 in a speed control loop including a drive circuit 5, a capstan motor 4, a capstan 2, a pinch roller 3, and a subtractor 6.
The output of the subtractor 6 is input to the drive circuit 5 so that the rotation speed is in accordance with the target speed of the drive circuit 5, and the error between the target speed 31 and the capstan rotation speed is fed back.
The capstan 2 is rotated at a predetermined speed. The magnetic tape 1 runs while being driven by a rotating capstan 2 and a pinch roller 3. Next, a digital signal to be recorded, a synchronizing signal and an address signal added for each predetermined capacity of the digital signal are modulated by a modulation circuit (not shown), and are synchronized with an internal reference signal so as to be synchronized with the magnetic head. 8 records on the magnetic tape 1.

At the time of reproduction, first, a target speed 31 and a capping speed are applied to the driving circuit 5 by a speed control loop including a driving circuit 5, a capstan motor 4, a capstan 2, a pinch roller 3, and a subtractor 6, in the same manner as during recording. The error with the stun rotation speed is fed back, and the magnetic tape 1 is caused to run. At this time, since the tape running speed differs depending on the device, the tape running speed at the time of reproduction has an error with respect to the tape running speed at the time of recording. Therefore, in order to reproduce the reproduced signal in synchronization with the reference signal, the tape traveling speed must be adjusted so that the tape traveling speed at the time of recording is obtained, and the phases of the reproduced signal and the reference signal must be matched.

In order to match the tape running speed during reproduction with the tape running speed during recording and to match the phase of the reproduced signal with the reference signal, first, the digital signal reproduced by the magnetic head 8 is converted by the demodulation circuit 9 into a digital signal. Demodulated. The phase error detection circuit 10 detects a synchronization signal and an address signal from the output of the demodulation circuit 9 and measures and outputs a phase error between the detected synchronization signal or address signal and a reference signal using a clock having a sufficiently high frequency. .

Next, a phase gain multiplication circuit 14 multiplies the output of the phase error detection circuit 10 by a predetermined phase gain, and
The signal is converted into an analog voltage by the A converter 16 and output to the adder 7. In the adder 7, the output of the subtractor 6 and the D / A converter 1
6 is input to the drive circuit 5 so that the tape traveling speed at the time of reproduction is adjusted to the traveling speed at the time of recording, the phase of the reproduction signal is adjusted to the reproduction reference signal, and the magnetic tape 1 is recorded at the time of recording. Played at speed.

[0010]

However, in the above-mentioned conventional configuration, when the difference between the tape running speed at the time of recording and the tape running speed at the time of reproduction is large, the value of the phase error when the feedback of the phase error to the drive circuit 5 is started. Is undefined, it takes time to adjust the phase of the reproduction signal to the reproduction reference signal if the phase error is large when the feedback of the phase error to the drive circuit 5 is started. Before adjusting to the reference signal, the phase error detection circuit 1
There is a problem that the limit of the phase detection of 0 is exceeded.

The present invention solves the above-mentioned conventional problems. With a simple configuration, even if the difference between the tape running speed during recording and the tape running speed during reproduction is large, the phase detection limit is exceeded. An object of the present invention is to provide a magnetic tape recording / reproducing apparatus which can quickly adjust the tape traveling speed during reproduction to the traveling speed during recording and adjust the phase of the reproduction signal to the reproduction reference signal.

[0012]

To achieve this object, a magnetic tape recording / reproducing apparatus according to the present invention comprises a capstan driving means for rotating a capstan at a predetermined speed, and a capstan driving means for rotating the capstan at a predetermined speed. A rotation speed determination means for determining whether or not the disk is rotating; and an internal reference signal serving as a reference for processing the reproduced digital signal, and
Reference signal generating means for resetting the reference signal in synchronization with an initially reproduced address signal when the capstan changes from a non-predetermined speed to a predetermined speed, and output from the reference signal generating means. Determine the phase difference between the reference signal and the synchronization signal or the address signal of the reproduction signal,
Phase error detecting means for outputting as a phase error signal, and phase gain multiplying means for multiplying the phase error output from the phase error detecting means by a predetermined constant, and when reproducing the magnetic tape, the capstan driving means The magnetic tape is caused to run at a predetermined speed at which data can be reproduced, and if the rotation speed determining means detects that the capstan is rotating at a predetermined speed, the reference signal generating means is reproduced. The phase error output from the phase error detecting means is multiplied by a predetermined constant, and is fed back to the capstan driving means.

The magnetic tape recording / reproducing apparatus of the present invention may further comprise a capstan driving means for rotating a capstan, and a speed error for obtaining a period of the synchronization signal or the address signal of the reproduction signal and outputting a difference from a target period. Detecting means, speed gain multiplying means for multiplying a speed error output from the speed error detecting circuit by a predetermined constant, and speed error determining for determining whether an output of the speed error detecting means is within a predetermined value. Means for generating an internal reference signal serving as a reference for processing the reproduced digital signal, and when the output of the speed error detecting means changes from a value outside a predetermined value to a value within a predetermined value, the signal is reproduced first. A reference signal generating means for resetting the reference signal in synchronization with an address signal; and a synchronizing signal of a reference signal and a reproduction signal output from the reference signal generating means. Phase error detecting means for obtaining a phase difference from the address signal and outputting the result as a phase error signal; phase gain multiplying means for multiplying a phase error output from the phase error detecting means by a predetermined constant; And an adding means for adding the output of the means and the output of the phase gain multiplying means, when reproducing the magnetic tape,
The magnetic tape is run at a predetermined speed by the capstan driving means, a speed error is obtained from the period of the synchronization signal and the address signal reproduced by the speed error detecting means, and the speed error is calculated by the speed gain multiplying means. After multiplying by a predetermined constant and feeding back the result to the capstan driving means to control the speed error to be equal to or less than a predetermined value, the reference signal generating means is adjusted to the reproduced synchronization signal or address signal. Reset, multiplying the phase error output from the phase error detection means by a predetermined constant, and adding the output of the speed gain multiplication means and the output of the phase gain multiplication means by the addition means,
The output thus added is fed back to the capstan driving means.

[0014]

According to the present invention, when a synchronization signal and an address signal recorded on a magnetic tape are reproduced during reproduction by the above-described structure, the reference signal generating means is adjusted to the reproduced synchronization signal or address signal. After resetting, the phase error output from the phase error detecting means is multiplied by a predetermined constant and fed back to the capstan driving means, so that the phase error when the feedback of the phase error to the capstan driving means is started. Is zero, and even when the difference between the tape running speed at the time of recording and the tape running speed at the time of reproduction is large, before the phase error of the reproduction signal exceeds the limit of the phase detection by the phase error detection means, the speed at the time of reproduction is quickly increased. The tape traveling speed can be adjusted to the recording traveling speed, and the phase of the reproduction signal can be adjusted to the reproduction reference signal.

Further, according to the present invention, when the synchronization signal and the address signal recorded on the magnetic tape are reproduced during reproduction, a predetermined constant is set to the speed error output from the speed error detection circuit. The speed error is controlled to a predetermined value or less by feedback to the capstan driving means. Thereafter, the reference signal generating means is reset in accordance with the reproduced synchronizing signal or address signal. Since the phase error output from the detecting means is multiplied by a predetermined constant and fed back to the capstan driving means, the speed error and the phase error when starting the feedback of the phase error to the capstan driving means are substantially zero. can do.

[0016]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a magnetic tape recording / reproducing apparatus according to a first embodiment of the present invention, FIG. 2 is a block diagram of an internal configuration example of a phase error detection circuit 10, and FIG. 3 is a phase error detection circuit of FIG. FIG. 4 is a main part operation waveform diagram showing signal waveforms at respective portions of FIG. 10, and FIG. 4 is a block diagram of an example of the internal configuration of the reference signal generation circuit 11.

In FIG. 1, 1 is a magnetic tape, 2 is a capstan, 3 is a pinch roller, 4 is a capstan motor, 5 is a drive circuit, 6 is a subtractor, 7 is an adder, 8 is a magnetic head, 9 Is a demodulation circuit, 10 is a phase error detection circuit, 14
Is a phase gain multiplication circuit, 16 is a D / A converter, 31 is a target speed, which are the same as in the conventional example. Reference numeral 30 denotes a capstan rotation speed detected by an FG (frequency generator) (not shown) or the like. Reference numeral 11 denotes a rising edge of the output of the first comparator 12 in synchronization with a rising edge of the first address detection signal when a rising edge of the first comparator 12 is input. Reset,
A reference signal generating circuit 12 for generating a reference signal serving as a reference for processing the reproduction signal compares the output signal of the subtractor 6 with the speed error lower limit value 32, and the output signal of the subtracter 6 is A first output that outputs an H level signal when the output signal of the subtractor 6 is low when the output signal of the subtracter 6 is higher is an L level when the output signal is larger.
The reference numeral 32 denotes a speed error lower limit value representing the lower limit value of the speed error at which the reproduction signal becomes readable, and 13 denotes a rising edge of the address detection signal of 2 after the output signal of the first comparator 12 becomes H level. This is a delay circuit that delays for a period until one or more signals are input. Reference numeral 15 denotes a changeover switch that is turned on or off according to the output of the delay circuit 13.

In FIG. 2, 101 is a clock generator,
Reference numeral 102 denotes a counter which is cleared at the falling of the reference signal 201 and counts the output of the clock generator 101. Reference numeral 103 denotes a synchronization signal or an address signal 20 from the reproduction signal 202.
3 is an address detection circuit for detecting 3; 104 is a latch circuit for latching the count data of the counter 102 at the rising edge of the address detection signal 203; 105 is a subtractor for subtracting the phase difference target value 200 from the output of the latch circuit 104; The latch circuit 104 holds and outputs the number of clock pulses generated by the clock generator 101 during the period from the rising edge of the reference signal 201 to the rising edge of the address detection signal 203, and outputs the phase difference target value 200 by the subtractor 105. The subtracted value is output. Phase difference target value 200
Is set to the number of clock pulses corresponding to the period from the rising edge to the falling edge of the reference signal 201. The phase error signal 204 is set when the rising edge of the output signal of the address detection circuit 103 is equal to the rising edge of the reference signal 201. Is zero, earlier is a negative value, later is a positive value.

If the phase difference between the reference signal 201 and the reproduction signal is larger than a predetermined value, the counter 102 is reset at the falling edge of the reference signal 201 and then the rising edge of the address detection signal 203 is latched. 104
The counter 102 overflows before it is input to. Therefore, the phase difference at which the counter 102 overflows is the limit of the phase error detection.

In FIG. 3, A indicates a change in the reference signal 201, B indicates a change in the output signal of the counter 102, C indicates a change in the output signal of the address detection circuit 103, and D indicates a change in the output signal of the latch circuit 104. E indicates a change in the output of the subtractor 105. The counter 102 is reset at the falling edge of A, and the output signal of the first comparator 12 changes from the L level to the H level at the timing of FF. , The reference signal 201 is reset at the rising edge of C, and the changeover switch 15 is turned on by the delay circuit 13 at the timing of GG.

In FIG. 4, reference numeral 205 denotes a speed error comparison signal output from the first comparator 12, and reference numeral 106 denotes an L level output when the speed error comparison signal 205 is at an L level. A reset signal generation circuit that generates a reset signal that changes from the L level to the H level in synchronization with the first rising edge of the address detection signal 203 when the level changes from the H level to the H level. 107 is a clock generator, 108
Is a frequency divider which is reset at the rising edge of the output signal of the reset signal generation circuit 106 and divides the output of the clock generator 107. As described above, the reference signal 201 is reset and output in synchronization with the first rising edge of the address detection signal 203 after the speed error comparison signal 205 changes from the L level to the H level.

The operation of the magnetic tape recording / reproducing apparatus of the present embodiment configured as described above will be described below.

Since recording is performed in the same manner as in the conventional example,
The playback time will be described. To match the tape running speed during reproduction with the tape running speed during recording, and to match the phase of the reproduced signal with the internal reference signal, first, the drive circuit 5, the capstan motor 4, the capstan 2 , A pinch roller 3, a subtractor 6, and a speed control loop, and a capstan rotation speed 30 and a target speed 3
The capstan 2 is rotated at a predetermined speed by feeding back the error from the value 1. The magnetic tape 1 runs while being driven by a rotating capstan 2 and a pinch roller 3. The first comparator 12 compares the output signal of the subtractor 6 with the speed error lower limit value 32, and outputs an L level when the output of the subtracter 6 is larger than the speed error lower limit value 32. At this time, the changeover switch 15 is turned off. When the absolute value of the output signal of the subtractor 6 is small, that is, when the tape running speed becomes a speed at which data can be reproduced, the first comparator 12 outputs an H level.

Next, when the output signal of the first comparator 12 switches from the L level to the H level, the reference signal generation circuit 11 detects the rising edge thereof, and synchronizes with the next rising edge of the address detection signal 203. To reset and output the reference signal 201. At this time, the phase error signal 20
Reference numeral 4 is indeterminate depending on the value of the counter 102, but is not fed back to the drive circuit 5 because the changeover switch 15 is in the OFF state. On the other hand, in the delay circuit 13,
From when the output signal of the first comparator 12 switches from L level to H level until the phase error signal 204 after the reference signal generation circuit 11 is reset is output, that is, the rising edge of the address detection signal is The output signal of the first comparator 12 is delayed for a period until two or more are input, and output to the changeover switch 15. Therefore, the change-over switch 15 sets the reference signal generation circuit 11 to the reset state and sets the phase error signal 204 to zero.
The state is set to N.

On the other hand, the reproduction signal reproduced by the magnetic head 8 is demodulated into a digital reproduction signal 202 by the demodulation circuit 9, and the reproduction signal 202 is reproduced by the phase error detection circuit 10.
, A synchronization signal or an address signal is detected, a phase error between the address detection signal 203 and the reference signal 201 is measured with a clock having a sufficiently high frequency, and output as a phase error signal 204. Next, in the phase gain multiplication circuit 14,
The phase error 204 is multiplied by a predetermined phase gain and output.

Next, when the changeover switch 15 is turned on by the output of the delay circuit 13, the output of the phase gain 14 is input to the first adder 7 via the D / A converter 16, and 5 to adjust the phase of the reproduction signal 202 to the reference signal 201. In this way, the feedback to the drive circuit 5 is performed after the phase error 204 is reduced to zero, so that the phase of the reproduction signal 202 can be quickly adjusted to the reference signal 201 before the counter 102 overflows.

As described above, according to the present embodiment, the reference signal generating circuit 11 is reset when the rotation speed of the capstan 4 becomes smaller than the lower limit value 32 of the speed error with respect to the target speed 31, and thereafter the detection is performed. Drive circuit 5
When the feedback of the phase error 204 to the drive circuit 5 is started, the phase error becomes zero, and even when the difference between the tape running speed at the time of recording and the tape running speed at the time of reproduction is large, even if the tape running speed at the time of reproduction is large. Before the limit is exceeded, the tape traveling speed during reproduction can be quickly adjusted to the traveling speed during recording, and the phase of the reproduced signal 202 can be adjusted to the reference signal 201.

Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram of a magnetic tape recording and reproducing apparatus according to a second embodiment of the present invention, and FIG.
FIG. 2 is a block diagram showing an example of the internal configuration of FIG.

In FIG. 5, 1 is a magnetic tape, 2 is a capstan, 3 is a pinch roller, 4 is a capstan motor, 5 is a drive circuit, 6 is a subtractor, 7 is a first adder, 8
Is a magnetic head, 9 is a demodulation circuit, 10 is a phase error detection circuit, 11 is a reference signal generation circuit, 13 is a delay circuit, 14 is a phase gain multiplication circuit, 15 is a changeover switch, and 16 is D / D
An A converter, 30 is a capstan rotation speed, and 31 is a target speed, which are the same as those in the first embodiment.
Reference numeral 17 denotes a speed error detection circuit which detects the period of the address detection signal by counting it with an external clock having a sufficiently high frequency, calculates a difference from the target period, and outputs it as a speed error signal. A speed gain multiplication circuit 19 multiplies a gain for feeding back the detected speed error to the drive circuit 5. The speed gain multiplication circuit 19 compares the speed error signal with the speed error lower limit value 33. When the speed error signal is smaller, the H level is increased. The second comparator 20 outputs an L-level speed error comparison signal when the speed error signal is larger. The output signal of the phase gain multiplication circuit 14 input via the changeover switch 15 and the speed gain multiplication circuit A second adder 33 for adding the 19 output signals; and 33, a second adder for detecting the difference between the period of the address detection signal detected from the reproduction signal and the period at the time of recording. A speed error limit value that represents the value.

In FIG. 6, 111 is a clock generator,
Reference numeral 112 denotes a counter, and 113 denotes an address detection circuit for detecting an address signal from the reproduction signal 202. The address detection circuit may also be used as the phase error detection circuit 10. 114 is a delay circuit, 1
Reference numeral 15 denotes a latch circuit, 116 denotes a subtractor, 117 denotes a target cycle output circuit for outputting a target cycle of the address signal, that is, an address signal cycle at the time of recording.
Latches the count signal of the counter 112 at the rising edge of the address detection signal 203. The counter 112 is cleared via the delay circuit 114 immediately after the data is latched in the latch circuit 115. Therefore,
The latch circuit 115 holds the number of clock pulses generated by the clock generator 111 during the output period of the address detection signal 203, counts the output period of the address detection signal 203 by a digital value, and outputs the digital value to the subtracter. Subtractor 11
In step 6, the target cycle output from the target cycle output circuit 117 is subtracted from the output of the latch circuit 115, and the result is output as a speed error signal 206.

The operation of the magnetic tape recording / reproducing apparatus of the present embodiment configured as described above will be described below.

Since recording is performed in the same manner as in the conventional example,
The playback time will be described. To match the tape running speed during reproduction with the tape running speed during recording, and to match the phase of the reproduced signal with the internal reference signal, first, the drive circuit 5, the capstan motor 4, the capstan 2 , A pinch roller 3, a subtractor 6, and a speed control loop, and a capstan rotation speed 30 and a target speed 3
The capstan 2 is rotated at a predetermined speed by feeding back the speed error with respect to 1. The magnetic tape 1 runs while being driven by the rotating capstan 2 and the pinch roller 3, and demodulates a reproduction signal reproduced by the magnetic head 8 into a digital reproduction signal 202 by the demodulation circuit 9.

Next, the speed error detecting circuit 17 detects a synchronizing signal or an address signal from the reproduction signal 202, measures the period of the address detection signal 203 with a clock having a sufficiently high frequency, and measures the measured period and the target period 34. And outputs the result as a speed error signal 206. The speed gain multiplication circuit 18 multiplies the speed error signal 206 by a predetermined gain, outputs the result to the D / A converter 16 via the second adder 20, and adds the output of the D / A converter 16 to the first addition. The output from the subtracter 6 is added to the output from the subtracter 6 and fed back to the drive circuit 5 to control the synchronization signal or the address signal of the reproduction signal 202 so as to have a recording cycle.

The second comparator 19 compares the absolute value of the speed error signal 206 with the speed error lower limit value 33. When the absolute value of the speed error signal 206 is large with respect to the speed error lower limit value 33, the output of the second comparator, that is, the speed error comparison signal 205 becomes L level, and when the absolute value of the speed error signal 206 is small, , The speed error comparison signal 205 becomes H level. Reference signal generation circuit 11
When the speed error comparison signal 205 switches from the L level to the H level, it resets and outputs the reference signal 201 in synchronization with the next rising edge of the address detection signal 203.
Therefore, the phase error signal 204 immediately after the reset becomes zero.

On the other hand, the delay circuit 13 delays the speed error comparison signal 205 for a period from when the reference signal generation circuit 11 is reset to when the phase error signal 204 is output, and outputs it to the changeover switch 15. Therefore, the changeover switch 15 is turned on after the reference signal generation circuit 11 is reset and the phase error signal 204 becomes substantially zero. Although the phase error signal 204 at the time when the reference signal generation circuit 11 is reset is undefined due to the value of the counter 102, the changeover switch 15 is in an OFF state, and is not fed back to the drive circuit 5.

The changeover switch 15 outputs the speed error signal 20
When the absolute value of 6 is larger than the speed error lower limit value 33, the state is OFF, and when the absolute value is small, the state is ON.
The phase error signal 204 is not input to the second adder 20 until the speed error signal 206 becomes smaller than the speed error lower limit value 33. Therefore, by setting the speed error lower limit value 33 to a sufficiently small value, when the phase error signal 204 is input to the second adder 20, the speed error and the phase error can be made substantially zero.

Next, the second adder 20 adds the output signal of the speed gain multiplication circuit 18 and the output of the phase gain multiplication circuit 14 and outputs the result to the D / A converter 16. The output signal of the D / A converter 16 is input to the first adder 7 and fed back to the drive circuit 5 so that the phase of the reproduction signal 202 is controlled so as to follow the reference signal 201. As described above, the phase error signal 204 is fed back to the drive circuit 5 after the speed error and the phase error are both substantially zero, so that the difference between the tape running speed during recording and the tape running speed during reproduction is different. Even if it is large, the phase of the reproduction signal 202 can be quickly and stably changed to the reference signal 2.
01 can be set.

As described above, according to the present embodiment, the difference between the period of the synchronization signal or address signal of the reproduction signal 202 and the target period is obtained, and the difference is fed back to the drive circuit 5 as a speed error. Since the reference signal generation circuit 11 is reset when the value becomes smaller, the detected phase error signal 204 is fed back to the drive circuit 5.
When the feedback is performed, the speed error and the phase error can be made substantially zero.

[0040]

As described above, according to the present invention, at the time of reproduction, the magnetic tape is run at a predetermined speed at which data can be reproduced by the capstan driving means, and the synchronization signal recorded on the magnetic tape is reproduced. When the address signal is reproduced, the reference signal generating means is reset in accordance with the reproduced synchronizing signal or address signal, and thereafter, the phase error output from the phase error detecting means is multiplied by a predetermined constant, Since the feedback to the capstan driving means, the phase error when starting the feedback of the phase error to the capstan driving means is zero,
Even when the difference between the tape running speed during recording and during playback is large, the tape running speed during playback can be recorded quickly before the phase error of the playback signal exceeds the limit of the phase detection operation by the phase error detection means. The phase of the reproduction signal can be adjusted to the reference signal according to the running speed at the time.

According to the present invention, at the time of reproduction, the magnetic tape is run at a predetermined speed at which data can be reproduced by the capstan driving means, and the synchronization signal and the address signal recorded on the magnetic tape are reproduced. Then, the speed error output from the speed error detection circuit is multiplied by a predetermined constant, and is fed back to the capstan driving means to control the speed error to a predetermined value or less. The phase error is reset in accordance with the synchronization signal or the address signal to be reproduced, and thereafter, the phase error output from the phase error detection means is multiplied by a predetermined constant and fed back to the capstan driving means. The speed error and the phase error when starting the feedback to the capstan driving means can be made substantially zero.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a magnetic tape recording / reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of the internal configuration of a phase error detection circuit according to the first embodiment;

FIG. 3 is an operation waveform diagram of a main part of the phase error detection circuit in the first embodiment.

FIG. 4 is a block diagram showing an example of the internal configuration of a reference signal generation circuit according to the first embodiment;

FIG. 5 is a block diagram showing a configuration of a magnetic tape recording / reproducing apparatus according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing an example of the internal configuration of a speed error detection circuit according to the second embodiment.

FIG. 7 is a block diagram showing a configuration of a magnetic tape recording / reproducing apparatus in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Magnetic tape 2 Capstan 3 Pinch roller 4 Capstan motor 5 Drive circuit 6 Subtractor 7 First adder 8 Magnetic head 9 Demodulation circuit 10 Phase error detection circuit 11 Reference signal generation circuit 12 First comparator 13 Delay circuit 14 phase gain multiplying circuit 15 changeover switch 16 D / A converter 17 speed error detecting circuit 18 speed gain multiplying circuit 19 second comparator 20 second adder

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Katsumi Sumida 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Field (Int.Cl. ⁶ , DB name) G11B 15/46

Claims (2)

(57) [Claims] 1. A magnetic tape recording / reproducing apparatus for driving a magnetic tape by a pinch roller and a capstan, adding a synchronization signal and an address signal to a digital signal for each predetermined capacity, and performing recording / reproduction on the magnetic tape. Capstan driving means for rotating the capstan at a predetermined speed, rotation speed determining means for determining whether the capstan is rotating at a predetermined speed, and processing the reproduced digital signal A reference for generating an internal reference signal serving as a reference, and resetting the reference signal in synchronization with an initially reproduced address signal when the capstan changes from a non-predetermined speed to a predetermined speed. Signal generating means for determining a phase difference between a reference signal output from the reference signal generating means and the synchronization signal or the address signal of a reproduced signal. Phase error detection means for outputting a phase error signal; and phase gain multiplication means for multiplying a phase error output from the phase error detection means by a predetermined constant. Means for running the magnetic tape at a predetermined speed at which data can be reproduced, and when the rotation speed determining means detects that the capstan is rotating at a predetermined speed, the reference signal generating means is activated. Reset in accordance with the reproduced synchronization signal or address signal, multiply the phase error output from the phase error detection means by a predetermined constant,
A magnetic tape recording / reproducing apparatus for feeding back to the capstan driving means. 2. A magnetic tape recording / reproducing apparatus which drives a magnetic tape by a pinch roller and a capstan, adds a synchronization signal and an address signal to a digital signal for each predetermined capacity, and performs recording / reproduction on the magnetic tape. Capstan driving means for rotating the capstan; speed error detecting means for obtaining a cycle of the synchronization signal or the address signal of a reproduction signal and outputting a difference from a target cycle; and outputting from the speed error detecting means. Speed gain multiplying means for multiplying the speed error by a predetermined constant; speed error determining means for determining whether or not the output of the speed error detecting means is within a predetermined value; and a reference for processing the reproduced digital signal. When the output of the speed error detecting means changes from a non-predetermined value to a predetermined value, the reproduced signal is reproduced first. A reference signal generating means for resetting the reference signal in synchronization with the address signal, and a phase difference between the reference signal output from the reference signal generating means and the synchronization signal or the address signal of the reproduced signal, Phase error detection means for outputting as an error signal; phase gain multiplication means for multiplying a phase error output from the phase error detection means by a predetermined constant; output of the speed gain multiplication means and output of the phase gain multiplication means And an adder for adding the following.When the magnetic tape is reproduced, the capstan driving unit causes the magnetic tape to run at a predetermined speed, and the synchronization signal and the address signal reproduced by the speed error detecting unit. A speed error is obtained from the cycle, the speed error is multiplied by a predetermined constant by the speed gain multiplying means, and the result is stored in the caption. When the speed error is controlled to a predetermined value or less by feeding back to the button driving means, the reference signal generating means is reset in accordance with the reproduced synchronizing signal or address signal and outputted from the phase error detecting means. The phase error is multiplied by a predetermined constant, the output of the speed gain multiplying unit and the output of the phase gain multiplying unit are added by the adding unit, and the added output is fed back to the capstan driving unit. Magnetic tape recording and reproducing device.