JPH0547906B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a continuous shooting control circuit for a video tape recorder (VTR), and more particularly to improving continuity between intermittent recordings.

FIG. 1 shows a servo circuit of a VTR, and this servo circuit is composed of a drum servo circuit 2 and a capstan servo circuit 4.

The drum servo circuit 2 controls the rotation of the rotary head 6 in synchronization with the vertical synchronization signal of the video signal.
That is, during recording, the DPG signal obtained by the pulse generator coil 8 (hereinafter referred to as DPG coil 8) is
The signal is delayed by a delay circuit 10 and then added to the phase comparator 12. This phase comparator 12 receives a vertical synchronization signal V _D separated from the video signal by a vertical synchronization separation circuit 14 and frequency-divided by a frequency division circuit 16.
It is applied via the recording side contact R of 8.

The output of the phase comparison between the DPG signal and the vertical synchronization signal _V
8 and the added output of both is applied as a rotation control signal to the drum motor 24 to control its rotation.

The frequency-divided signal of the vertical synchronizing signal V _D obtained through the recording side contact R of the switch 30 is applied to the control head 32 to perform magnetic saturation recording on the control track of the magnetic tape 34.

On the other hand, the capstan servo circuit 4
It is installed for stabilizing the speed and switching the speed as necessary, or for tracking servo during playback. capstan 3
6, a pinch roller 38 is pressed against the magnetic tape 34, and during recording, its rotation is detected by a frequency generator 40 (hereinafter referred to as CFG 40). This detection output is discriminated by a frequency discrimination circuit 42 and applied to an adder 44, and after being frequency-divided by a frequency divider 46, it is applied to a phase comparator 50 from a recording side contact R of a switch 48. In this phase comparator 50, this frequency-divided output and the switch 18,
The phase is compared with the vertical synchronizing signal applied via the recording side contact R of 52. The comparison output is applied to an adder 44 via a low-pass filter 54 and added to the output of the frequency discrimination circuit 42, and the rotation of the capstan motor 56 is controlled by this added output.

Further, in such a servo circuit, during reproduction, each switch 18, 30, 48, 52 is switched to the reproduction side contact P. The phase comparator 50 includes a tracking adjustment multivibrator 6 whose trigger signals are the control signal detected by the control head 32 and the reference signal from the reference oscillator 58.
0 (hereinafter referred to as MM60) is added,
The phases of both are compared. Based on this phase comparison output, the rotation of the capstan motor 56 is controlled.

Incidentally, errors in the mounting position of the control head 32 and angle errors between the rotary head 6 and the DPG coil 8 are corrected by adjusting the time constants of the delay circuit 10 and the MM 60.

Portable VTRs are combined with a camera to continuously record intermittent video signals and perform splicing to stabilize the video during playback. This continuous shot is as shown in Figure 2.
The _L1 recording mode is stopped (Bose) at point A by operating the pause button, and in the _L2 section, the magnetic tape 34 is reversed by more than ten frames (shot rewind) and waits (point B). When the pause is released at the point, tape transport starts in the section _L3 (assembly mode), transitions to recording mode in the section shown from point D to _L4 , and 2 or 3 frames between points D and A' are transferred. Recording is performed in such a way that there are no unrecorded portions on the magnetic tape by overlapping recording in sections. In addition, the second
In the figure, arrow t indicates running time, and arrow l indicates tape transport amount.

FIG. 3 shows the recording portion of the magnetic tape in this case, where arrow E indicates the running direction of the magnetic tape 34 during recording, and arrow F indicates the rotation direction of the rotary head 6. A control track 34B is formed on the magnetic tape 34 together with a recording pattern 34A, and a control track 34B is formed along the broken line 3.
The recording pattern and control signal after the splicing shot indicated by 4A' need to be arranged at equal intervals in the spliced portion in order to stabilize the video.

FIG. 4 shows a conventional continuous shooting control circuit, in which the same parts as the servo circuit shown in FIG. 1 are given the same reference numerals. That is, the waveform of the vertical synchronization signal V _D is shaped by the waveform shaping circuit 62 and used as a reference signal.
It is applied to the MM 60 and also to the control head 32 as a control signal during recording. It is assumed that the reproduction side contact P of the switch 52 is switched during the assemble mode. The signal obtained via this switch 52 is applied to a timing circuit 64, the output of which is applied to a phase comparator 50.

In such a continuous shooting control circuit, a vertical synchronization signal is used as a reference signal, a control signal is used as a comparison signal, and an assemble mode is executed.
Capstan system phase servo control is performed.

FIG. 5 shows the operation timing during recording, where A is the reference signal obtained via the waveform shaping circuit 62, and B is the reference signal obtained through the waveform shaping circuit 62.
is a control signal, C and D are reference signals obtained by the timing circuit 64, and F is a CPG signal obtained from the output E of the CFG 40 via the frequency divider 46. The waveform C is formed by the constant radio wave charging circuit of the timing circuit 64, and is formed in synchronization with the reference signal pulse shown in FIG. 5A, and its upper limit voltage is the drive voltage Vcc. That is, the phase comparison is performed by sampling and holding the waveform C at the leading edge of the CPG signal F.

6 shows the operation timing in the assemble mode, G, H, I correspond to the waveforms A, D, C in FIG. 5, and J is the control track 34 during playback.
The control signals K and L reproduced from B correspond to E and F in FIG. 5, and phase comparison is performed by sampling and holding waveform I at the rising edge of the control signal.

That is, as is clear from the comparison of the waveforms I, J, and K in Figure 6, the leading edge of the CPG signal and the control signal are not synchronized, and a phase error of t _D and t _D ' occurs. . This is because the slip occurring between the capstan shaft and the magnetic tape 34 during recording and reproduction causes a phase error during switching.
If this phase error becomes large, a difference will occur between consecutively shot images, impairing smooth image feeding.

SUMMARY OF THE INVENTION Therefore, the present invention aims to provide a splicing control circuit for a video tape recorder that eliminates unrecorded portions between images and improves continuity between images when performing intermittent recording. The purpose is to use a vertical synchronization signal as a signal, and to delay the phase of this vertical synchronization signal to match the CPG phase in the assemble mode.

That is, in the video tape recorder continuous shooting control circuit of the present invention, in the assemble mode, the playback control signal detected from the magnetic tape is added as a reset signal, and in the recording mode, the vertical synchronization signal is added as the reset signal, and the control circuit adds the reproduction control signal detected from the magnetic tape as the reset signal, and controls the arrival of each clock signal. a counter 8 that counts clock signals according to
4, a latch circuit 82 that latches the count value of the counter in response to a rotation detection signal from the capstan side in the assemble mode, and a count value in the assemble mode and the count value of the counter that are latched to this latch circuit during recording. a comparison circuit 86 that detects a time difference signal between the vertical synchronization signal and the rotation detection signal detected from the capstan side, and generates a time difference signal representing the time difference;
The time difference signal of this comparison circuit is the clock input,
a flip-flop circuit 90 to which a vertical synchronizing signal is applied as a data input to generate a correction signal representing the time difference; and a capstan reference signal to which the correction signal is applied from the flip-flop circuit during recording and whose generation timing is delayed by the time difference. and a timing circuit 64 for generating the capstan system reference signal, and is characterized in that, during recording, the generation timing of the capstan system reference signal is delayed by a time difference given by the count value of the counter.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 7 shows a continuous shooting control circuit for a VTR according to the present invention, and the same parts as the circuits shown in FIGS. 1 and 4 are given the same reference numerals.

In Figure 7, terminal 70 is connected to CFG40.
The CFG signal is applied to a counter 72 that constitutes a frequency divider circuit. This counter 72 has
A control signal applied to terminal 74 is applied via switch 76, and counter 72 is reset by this control signal. That is,
As shown in the timing chart of FIG. 5, the counter 72 counts the pulses shown at E, generates the pulses shown at F, and is reset by the pulses shown at B. Therefore, counter 72
generates a CPG signal obtained by frequency-dividing the CFG signal, and sends it to the time difference detection circuit 80 via the switch 78.
has been added to.

The time difference detection circuit 80 digitally counts and detects the time difference between the playback control signal and the CPG signal in the assemble mode, and holds the time difference. It consists of a digital multivibrator. Latch circuit 8
2, the CPG signal of the counter 72 is added,
A control signal is applied to the counter 84 from the terminal 74 via a switch 88, as well as a clock signal CL. In the switches 78 and 88, R is a recording side contact, and R is a non-recording side contact.

The output of the comparison circuit 86 of the time difference detection circuit 80 is
The signal is applied to the C terminal of a D-flip-flop circuit 90 (hereinafter referred to as D-FF circuit 90), and the frequency-divided signal of the vertical synchronization signal from the waveform shaping circuit 62 is applied to the D terminal.

The output of this D-FF circuit 90 is
It is applied to the timing circuit 64 via the recording side contact R of. Further, the output of the multivibrator 60 for tracking adjustment or the waveform shaping circuit 62 is applied to the timing circuit 64 via the non-recording side contact of the switch 92 via the assemble mode side contact ASB of the switch 52. .

Based on the above configuration, its operation is shown in Figures 8 and 9.
This will be explained with reference to the figures.

In the assemble mode, the switch 52 closes to the assemble side contact ABS, the switches 78, 88, and 92 close to the non-recording side contacts, and the switch 76 also closes.

FIG. 8 shows a timing chart in the assemble mode, where A is the control signal from the control head 32 applied to the terminal 74, B is the CPG signal obtained from the counter 72, and C is the signal from the counter 8.
4, and D is the output of the latch circuit 82.

That is, the counting operation of the counter 84 is reset by the control signal, and the counter 84 counts the clock signal. This count value is always added to the latch circuit 82, the CPG signal from the counter 72 is added,
The latch timing is set at its leading edge.
At that timing, the count value of the counter 84 is latched in the latch circuit 82. This operation is repeated during the assemble mode period, and the updated final value is held in the latch circuit 82, which is the amount of delay. Ideally, the latch output shown at D in Figure 8 does not change, but there is a slight difference between the control signal CTL and the CFG signal, and in reality, a certain level difference will occur. This is an exaggerated statement.

Next, FIG. 9 shows a timing chart from the assemble mode to the next recording mode, where E is the output pulse of the waveform shaping circuit 62, F is the count value of the counter 84, G is the output of the comparison circuit 86, and H is the D- This is the output of the FF circuit 90. In F, Nd is the count value held by the latch circuit 82, and when the count value of the counter 84 reaches the count value Nd, the output of the comparison circuit 86 is inverted. This output is D-
This becomes the clock input of the FF circuit 90, and an output Q is generated in response to its leading edge, forming a delay time of _tD .

The output of this D-FF circuit 90 is
1 to the timing circuit 64 to form the timing waveform shown in FIG. 9I, which is applied to the phase comparator 50 of FIG. As is clear from the comparison with the waveform shown in Figure 5C, this delay time is
It occurs at t _D.

In this way, in assemble mode, the time difference between the playback control signal and the CPG signal is digitally counted and detected, and when recording, the capstan reference signal is delayed by that time difference, so the transition from assemble mode to record mode is possible. At the same time, the time deviation of the comparison signal can be corrected on the reference signal side, making it possible to achieve smooth continuous shooting without phase errors.

Comparing these control results with conventional continuous shooting, the maximum phase error during continuous shooting was 360° x (reference frequency/FG frequency), whereas it was 360° x (reference frequency/FG frequency). /counting clock signal frequency of counter 84), which is a significant improvement. Furthermore, in this case, by increasing the frequency of the counting clock signal of the counter 84, the phase error can be reduced to a negligible level.

Note that the multivibrator for time delay during recording can also be used as a time constant circuit for detecting delay amount time in assemble mode, that is, as a delay amount counter, and the circuit configuration can be simplified.

FIG. 10 shows a specific example of the circuit configuration of the time difference detection circuit 80, and the same reference numerals as in the embodiment shown in FIG. 7 are given.

In FIG. 10, the latch circuit 82 is composed of a plurality of registers 94 ₁ , 94 ₂ , 94 ₃ . . . 94 _N ,
The counter 84 includes a plurality of flip-flop circuits 96.
₁ , 96 ₂ , 96 ₃ ...96 _N (hereinafter referred to as FF circuit 96 ₁ , 9
6 ₂ , 96 ₃ ...96 _N ).
A clock signal CL is sequentially applied to each FF circuit 96 ₁ , 96 ₂ , 96 ₃ . . . 96 _N , and each FF circuit 96 ₁ , 9
The outputs Q _{1 , Q 2 ...} Q _M of the registers 94 ₁ , 94 2 , 96 3 ... 94 N are the inputs D ₁ , D ₂ ... of the registers 94 1 _, 94 ₂ , 96 ₃ ... 94 _N.
It is made up of _DM .

The comparison circuit 86 includes AND circuits 98 ₁ , 9
Consisting of 8 ₂ ...98 _N and 100 OR circuits, each
AND circuits 98 ₁ , 98 ₂ ...98 _N are registers 94
₁ , 94 ₂ , 94 ₃ ... 94 _N outputs O ₁ , O ₂ ... O _M ,
FF circuits 96 ₁ , 96 ₂ , 96 ₃ ...96 _N output Q ₁ ,
Q ₂ ...Takes the AND with Q _M , and this output is OR circuit 1
00.

According to such a configuration, it is possible to digitally count and detect the time difference between the playback control in the assemble mode and the CPG signal, and the time difference is stored in the registers 94 ₁ , 94 ₂ , 94 ₃ . . . 94 _N
Therefore, highly accurate delay control can be achieved.

As explained above, according to the present invention, in the assemble mode, the playback control signal and
The time difference with the CPG signal is detected, and when recording, the capstan reference signal is delayed by that time difference, so when transitioning from assemble mode to record mode, the time difference in the comparison signal can be corrected on the reference signal side, and the phase error Smooth continuous shooting can be performed without any blemishes, and when intermittent recording is performed, unrecorded portions between images can be eliminated and continuity between images can be improved.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the servo circuit of a VTR, Fig. 2 is an explanatory diagram showing splicing, Fig. 3 is an explanatory diagram showing the recording state of magnetic tape, and Fig. 4 is a conventional splicing control circuit. 5 is an explanatory diagram showing the operation timing during recording, FIG. 6 is an explanatory diagram showing the operation timing in assemble mode, and FIG. 7 is an embodiment of the VTR continuous shooting control circuit of the present invention. FIG. 8 is an explanatory diagram showing the operating timing in the assemble mode, FIG. 9 is an explanatory diagram showing the operating timing in recording, and FIG. 10 is a specific circuit configuration example of the digital time constant circuit. FIG. 64...Timing circuit, 80...Time difference detection circuit, 82...Latch circuit, 84...Counter,
86...Comparison circuit, 90...Flip-flop circuit.

Claims (1)

[Claims] 1. In the assemble mode, a reproduction control signal detected from the magnetic tape is added as a reset signal, and in recording, a vertical synchronization signal is added as a reset signal, and clock signals are counted according to the arrival of each clock signal. a counter; a latch circuit that latches the counted value of the counter in response to a rotation detection signal from the capstan side in the assemble mode; and a counted value in the assemble mode and the counted value of the counter that are latched in the latch circuit during recording; a comparison circuit that detects a time difference signal between the vertical synchronization signal and the rotation detection signal detected from the capstan side and generates a time difference signal representing the time difference; a flip-flop circuit to which a vertical synchronizing signal is applied as a data input and generates a correction signal representing the time difference; and a capstan reference whose generation timing is delayed by the time difference by applying the correction signal from the flip-flop circuit during recording. A timing circuit for generating a signal; and a continuous shooting control circuit for a video tape recorder, characterized in that during recording, the generation timing of the capstan reference signal is delayed by a time difference given by the count value of the counter. .