JPH03252953A - Capstan phase control circuit - Google Patents

Abstract

PURPOSE:To stabilize the control of a capstan by connecting a correcting means to a comparison signal generating means so that the phase difference of a signal can be corrected by changing the output period of a comparison signal when a mode is switched from an ASB mode to an REC mode. CONSTITUTION:This correcting means is connected to the comparison signal generating means so that the phase difference of the signal can be corrected by changing the output period of the comparison signal when the mode is switched from the ASB mode to the REC mode. Therefore, a sampling pulse to be generated by both output signals such as an ASB output signal to be outputted from a signal means for ASB and a REC output signal to be outputted from a signal means for recording is always made coincident with the reference position of the comparison signal. Thus, a capstan phase control circuit can prevent the capstan phase from being distorted when the mode is switched from the ASB mode to the REC mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a capstan phase control circuit used in a magnetic recording/reproducing device having an assemble mode.

[Prior Art] A video tape recorder (VTR) is a magnetic recording and reproducing device.
) is designed to run the tape through the rotation of the capstan. At this time, the video track, which is a recording band of information signals recorded on the tape, has a very narrow width and is formed in the width direction, making it difficult to match the head scanning. Therefore, normal VT
R is provided with a capstan phase control circuit that controls the rotation of the capstan and enables tracking control.

In addition, some recent VTRs have added value by being equipped with editing functions such as splicing, and when performing splicing, recording (R
A capstan phase control circuit equipped with an assemble (ASB) mode for controlling the capstan phase is employed as in the case of EC).

Conventionally, the above-mentioned capstan phase control circuit uses a playback control signal (playback C
ASB having a CTL-P frequency division counter circuit 45 which uses TL-P) as a capstan phase system sampling pulse.
a recording signal circuit 41 which uses the C-PC signal obtained by dividing the frequency of the C-FC signal from the frequency generator provided in the capstan as a sampling pulse of the capstan phase system, and the above-mentioned ASB signal circuit 40; A changeover switcher 43 that switches the signal circuit 40 and the recording signal circuit 41 between ASB mode and REC mode, and an output signal inputted through this changeover switcher 43 as a sampling pulse, and a capstan output signal based on this sampling pulse. It consists of a phase control circuit 44 that controls the phase.

As a result, a magnetic recording/reproducing device such as a VTR equipped with the above-mentioned capstan phase control circuit has a reproduction CTL of A38.
By constantly controlling the capstan phase by switching between -P and the C-PC signal in the REC mode, continuous shooting can be performed.

(Problems to be Solved by the Invention) However, the conventional capstan phase control circuit described above has a problem in that the control of the capstan phase when switching from ASB mode to RPC mode is insufficient.

That is, in the ASB mode, the reproduction C of the recording signal circuit 41
The output signal which is TL-P is used as a capstan phase system sampling pulse, and in the REC mode, the output signal which is a C-FC signal of the recording signal circuit 41 is used as a capstan phase system sampling pulse. There is.

At this time, the above C-PC signal is converted into the following C-PC signal as shown in FIGS. It is formed by starting counting at the rising edge of .

Therefore, the phase of the C-PC signal is shifted by a maximum of one cycle of the C-FC signal from the phase of the reproduced CTL-P.
will have the following. And this delay time t is AS
When switching from the B mode to the REC mode, the phase control circuit 44 determines that there is a phase lag, and controls the capstan to speed up the rotation so as to correct this phase lag. As a result, the horizontal synchronization signal (H-3Y
This results in a misalignment in the alignment of the images (NC), resulting in skew distortion on the monitor.

In this way, the conventional capstan phase control circuit
Capstan phase control is insufficient due to the delay time t, which is a phase difference that occurs when switching from B mode to REC mode. Therefore, in the present invention, AS
It is an object of the present invention to provide a capstan phase control circuit that can stabilize capstan phase control and prevent skew distortion by correcting the phase difference that occurs when switching from B mode to REC mode.

[Means for Solving the Problems] In order to solve the above problems, the capstan phase control circuit according to the present invention uses a playback control signal (
ASB signal means for outputting an ASB output signal based on the reproduction CTL-P); a recording signal means for outputting an RPC output signal obtained by frequency-dividing a CFG signal from a frequency generator provided in the capstan; a switching means for switching the ASB output signal and the REC output signal between the ASB mode and the REC mode; a sampling pulse generating means for using the ASB output signal and the REC output signal inputted through the switching means as sampling pulses; a comparison signal generating means for outputting a comparison signal at time intervals of , and a control means comprising a C-APC counter circuit and a C-APC error detection circuit for controlling the capstan phase so that the sampling pulse becomes the reference position of the comparison signal. In the capstan phase control circuit having a capstan phase control circuit, the comparison signal generating means is configured to detect the phase difference between the ASB output signal and the REC output signal by changing the output timing of the comparison signal when switching from the ASB mode to the REC mode. It is characterized in that a correction means for correction is connected.

[For production]

According to the above configuration, the capstan phase serves as the reference position of the comparison signal between the sampling pulse formed by the ASB output signal output from the ASB signal means and the REC output signal output from the recording signal means. It is controlled by controlling as follows.

At this time, the above comparison signal is output from the comparison signal generating means at regular time intervals, and the output timing is constant, but this output timing is changed when switching from ASB mode to REC mode. It will be changed by the correction means. This change in output timing makes it possible to correct the phase difference between the ASB output signal outputted from the ASB signal means and the REC output signal outputted from the recording signal means, and the above-mentioned Riki Okayama signal. The generated sampling pulse will always coincide with the reference position of the comparison signal.

This makes it possible for the capstan phase control circuit to prevent disturbance of the capstan phase when switching from ASB mode to REC mode, thereby making it possible to prevent skew distortion.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

As shown in FIG. 1, the capstan phase control circuit according to the present embodiment is an AS system that outputs an ASB output signal based on a playback control signal (playback CTL-P) from a tape.
an ASB signal circuit 1 which is a B signal means; and a recording signal circuit 2 which is a recording signal means which divides the frequency of a C-FG multiplied signal from a frequency generator provided in a capstan and outputs a REC output signal. have.

The ASB signal circuit 1 described above is connected to an input terminal 6 into which the reproduced CTL-P is input, and this input terminal 6 is
The ASB signal circuit 1 is branched into two, and one terminal is connected to one terminal 7a of the changeover switcher 7 via an inverter 8.
The other terminal is connected to the other terminal 7b of the changeover switcher 7. As a result, the reproduced CTL-P during reverse playback is input to the common terminal 7C of the changeover switcher 7 by connecting the common terminal 7c and the terminal 7a, while the Regeneration CTL-P
is input by connecting the common terminal 7c and the terminal 7b.

The above common terminal 7c is connected to the CTL-P frequency dividing counter circuit 9.
This CTL-P frequency dividing counter circuit 9
When performing special playback modes such as fast-forward playback, the playback C
The frequency of TL-P is divided into two or three. The CTL-P frequency dividing counter circuit 9 in the ASB mode and the REC mode is in a through state with a frequency division ratio of 1, and the approximately 30 Hz reproduction CTL-P for capstan phase control used in the ASB mode is set to a through state with a frequency division ratio of 1. It is designed to output an ASB output signal equivalent to P.

On the other hand, the recording signal circuit 2 is connected to an input terminal 10 to which the C-FG multiplied signal is input. This input terminal 10 is
It is connected to the C-FC frequency division counter circuit 11 in the recording signal circuit 2, and this CFG frequency division counter circuit 11 is
For example, divide the 720Hz C-FC signal by 1/2 and divide it into 36
The frequency is set to 0Hz. The C-FC frequency dividing circuit 11 is connected to the capstan speed system control circuit 12 and also to the C-PC frequency dividing circuit 13.

The above C-PG frequency division counter circuit 13 is connected to the CTL and -P frequency division counter circuit 9 of the ASB signal circuit 1, and the output signal from this CTL-P frequency division counter circuit 9 is a reproduction signal. CTL-P is input. This CPG frequency division counter circuit 13 is reset at the rising edge of the reproduction CTL-P described above, and outputs approximately 307 outputs for capsun phase control used when switching from ASB mode to REC mode. It is designed to output a signal.

C-PC frequency divider circuit 1 that outputs the above output signal
3 is one terminal 3 of a changeover switcher 3 which is a switching means.
This terminal 3b is connected to the common terminal 3C in the REC mode. Also,
The other terminal 3a of the above changeover switcher 3 is CTL-
It is connected to the P frequency division counter circuit 9, and this terminal 3a
is connected to the common terminal 3C in the ASB mode.

The common terminal 3C of the changeover switcher 3 is connected to a C-APC sampling pulse generation circuit 14 which is sampling pulse generation means of the phase control circuit 4. This C-APC sampling pulse generation circuit 14 receives an ASB output signal or an R
A sampling pulse is generated at the rising edge of the EC output signal, and this sampling pulse is output to a C-APC counter circuit 15, which constitutes a control means together with a C-APC error detection circuit 17, which will be described later. It has become. And this C-APC counter circuit 1
5 compares the phase of the C-APC trapezoidal wave, which is a comparison signal created internally, with the above sampling pulse and converts it to C-APC.
The comparison counter value is output.

The above (,-APC counter circuit 15 has an output side of C-
It is connected to a C-APC error detection circuit 17 that outputs the APC comparison counter value as a C-APC error amount. On the other hand, the C-APC counter circuit 15 includes a C-APC counter preset decoder circuit 16 which is a comparison signal generating means.
is connected, and this C-APC counter precent decoder circuit 16 receives a video head switching signal (video H
3t-P) and outputs a start signal to start counting for creating the trapezoidal wave described above. A video H-3WP circuit 18 that outputs the video head switching signal described above is connected to this C-APC counter preset decoder circuit 16, and this video H3W-P circuit 18 operates in ASB mode and R
In both EC modes, the video vertical synchronization signal (V-3YNC
) is used to determine the phase.

Further, an arithmetic circuit 5 which is a correction means is connected to the C-APC counter preset decoder circuit 16, and this arithmetic circuit 5 is connected to an arithmetic microcomputer 19 connected to the CAPC counter preset decoder circuit 16. , is connected to this calculation microcomputer 19, and the above-mentioned C
It consists of a CTL-P/C-PC phase detection circuit 20 connected to a TL-P frequency division counter circuit 9 and a C-PC frequency division counter circuit 13.

The above CTL-P/C-PC phase detection circuit 20 has a counter that counts at a frequency obtained by dividing the color subcarrier frequency fic of approximately 3.58 MHz of the NTSC system by 1/2, for example. The counter is configured to count the time from the rising edge of the reproduced CTL-P from the CTL-P frequency division counter circuit 9 to the rising edge of the C-FC signal from the C-PC frequency division counter circuit 13. This count value is input to the calculation microcomputer 19, and the calculation microcomputer 19 calculates a C-APC counter value (M) for correcting the output timing of the start signal based on the count value.

In the above configuration, the operation of the capstan phase control circuit will be explained below based on the timing charts of FIGS. 2 and 3.

First, the reproduced CTL-P is transferred to the CTL-P via the changeover switcher 7 in which the common terminal 7C and the terminal 7b are connected.
The frequency division counter circuit 9 is manually inputted. This CTL-P frequency division counter circuit 9 passes the reproduced CTL-P at a frequency division ratio of 1, and the reproduced CTL-P, which is the ASB output signal, is sent to the terminal 3a of the changeover switcher 3, CTL-P/C-PC. It will be output to the phase detection circuit 20 and the C-PC frequency dividing circuit 13.

As shown in FIG.
The rising edge of -P forms a C-PG reset pulse. Then, this C-PG reset pulse is
This causes the PG frequency division counter circuit 13 to reset the count of the manually inputted C-FG signal, and the C-PG frequency division counter circuit 13 whose count has been reset is
Counting will start again from the C-FC signal following the FG signal. As a result, the c-pc frequency division counter circuit 13
outputs a REC output signal having a delay time t of about one cycle of the C-FG signal with respect to the reproduced CTL-P output from the CTL-P frequency division counter circuit 9.

The REC output signal of the c-pc frequency division counter circuit 13 is connected to the terminal 3b of the changeover switcher 3 and the CTL-P/C
-10 is output to the phase detection circuit 20. This CTL-P
/C-10 phase detection circuit 20 detects C-10 from the rising edge of reproduced CTL-P of CTL-P frequency division counter circuit 9.
The time until the rising edge of the output signal of the PC frequency division counter circuit 13 is counted, and this counted value is calculated by the microcomputer 19.
This will require manual labor. Then, the calculation microcomputer 19 corrects the delay time t based on the above count value (, -
The APC counter value (M) will be calculated.

When switching from ASB mode to REC mode, the above C-APC counter value (M) replaces the C-APC counter value (N) that was output in AsB mode.
The signal is output to the APC counter preset decoder circuit 16. As a result, the C-APC counter circuit 15
As shown in the figure, the rise timing of the trapezoidal wave due to the start signal from the C-APC counter preset decoder circuit 16 is delayed by the C-APC counter value (M), and this delay is caused by the changeover switcher 3. The sampling pulse formed by the output signal inputted through is always located at the center, which is the reference position. and,
The C-APC counter circuit 15 converts the C-APC comparison counter value located at the center of the trapezoidal wave to the C-APC counter circuit 15.
Output to the error detection circuit 17, C-APC error detection circuit 1
7 outputs the C-APC comparison counter value that does not include the delay time t as (, -APC error amount).

In this way, the capstan phase control circuit of this embodiment is
Even when switching from ASB mode to REC mode, the output timing is corrected so that the sampling pulse is located at the center of the trapezoidal wave of the capstan phase system. Therefore, in the capstan phase control circuit, the delay time t of the output signal that occurs when switching from ASB mode to REC mode does not affect capstan phase control, and the capstan phase control circuit It is now possible to match records and later records.

This alignment of H-3YNC prevents the occurrence of skew distortion and enables good continuous shooting.

In this embodiment, the calculation microcomputer 1 of the calculation circuit 5
Although the delay time t is corrected in step 9, the present invention is not limited to this. For example, the count value of the CTL-P/C-10 phase detection circuit 20 may be directly transferred to the C-APC counter preset decoder circuit 16. The C-APC counter value (N) set in ASB mode is changed to C-APC counter value (N) in REC mode.
-APC counter value (M) [Effects of the Invention] As described above, in the capstan phase control circuit according to the present invention, when switching from ASB mode to REC mode,
A correction means for correcting the phase difference between the ASB output signal and the REC output signal by changing the output timing of the comparison signal is connected to the comparison signal generation means.

As a result, when switching from ASB mode to REC mode, the phase difference between the ASB output signal and the REC output signal is corrected by changing the output timing of the comparison signal, so the deviation between the sampling pulse and the reference position of the comparison signal Therefore, the prevention of this shift stabilizes the control of the capstan phase, and has the effect that it becomes possible to prevent skew distortion.

[Brief explanation of drawings]

1 to 3 show one embodiment of the present invention. FIG. 1 is a block diagram of a capstan phase control circuit. FIG. 2 is a timing chart showing signal states of the capstan phase control circuit. FIG. 3 is a timing chart showing the signal states of the recording signal circuit. 4 to 6 show conventional examples. FIG. 4 is a professional diagram of the capstan phase control circuit. FIG. 5 is a timing chart showing signal states of the capstan phase control circuit. FIG. 6 is a timing chart showing the signal states of the recording signal circuit. 1 is an ASB signal circuit (ASB signal means), 2 is a recording signal circuit (recording signal means), and 3 is a changeover switcher (
4 is a phase control circuit, 5 is an arithmetic circuit (correction means), and 4 is a C-APC sampling pulse generation circuit (
15 is a C-APC counter circuit (control means), 16 is a C-APC counter precent decoder circuit (comparison signal generation means), 17 is CA
This is a PC error detection circuit (control means).

Claims (1)

[Claims] 1. ASB signal means for outputting an ASB output signal based on a reproduction control signal, and a C-
a recording signal means for outputting a REC output signal obtained by dividing the frequency of the FG signal; a switching means for switching the ASB output signal and the REC output signal between ASB mode and REC mode; sampling pulse generation means that uses the ASB output signal and the REC output signal as sampling pulses; comparison signal generation means that outputs a comparison signal at regular time intervals; In the capstan phase control circuit, the comparison signal generating means is configured to calculate the phase difference between the ASB output signal and the REC output signal of the comparison signal when switching from the ASB mode to the REC mode. A capstan phase control circuit characterized in that a correction means for correcting by changing the output timing is connected.