JPH0616340B2 - Playback speed controller - Google Patents

Description

The present invention relates to a reproduction speed control device for a motor that keeps a signal reproduction speed of a tape, a disk, etc. constant.

An analog signal is converted to a digital signal by an analog-digital converter, a sync signal is added at each signal break and recorded, and the sync signal is detected from the read digital signal during playback, and based on this sync signal. The PCM recording method that reproduces a digital signal and reproduces an analog signal at the time of recording by a digital-analog converter has the advantage that sound quality is not deteriorated without being affected by distortion of the recording medium, and its spread is expected. .

In PCM recording, the digitally converted signal is further modulated and recorded as a train of several different pulse width signals. One example is shown in FIG. (a) shows an example of the contents of recorded signals, and (b) shows a sequence of digital signals when viewed as an electrical signal. In Fig. 1, T is the unit clock cycle, and it is called "High level" of 11T.
This is an example of the case where a combined signal of 11T "Low level" is used as a synchronizing signal and the information signal is recorded as an example of a pulse of 10T or less and 3T or more. The display of 3T to 10T in (b) shows the width of the pulse of "High level" and "Low level". Therefore, in this example, 11T and 11T "Hi
When there is a combination of gh level and "Low level", it can be identified as a synchronization signal.

FIG. 2 shows an example of the structure of a reproducing apparatus for reproducing a PCM signal recorded on a disc by such a method.

In FIG. 2, reference numeral 1 is a display, 2 is a pickup, 3
Is a motor, 4 is a code demodulator, 5 is a sync signal detector, 6 is a digital processor, 7 is a digital-analog converter,
8 is a frequency / voltage converter (hereinafter referred to as -v converter),
Reference numeral 9 is a reference value, and 10 is an error amplifier.

The signal read from the disc 1 by the pickup 2 is
The signal is demodulated by the code demodulator 4 into a digital acid signal before recording and modulation, and then input to the sync signal detector 5 and the digital processor 6. The sync signal detector 5 detects and reproduces a sync signal from the recorded signals. The digital processor 6 discriminates the digital signal based on this synchronizing signal, corrects an error that occurs during transmission, and reproduces an analog signal by the digital-analog converter 7. By the way, the reading speed of the signal must be controlled so that the synchronizing signal has a constant interval. That is, the rotation speed of the motor 3 for rotating the disk 1 must be controlled so that the synchronizing signal becomes a constant interval, and the reproduced synchronizing signal of the synchronizing signal detector 5 is converted into a voltage signal by the -v converter 8 and the error amplifier It is returned to the motor 3 via 10 and the number of rotations of the motor 3,
That is, the rotation speed of the disk 1 is controlled. The voltage source 9 provides a reference voltage for rotating the disc 1 at a predetermined speed.

In the above description, the rotation of the disk 1, that is, the motor 3 rotates at a predetermined speed, the code demodulator 4 can correctly determine the pulse width of the information signal and the pulse width of the synchronization signal, and the output of the synchronization signal detector 5 It has been assumed that the reproduced sync signal is obtained.

However, as can be seen from the width of the signal pulse shown in FIG. 1, it can be determined whether the signal is a synchronization signal or an information signal.
It must be possible to distinguish between T and pulse widths of 10T or less. That is, as shown in FIG. 3, the sync signal detector 5 has a limited range in which the sync signal can be detected and reproduced. FIG. 3 shows a range in which the sync signal can be detected in the vicinity of the target speed. In this range, the speed control is performed, but in the range in which the sync signal cannot be detected, the information on the disc 1 is no longer reproduced. It will be impossible.

In particular, the disk 1 has a constant linear velocity (Co
nstant Linear Velocity (called CLV) is recorded. When reproducing the disc 1 recorded by CLV, the rotation speed of the motor 3 varies depending on the position of the pickup 2. That is, the rotation speed of the motor 3 must be reduced as the pickup 2 moves toward the outer circumference of the disk 1. When playing such a disc, a problem occurs at the time of starting. Assuming that the motor 3 is applied so that the rotation speed increases while the output of the -v converter 8 is not present, a reproduction sync signal can be transiently obtained by the sync signal detector 5, but The rotation speed of the motor 3 cannot necessarily be skillfully controlled due to the response characteristic of. A further problem is that when the position of the pickup 2 is randomly moved beyond the detection range of the synchronization signal detector 5, it is not possible to identify where in (3) of FIG. 3, and the rotation of the motor 3 should be made faster or slower. You will not be able to obtain information on what to do.

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a reproduction speed control device which always has a predetermined rotation speed.

Therefore, the present invention has been recorded. Using the fact that PCM signals are signals with several different pulse widths, the pulse width of a specific pulse (for example, the maximum pulse width, which will be described later using the maximum pulse width) is detected, and this pulse width is detected. Also, the first speed control loop for pulling the motor rotation speed into the operating range 12 of the sync signal detector and the sync signal for reproduction of the sync signal detector are predicted by predicting the current sync signal interval from the length of And a second speed control loop for performing the above control. The first speed control loop is used until the sync signal is detected by the sync signal detector, and the second speed control loop is used after the sync signal is detected. This is because it is controlled by the speed control loop.

FIG. 4 shows the basic idea of the present invention. The first speed control loop pulls the speed into the sync signal detectable range,
It is intended to control the target speed by switching to the second speed control loop with the detection and reproduction of the sync signal.
Therefore, in FIG. 4, is the operating range of the first speed control loop, and is the operating range of the second speed control loop.

FIG. 5 shows an example of the speed control device according to the present invention. The same symbols as in FIG. 2 indicate the same items. Until the sync signal can be reproduced by the sync signal detector 5, the maximum pulse width in the signal read by the pickup 2 from the disc 1 is detected and updated by the maximum pulse width detector 11 at regular intervals, and the pulse width is updated. The voltage converter 12 converts the pulse width signal into voltage, and the switching device
13 is connected to the (a) side to drive the motor 3. This loop is called the first speed control loop. The first speed control loop operates in the area shown in FIG. When the rotation of the motor 3 falls within the sync signal detectable range of the sync signal detector 5 by the above control, the sync signal is detected and reproduced by the sync signal detector 5, so the switching device 13 is set to the (b) side. By connecting and rotating the motor 3 (this is called a second speed control loop), it is possible to control the target speed at any time. If the maximum pulse width can always be detected accurately and reliably, the speed control can be performed only by the first speed loop.

However, it is not preferable to perform the speed control only by the first speed control loop for the following reasons.

1) The signal read from the pickup 2 is temporarily lost due to scratches or dust adhering to the disc 1, and the signal level becomes H level or L level during this period. At this time, if the speed control is performed only by the first speed control loop that keeps the pulse width of the signal constant, there is no signal change during this period, so it is determined that the disk 1 is not rotating, and the motor 3 The control loop operates so as to apply a voltage to the disk to increase the rotation speed of the disk 1.

On the other hand, in the second speed loop, the sync signal detection circuit 5 can be provided with the ability to replenish the sync signal when the signal is lost due to scratches on the disk 1 or the like. As a result, by supplementing the synchronizing signal during the flaw period, rotation control can be performed without giving a large disturbance to the speed control loop.

2) In the first speed control loop, the control by the maximum pulse width is performed by observing the length of the pulse width 11T, whereas the second speed control loop is much longer than 11T. Speed control is performed by looking at the synchronization signal period (MT). As a result, the speed detection by the second speed control loop can detect the speed fluctuation more finely and perform the control.

3) The first speed control loop performs speed control by detecting the length of the maximum pulse width 11T. 11T is because it is always recorded in the synchronizing signal portion shown in A _1, A 2 _--- in Figure 1, the pulse width detector 15 ₁ detects a maximum pulse width from the signal read from the pickup 2 If the rotation speed of the motor is slower than the target speed, the maximum pulse width cannot be detected unless the rotation speed of the motor is set longer than the synchronization signal cycle when the rotation speed of the motor is the target speed.

On the other hand, in the second speed control loop, the speed is detected and controlled in the synchronization signal cycle, so that the speed fluctuation detection cycle can be set shorter and the rotation control can be performed more accurately.

For the above reasons, it is not preferable to perform the speed control only by the first speed control loop. Until the signal read from the disk 1 has almost the same speed as that at the time of recording, the control is performed by the first speed control loop. When the sync signal detection circuit 5 detects the sync signal, the speed control is performed by the second speed control loop, so that the speed control can be performed quickly at the time of retraction and more stable and accurate after the retraction. .

FIG. 6 shows another embodiment of the present invention. In FIG. 5, the switching device 13 is automatically switched by the discriminating circuit 14 for discriminating whether or not the synchronizing signal can be detected by the synchronizing signal detector 5. Different from the example.

Another embodiment of the present invention is shown in FIG. Reference numeral 15 denotes a pseudo sync signal generator, which is different from the example of FIG. 6 in that the switching device 13 is placed in front of the −v converter 8. The pseudo sync signal generator 15 has, for example, a configuration example shown in FIG. Before the description of FIG. 7, the operation of FIG. 8 will be described using the signal example of FIG. Reference numeral 15 ₁ is a pulse width detector, which uses different width pulse widths from the pickup 2 as a reference clock generator 15 ₅
Count with the reference clock of. 15 ₂ is a pulse width detector
Value of more pulse width most count value among detected in 15 ₁ is the maximum pulse width detectors registered number. FIG. 9 shows a process in which the disk 1 starts rotating from a stationary state and a signal is correctly read.

The motor 3 starts rotating at the point indicated by p in the figure.

The signal recorded on the disc 1 from here is picked up by the pickup 2
However, the synchronizing signal detector 5 is outside the synchronizing signal detectable range B shown in FIG. 4, and the synchronizing signal cannot be detected.

As a result, the discrimination circuit 14 selects the switching device 13 to the side (a) and controls the speed of the motor in the first speed control loop based on the output of the pseudo sync signal generator 15.

Here, the pseudo sync signal generation circuit 15 operates as described below. Among the period of each pulse width of the eighth diagram of a pulse width detector 15 ₁ and a maximum pulse width detector 15 ₂ in the signal reproduced by the pickup 2 were counted, determined by the timing circuit 15 _6, the pulse width detection circuit 15 _The maximum pulse width detected by ₁ is output.

At start-up, the rotation speed of disk 1 is lower than the target rotation speed.
Pulse widths longer than 1T are counted. Here, description will be made assuming that the counted value is 22T and the synchronization signal period M is 588T. At this time, the calculator 15 ₃ is made to receive the output of the maximum pulse width detector 15 ₂ and to output the following values.

Maximum pulse width detector 15 ₂ output Operator 15 ₂ output 5 267 11 588 22 1176 That is, it is designed to output a value of (maximum pulse width detector 15 ₂ output) × 588/11.

This can be predicted synchronizing signal period from the output of the maximum pulse width detector 15 _2. That is, if 11T output of the maximum pulse width detector 15 _2, the rotation of the disk 1 is approximately at the target rotational speed, to the synchronization signal period is 588T, the maximum pulse width detector immediately after startup 15
If the output of ₂ is 22T, the rotation of the disk 1 is about half of the target rotation speed, and the synchronizing signal cycle is 2 of 588T.
It can be predicted to be about double that of 1176T.

Predicting a synchronizing signal period from the maximum pulse width Thus, entering this value as a frequency division ratio of the timing device 15 _4.
A clock timed device 15 ₄ in the reference clock generator 15 ₅ divides to generate a pseudo sync signal.

The pseudo sync signal thus generated is the pseudo sync signal output shown in FIG. 9, and is detected from the point p at which the disk 1 starts rotating. This output does not match the phase of the sync signal of the signal reproduction output, but has the same cycle.

By the first speed loop based on this pseudo sync signal, the rotation speed of the disk 1 approaches the target rotation speed,
As shown in FIG. 4, the sync detection range 5 is entered and the sync signal starts to be detected by the sync detector 5.

When the sync signal starts to be detected, the discrimination circuit 14 switches the switching device 13 to the (b) side, and the second circuit based on the sync signal is detected.
Switch to the speed loop of. Q of FIG. 9 immediately after switching
At the point, the sync signal is shortened by one sync period, but the motor 3
Does not respond to such a period disturbance, so there is no problem in practice.

Since the synchronizing signal input to the fV converter 8 continuously changes in this way, the rotation of the motor 3 can be smoothly controlled.

In this way, the output of the switching device 13 selects the pseudo sync signal from the start to the pull-in (from p to q in FIG. 9),
A synchronization signal is selected from the pull-in point (q in FIG. 9).

In this way, the speed is controlled by switching between the two detection circuits for detecting the rotation speed of the disk 1.

In FIG. 7, the pseudo sync signal obtained by the pseudo sync signal generator 15 is used to connect the switching device 13 to the (a) side until the sync signal detector 5 operates to form the first speed control loop. Then, when the sync signal can be detected and reproduced by the sync signal detector 5, the switching device 13 is switched to the (b) side to form the second speed control loop to control the speed of the motor 3. Since the signals of the first and second speed control loops in the example of FIG. 7 are the same at the same frequency and at the target speed, as shown in the examples of FIGS. There is no gain variation occurring between the voltage converters 12, and there is an advantage that the switching of the switching device 13 can be performed smoothly.

As described above, according to the present invention, since the pseudo sync signal generator 15 is provided, the motor can be rotated at a predetermined target speed at any time even when the sync signal detection range is narrow. Further, although the present invention has been described by taking the disc reproducing apparatus as an example, it goes without saying that the present invention is not limited to the disc.

[Brief description of drawings]

FIG. 1 is a waveform diagram showing an example of a PCM signal recording method, and FIG.
FIG. 4 is a block diagram showing a configuration example of a conventional disc reproducing apparatus, FIG. 3 is an explanatory diagram for explaining problems in the conventional apparatus, and FIG. 4 is an explanatory diagram showing a basic concept of the present invention.
5 is a block diagram showing an embodiment of the present invention, FIG. 6 is a block diagram showing another embodiment, FIG. 7 is a block diagram showing still another embodiment, and FIG. 8 is a block diagram showing FIG. FIG. 9 is a circuit diagram of the pseudo sync signal generator 15, and FIG. 9 is an operation explanatory diagram of FIGS. 7 and 8. 1: Disc, 2: Pickup, 3: Motor, 4: Code demodulator, 5: Synchronous signal detector, 8: Frequency / voltage converter, 10: Error amplifier, 11: Specific pulse width detection device, 12: Pulse width Voltage converter, 13: switching device, 14: judging device, 15: pseudo sync signal generator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeki Inoue, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Household Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Taka Takeuchi, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi Home Appliances Research Laboratory (72) Inventor Shinichi Ohashi Inside 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Inside the Hitachi Home Appliances Research Laboratory (56) Reference JP-A-57-211612 (JP, A)

Claims (1)

[Claims] 1. The synchronizing signal is used after the rotation speed of a motor for rotating a recording medium on which digital data including a synchronization signal having a constant pulse width and a maximum pulse width is recorded is brought into a constant rotation speed range including a target speed. In a rotation control playback device, a sync signal detection circuit that detects the sync signal when the playback signal is played back by the playback device is within a certain speed range including the motor rotation speed target speed, and the playback signal is played by the playback device. Pseudo sync signal generator for detecting the pulse width of the reproduction signal and generating a pseudo sync signal having a cycle obtained from the maximum pulse width among the detected pulse widths, the output of the pseudo sync signal device and the sync signal detection When the sync signal is not detected by the sync signal detection circuit, the output of the circuit is input and the output of the pseudo sync signal device is output. A switching circuit that outputs the output of the synchronization signal detection circuit when the synchronization signal detection circuit detects the synchronization signal, and a frequency-voltage converter that frequency-voltage converts the output selected by the switching circuit A reproduction speed control device for controlling rotation of the motor by comparing an output of the frequency / voltage converter with a reference voltage corresponding to a synchronization signal period at the target speed.