JP2972751B1 - Program debug support circuit and its debug support method - Google Patents

Abstract

An object of the present invention is to provide a program debug support circuit and a debug support method capable of giving arbitrary data to a program at an arbitrary timing. SOLUTION: As shown in FIG. 1, a debug support circuit (1) according to the present embodiment includes an interface section (5), an insert trigger circuit (3), an insert memory section (4), a selector (2), The interface unit (5) transmits data necessary for the operation of the debug support circuit (1) from the processor (7) to the processor bus (S).
Receive through 1). One piece of data has a bit length of “the number of all signal lines−1” between the processor (7) and the peripheral device, and one signal line is assigned to one bit.
Since only the bus clock is excluded from all signal lines, "-
1 ".

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program debug support circuit, and more particularly to a program debug support circuit for simulating the operation of a peripheral device in which an address bus, a data bus and a bus control signal line are connected to a central processing unit. Belongs to debugging support method.

[0002]

2. Description of the Related Art Conventionally, a program operation has been confirmed by providing a tracer memory or a tracer register and analyzing collected trace data. For example,
Japanese Patent Laying-Open No. 5-66964 describes a technique for diagnosing a running route of firmware using a memory for a tracer.

[0003]

However, in the prior art, it is only possible to collect signals transmitted and received between a central processing unit (hereinafter, referred to as a processor) and peripheral devices. Cannot be given at an arbitrary timing. Therefore, if the peripheral device does not operate normally, a normal signal is not transmitted and received between the processor and the peripheral device, and debugging of the program is impossible. Conversely, when the peripheral device operates normally, the failure handling operation of the program to be executed when the peripheral device fails cannot be confirmed. Another problem is that it is not possible to confirm the operation of the program when a plurality of events occur simultaneously.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a program debug support circuit and a debug support method capable of giving arbitrary data to a program at an arbitrary timing. The point is to provide.

[0005]

The gist of the present invention is a program debug support circuit for firmware, which receives data necessary for the operation of the debug support circuit from a central processing unit through a processor bus. An interface unit, an insert trigger circuit for monitoring the processor bus based on data received from the interface unit, and, according to an instruction of the insert trigger circuit, the set data and a signal from a peripheral device are transmitted to the processor bus. There is provided a program debug support circuit comprising: a selector for switching and transmitting; and an insert memory unit for transmitting data received from the interface unit to the selector in response to a data transmission instruction from the insert trigger circuit. The gist of the present invention is that the data received by the interface unit from the central processing unit is six types of data from first data to sixth data, and is "1" in bit units.
Or "0" is set, first data transmitted to the central processing unit in place of the peripheral device, second data for specifying validity or invalidity of the first data in bit units, The first data set to “1” or “0”, the signal line to be monitored among the signals of the processor bus, the fourth data to be compared with the third data, and the It is characterized by comprising: fifth data for setting “1” or “0”; and sixth data for designating a signal line to be monitored among the signals of the processor bus and comparing with the fifth data. A program debug support circuit according to claim 1. The gist of the present invention is that the first data and the second data are set in the insert memory unit by the interface unit using an internal bus, and the third data and the fourth data are set in the insert memory unit. 3. The program debug support circuit according to claim 1, wherein the data, the fifth data, and the sixth data are set in the insert trigger circuit. The gist of the present invention according to claim 4 is a program debugging support method for firmware, wherein the insert trigger circuit receives the third program received from the interface unit.
Monitor the processor bus based on the data and the fourth data,
When the same data as the third data appears on the signal line to be monitored, a data transmission instruction is issued to the insert memory unit,
The selector instructs the selector to transmit the data of the insert memory unit to the processor bus, and the insert memory unit transmits the stored first data and second data to the data transmission from the insert trigger circuit. In response to the instruction, the selector transmits the first data specified by the second data while receiving the instruction to transmit the data of the insert memory unit to the processor bus from the insert trigger circuit. The insert trigger circuit continues to transmit a valid field to the processor bus, and the insert trigger circuit receives the fifth field received from the interface unit.
The processor bus is monitored based on the data and the sixth data, and when the same signal as the fifth data appears on the monitored signal line, an instruction to send the data of the peripheral device to the processor bus is issued to the selector. Wherein the selector sends the signal of the peripheral device to the processor bus while receiving an instruction from the insert trigger circuit to send the signal of the peripheral device to the processor bus. It lies in the debugging support method. The gist of the present invention according to claim 5, is that the insert memory unit receives the first data received from the interface unit.
5. The program debug according to claim 4, wherein the data and the second data are stored in the insert memory unit in the order of transmission, and the first data is transmitted to the selector in accordance with a transmission instruction from the insert trigger circuit. Be in the way of support. The gist of the present invention is that the same number of the third data and the fourth data are set in the insert trigger circuit, and the same data as the third data appears on the signal line to be monitored. Each time, an instruction to send data to the processor bus is issued to the insert memory unit and the selector, and monitoring under the monitoring conditions set by the next third data and fourth data is resumed. A program debugging support method according to claim 4 or 5 is provided. The gist of the present invention described in claim 7 is:
The same number of the fifth data and the sixth data are set in the insert trigger circuit, and each time the same data as the fifth data appears on the signal line to be monitored, the data of the peripheral device is sent to the selector. The program according to any one of claims 4 to 6, wherein a transmission instruction to the processor bus is issued, and monitoring under the monitoring condition set by the next fifth data and sixth data is resumed. It lies in the debugging support method. The gist of the present invention described in claim 8 is:
A storage medium storing a program capable of executing the program debugging support method according to any one of claims 4 to 7.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. As shown in FIG. 1, the debug support circuit (1) according to the present embodiment is schematically configured by an interface unit (5), an insert trigger circuit (3), an insert memory unit (4), and a selector (2). The interface unit (5) receives data necessary for the operation of the debug support circuit (1) from the processor (7) through the processor bus (S1). One piece of data has a bit length of “the number of all signal lines−1” between the processor (7) and the peripheral device, and one signal line is assigned to one bit. Since only the bus clock is excluded from all signal lines,
-1 ".

[0007] There are the following six types of data. First, there are two types of data for generating data to be sent to the processor bus (S1) in place of the peripheral device (6), which are referred to as first data and second data. The first data is a peripheral device (6)
To be sent to the processor (7) in place of
"1" or "0" is set for each bit, that is, for each signal line. The second data specifies validity or invalidity of the first data in bit units. Valid is "1", invalid is "
0 "is set. The signal of the first data set to be valid by the second data is sent to the processor bus (S1),
The data set as invalid is not sent to the processor (7), and the signal from the peripheral device (6) reaches the processor (7) as it is on the corresponding signal line.

Next, there are two types of data for generating a timing for sending a signal to the processor bus (S1).
These are referred to as third data and fourth data. The third data is
"1" or "0" is set for each bit, that is, for each signal line. The fourth data specifies a signal line to be monitored among the signals of the processor bus (S1). “1” sets the corresponding signal line to be monitored, and “0” does not. When the signal appearing on the signal line to be monitored on the processor bus (S1) matches the third data, the data generated from the first data and the second data is sent to the processor bus (S1). The non-monitored fields of the third data are invalid.

Next, there are two types of data for generating a timing for stopping signal transmission to the processor bus (S1), which are referred to as fifth data and sixth data. The fifth data sets "1" or "0" in bit units, that is, in signal line units. The sixth data specifies a signal line to be monitored among the signals of the processor bus (S1). “1” sets the corresponding signal line to be monitored, and “0” does not. When the signal appearing on the signal line to be monitored of the processor bus (S1) matches the fifth data, the transmission of the signal to the processor bus (S1) is stopped.

The interface section (5) uses the internal bus to set the first data and the second data in the insert memory section (4), and sets the third to sixth data in the insert trigger circuit (3). .

The insert trigger circuit (3) monitors the processor bus (S1) based on the third and fourth data received from the interface section (5), and outputs the same data as the third data to a monitored signal line. Appears, a data transmission instruction is issued to the insert memory unit (4), and at the same time, an instruction is transmitted to the selector (2) to transmit the data of the insert memory unit (4) to the processor bus (S1).

The processor bus (S1) is monitored based on the fifth data and the sixth data received from the interface section (5), and when the same signal as the fifth data appears on the monitored signal line, the selector ( Instruct 2) to send the data of the peripheral device (6) to the processor bus (S1).

A plurality of settings can be made for the third data and the fourth data. In this case, the same number is set for both data. Each time the data transmission start timing is detected based on the third data and the fourth data, the monitoring of the processor bus (S1) is restarted under the next monitoring condition. A plurality of settings can be made for the fifth data and the sixth data. In this case, the same number is set for both data.

Whenever the data transmission stop timing is detected based on the fifth data and the sixth data, the monitoring of the processor bus (S1) is restarted under the following monitoring conditions.

The insert memory unit (4) stores the first data and the second data received from the interface unit (5),
The data is transmitted to the selector (2) in response to a data transmission instruction from the insert trigger circuit (3). A plurality of data to be transmitted can be set. The data is stored in the insert memory section (4) according to the transmission order, and is transmitted from the first data to the selector (2) in order each time a transmission instruction is received from the insert trigger circuit (3).

The selector (2) receives the instruction from the insert trigger circuit (3) to send the data of the insert memory section (4) to the processor bus (S1) while the second data specified by the second data. Only the valid field of one data is sent to the processor bus (S1). Also, while receiving an instruction from the insert trigger circuit (3) to send the signal of the peripheral device (6) to the processor bus (S1), the signal of the peripheral device (6) is sent to the processor bus (S1).
To send to.

When reading the data of the peripheral device (6), the processor (7) supplies the peripheral device (6) with an address signal for specifying the peripheral device (6) mapped on the I / O address and the processor (7). 7) sends a transfer control signal indicating that it is in the data reading state. When the reading is completed, the polarity of the transfer control signal is inverted. These signals are set in the insert trigger circuit (3) as data for generating a transmission start timing or a transmission stop timing, and data transmitted by the peripheral device (6) is set in the insert memory unit (4). The operation of the peripheral device (6) can be simulated. That is, when the address signal of the peripheral device (6) and the transfer control signal in the read state appear on the processor bus (S1), a signal is transmitted from the insert memory unit (4), and the polarity of the transfer control signal is inverted. Then, the transmission is stopped. Therefore, even if there is no peripheral device (6), the operation of the program can be confirmed. The processor (7) has a ROM
(8) and a RAM (9) are provided.

FIG. 2 is a block diagram showing the configuration of the interface unit (5). The interface unit (201)
The comparator (1) monitors the appearance of the I / O address assigned to the debug support circuit (1) on the processor bus so that the processor (7) can access the debug support circuit (1) itself as one peripheral device. 205). The comparator (205) is connected to the I of the debug support circuit (1).
When the / O address matches the address appearing on the processor bus (S1), "1" is output. Since the debug support circuit (1) requires two consecutive I / O address spaces, the least significant bit of the address is ignored for comparison.

The least significant bit of the address is a NOT circuit (2
06) via the address register (2
08) or write data register (2
09) or read data register (210).

The address register (208) is controlled by an AND circuit (212) so that the address match signal (207) from the comparator (205) is "1" and the lowest order of the address bus is "0", that is, the NOT circuit (206). Is "1", the write / read control signal line (2) from the processor (7)
17) Data is taken in at the leading edge of the write pulse.

The write data register (209) stores A
The address match signal (207) from the comparator (205) is "1" and the lowest address bus is "1" by the ND circuit (213), that is, the output of the NOT circuit (206) is "0".
At this time, data is fetched at the leading edge of the write pulse on the write / read control signal line (217) from the processor (7).

Read Data Register Register (21)
0) is output from the comparator (205) by the AND circuit (214).
When the address coincidence signal (207) from the processor (7) is "1" and the least significant bit of the address bus is "1", that is, when the output of the NOT circuit (206) is "0", When the line (217) is inactive, the data on the internal data bus at that time is sent to the data bus on the processor side.

The differentiating circuit (211) comprises a processor (7)
Differentiating the trailing edge of the write pulse of the write / read control signal line (217) from "0" to "1" from "0"
Generates a pulse returning to 0 ". AND circuit (218)
Pass this pulse only when the lowest order of the address bus is "1".

The output of the address register (208), the output of the write data register (209), the input of the read data register (210), and the output of the AND circuit (218), as shown in FIG. Become a bus.

Table 1 shows the correspondence between I / O addresses and data on the processor bus (S1), and Table 2 shows the correspondence between addresses and data on the internal bus.

[0026]

[Table 1]

[0027]

[Table 2]

When data is set from the processor (7) to the internal address of the debug support circuit (1), Table 1
The internal bus address data is set by the internal bus address writing, and then the write data is set by the internal bus writing. In this way, it is realized by two I / O accesses.

When reading, the internal bus address data is set by writing the internal bus address shown in Table 1, and then the internal bus data is read to read the data. This is also realized by two I / O accesses.

FIG. 3 is a block diagram showing the structure of the insert trigger circuit (3). Insert trigger circuit (30
1) Insert start trigger setting memory (303)
And an insert start trigger mask memory (304);
It has an insert stop trigger setting memory (312) and an insert stop trigger mask memory (313).

The four memories have the same circuit, and FIG. 4 is a block diagram showing the circuit configuration. The comparator (402) compares the upper 4 bits of the address of the internal bus with a unique identification number assigned to its own circuit. If they match, "1" is output. This identification number is "1" in the insert start trigger setting memory (303), "2" in the insert start trigger mask memory (304), "3" in the insert stop trigger setting memory (312), and "3" in the insert stop trigger mask memory (313). It is "4".

The flip-flop (404) latches the least significant bit (414) of the internal data bus (409) at the rise of the write / read control signal. At this time, the output of the comparator (402) is "1" and the address (40
The upper 5 bits (413) of 8) must be "1". When the output of the flip-flop becomes "1", the selector (403) determines the address (408) from the internal bus.
Is selected, and when it becomes "0", the address (411) from the address counter is selected.

The memory (406) is a memory for storing trigger data. Data length is processor bus (S1)
"Total number of signal lines-1". For example, when the processor bus (S1) includes 32 address buses, 32 data buses, and 20 control lines, 32 + 32 + 20−
1 = 83 bits. Since only the bus clock is not subject to trigger data, it is set to "-1".

Data writing is performed in the following sequence. First, the identification number is assigned to the upper 4 bits of the internal address bus, “1” is assigned to the upper 5 bits, and the internal data bus (40
The least significant bit of 9) is set to "1", and a write pulse is generated on the write / read control signal line (410).
In this operation, the interface unit (5) is operated by the processor (7)
It is realized by being accessed from. This sets the flip-flop (404) and sets the selector (403)
Selects the address of the internal bus, and selects the selector (40
The output of 3) becomes an address input of the memory. At this point, since the upper 5 bits are "1", the write pulse does not reach the memory (406) due to NOT (415) and AND (405). Next, an identification number is assigned to the upper 4 bits,
Specifying "0" in the upper 5 bits and the address of the memory in the lower bits, setting the data to be written in the data section and generating a write pulse, the upper 5 bits of the internal address are now set to "0". Therefore, the write pulse reaches the memory (406), and data is written. Until "0" is set to the flip-flop (404), data can be continuously written to the memory.

The data written in the memory (406) can be read. Reading of data is performed in the following sequence. First, flip-flop (404)
Must be set to "1", which is the same as in the case of writing. Next, the memory (406) sends data to the internal data bus (409) when the upper 4 bits specify the identification number, the upper 5 bits specify “0”, and the lower bits specify the memory address. This data is read into the processor (7) through the interface section (5).

When the own circuit is not selected, that is, when the output of the comparator (402) is "0", the gate (4) is connected to the internal data bus (409) to prevent data collision.
07). The gate (407) is connected to the comparator (40
When the output (412) of 2) is "0", the output to the internal data bus is set to high impedance.

Further, all four circuits are provided with a reset circuit (30
Input a reset pulse from 7). When the reset pulse is input, the flip-flop is set to “0”. That is, the address is obtained from the address counter.

In FIG. 3, an insert trigger circuit (30
1) has an address counter 1 (302). The address counter 1 (302) receives the output (322) of the comparator 1 (305) as an input. Address counter 1 (30
2) counts up by one each time a pulse signal is received from the comparator 1 (305). This count value is output to the insert start trigger setting memory (303) and the insert start trigger mask memory (304). Also,
When a reset signal is input from the reset circuit (307), the count value is set to 0. The address counter 2 (311) performs the same operation. However, the address counter 2 (31
1) is connected to the comparator 2 (310), the insert stop trigger setting memory (312), and the insert stop trigger mask memory (313).

In FIG. 3, an insert trigger circuit (30
1) AND1 (306), AND2 (309) and A
Four ANDs of ND3 (320) and AND4 (321)
Circuit. These AND circuits perform an AND operation on the two signal lines of “total number of signal lines−1” of the processor bus (S1) for each bit, and output as a signal of the total number of signal lines−1. The value of “−1” is because the signal lines constituting the processor bus (S1) do not include the bus clock signal.

The AND1 (306) receives signals from the insert start trigger setting memory (303) and the insert start trigger mask memory (304) as input, and sends the ANDed result to the comparator 1 (305). AND2 (3
09) receives the signals from the entire processor bus except for the bus clock and the signal from the insert start trigger mask memory (304), and sends the AND result to the comparator 1 (305). The AND3 (320) receives as input the signals from the entire processor bus except the bus clock and the insert stop trigger mask memory (313), and sends the ANDed result to the comparator 2 (310). AND4 (321) is
A signal from the insert stop trigger setting memory (312) and the signal from the insert stop trigger mask memory (313) are input, and an AND result is sent to the comparator 2 (310).

In FIG. 3, an insert trigger circuit (30
1) has a comparator 1 (305) and a comparator 2 (310). The two comparators compare two signal lines of the total number of signal lines of the processor bus (S1) minus one. The comparison is performed in synchronization with the bus clock. When they match, a pulse signal is output from "0" to "1" and returning to "0". It has an interface with the internal bus (325), and can instruct the start / stop of detection from the interface unit (5). Further, it is connected to the reset circuit (307), and stops the comparison operation when receiving a reset pulse from the reset circuit (307).

The input of the comparator 1 (305) is AND1
(306) and AND2 (309), and output (3
24) is connected to the input of the address counter 1 (302) and the set terminal of the latch (308). It is also output to the insert memory section (4).

The input of the comparator 2 (310) is AND3
(320) and AND4 (321), and output (3
23) is ORed with the input of the address counter 2 (311)
1 (326).

In FIG. 3, the insert trigger circuit (30
1) has a latch (308). Latch (308)
When a pulse is input to the set terminal, the output (31
Send “1” to 5). When a pulse is input to the reset terminal, "0" is sent to the output (315). set
/ Reset type flip-flop is constituted by one. The set terminal is connected to the output (324) of the comparator 1 (305), and the reset terminal is connected to the output of OR1 (326). Since the input of the OR1 is connected to the output (323) of the comparator 2 (310) and the reset circuit (307), a pulse is output from the comparator 2 (310) or the reset circuit ( When the reset pulse is input from 307), the output (315) becomes “0”. The output is sent to the selector (2).

In FIG. 3, the insert trigger circuit (30
1) has a reset circuit (307). The reset circuit has an interface with the internal bus (325), and receives a reset instruction from the interface unit (5). When a reset instruction is received, a reset pulse is output to a reset signal line (314). The reset signal includes an address counter 1 (302) and an address counter 2 (31).
1), an insert start trigger setting memory (303), an insert start trigger mask memory (304), an insert stop trigger setting memory (312), an insert stop trigger mask memory (313), and a comparator 1 (30).
5), comparator 2 (310), and OR1 (326). When the address counter 1 (302) and the address counter 2 (311) receive the reset pulse,
Reset the counter to zero. Insert start trigger setting memory (303), insert start trigger mask memory (304), and insert stop trigger setting memory (3)
12) and insert stop trigger mask memory (31)
3) When the reset pulse is received, the address value of the internal memory is obtained from the address counter.
Comparator 1 (305) and comparator 2 (310) stop the comparison operation upon receiving the reset pulse.

Since the OR1 (326) drives the reset terminal of the latch (308), the output of the latch (308) becomes "0".

FIG. 5 is a block diagram showing the structure of the insert memory (501). Insert memory (501)
Has an insert data memory (503) and an insert mask memory (504). The circuit configuration of these two memories is the same as the configuration of the memory shown in FIG. 4 used in the insert trigger circuit (301). The identification number of the insert data memory (503) is "5",
The identification number of the insert mask memory (504) is "6"
It is.

The insert data memory (503) and the insert mask memory (504) are both connected to the address counter 3 (502), the internal bus (509) from the interface unit (5), and the reset circuit (505). . As other connection destinations, the insert data memory (503) has an insert data register (506).
, And the insert mask memory (504) is connected to the insert mask register (507).

In FIG. 5, insert memory (501)
Has an address counter 3 (502). The address counter 3 (502) receives the output (324) of the comparator 1 (305) of the insert trigger circuit (3) as an input. It counts up each time a pulse is input from here. The count value is output to the insert data memory (503) and the insert mask memory (504). When a reset pulse is received from the reset circuit (505), the counter value is cleared to "0".

In FIG. 5, insert memory (501)
Has a reset circuit (505). The reset circuit has an interface with the internal bus (509) and receives a reset instruction from the interface unit (5). When receiving the reset instruction, the reset signal is output to the reset signal line (510). The reset signal is transmitted from the address counter 3 (502) and the insert data memory (50).
3), an insert mask memory (504), an insert data register (506), and an insert mask register (507). Address counter 3 (5
02) resets the counter to 0 upon receiving a reset pulse. Upon receiving the reset pulse, the insert data memory (503) and the insert mask memory (504) acquire the address value of the internal memory from the address counter. The insert data register (506) and the insert mask register (507)
When a reset pulse is received, its contents are cleared to "0".

The insert data memory (503) and the insert mask memory (504) have the address counter 3
The data specified in (502) is transmitted. Since the address counter 3 (502) is cleared to 0 at the time of reset, the data of the address 0 has already been selected at this time by the selector (2).
Has been sent to. The signal which is the mark of the first start trigger detection from the insert trigger circuit (3) is compared with the signal of the comparator 1 (305)
, When the first data transmission timing is reached, the address counter 3 (502) is incremented by one, so that the data at address 1 is transmitted and the data at address 0 is invalid without being transmitted. Will be.
The insert data register (506) and the insert mask register (507) prevent this and ensure that data is transmitted from address 0, which is the head address of the memory.
Is installed at the position shown in FIG. Since these two registers take in the data of the insert data memory (503) or the insert mask memory (504) with the pulse from the insert trigger circuit (3), the contents of the address 0 are surely detected from the time of detecting the first start trigger. Is sent to the selector (2). That is, the address counter 3 (50
This is a circuit for sending data of the next lower address to the selector (2) from the addresses of the insert data memory (503) and the insert mask memory (504) indicated by 2). The reason why the same mechanism is unnecessary in the insert trigger circuit (301) is that the data for detecting the start trigger is used before the detection of the start trigger, and the data sent to the processor bus (S1) upon the start trigger is used after the detection of the start trigger. To do that.

FIG. 6 is a block diagram showing the structure of the selector (2). A circuit (602) including an AND (603), a gated three-state driver (604), a NOT (605), and a gated bidirectional driver (306).
Has a “signal line total number−1” set of the processor bus (S1). The output (315) of the latch (308) of the assert trigger circuit is ANDed with the output (512) of the insert mask register (507) of the insert memory (501).
The AND operation is performed in (603), and the gated three-state driver (604) or the bidirectional three-state driver (6
06). When the input of the three-state driver with gate (604) is passed, the output (511) of the insert data register (506) from the insert memory (501) is input to the data input of the three-state driver with gate (604). S
Sent to 1). Bidirectional 3-state driver (60
When the data of 6) is passed, the processor (7) and the peripheral device (6) transmit and receive signals in two directions. Also,
When the bidirectional driver is shut off, data is shut off in both directions.

Hereinafter, the operation of the present embodiment will be described with an example. Assume the following conditions. The firmware is provided with a failure notification routine for periodically monitoring a failure of the peripheral device (6) for a predetermined time and detecting a failure three times in succession when the failure is detected three times in a row. I do.

It is assumed that a peripheral device (6) that normally operates is prepared for the running environment of the firmware. It is also assumed that there is an in-circuit emulator as another firmware operation checking device.

When a fault occurs, the peripheral device (6) displays the fault in a fault display register. When the fault display register is read from the processor (7), it is cleared if the fault factor has disappeared at that time. If the failure factor continues, it will be displayed again. This peripheral device (6)
Of the I / O address "A000000"
It is assumed that it is mapped to address 0. In the event of a fault, the least significant bit is set to "1" in the fault display register, and the bit is set to "0" in the normal state.

The read cycle in the processor bus (S1) is as shown in FIG. In FIG. 7, R / W (703) indicates a read cycle when "1" and a write cycle when "0".
TS (704) is a transfer control signal. When "0", the peripheral device (6) captures an address, and when "1", the processor (7) captures data.

First, the debug support circuit (1) is reset. The reset is realized by performing two write operations on the I / O address mapped to the debug support circuit itself.

In the first writing, the internal bus address data is written as "0" at an address whose least significant bit is "0" among the I / O addresses mapped to the debug support circuit itself. Thus, 0 is set in the address register (208) of the interface unit (5), and 0 is output to the address bus of the internal bus.

In the second write, a write operation is performed on an address whose least significant bit is 1. Although the internal bus write data value at this time is invalid, the trailing edge of the write pulse accompanying the write operation becomes a pulse by the differentiating circuit (211), and this pulse becomes an input to the AND circuit (218). Further, since the writing is performed with the least significant bit being 1, this AND circuit (218) includes a differentiating circuit (2
The pulse input from 11) is input to an AND circuit (218).
To the output of

In the debug support circuit, the reset circuit (307) of the insert trigger circuit (3) and the reset circuit (505) of the insert memory (501) are mapped with the internal bus address being 0.
One reset circuit receives a pulse from the AND circuit (218) and transmits it as a reset pulse to each circuit in the debug support circuit.

The reset pulse corresponds to the address counter 1
(302), address counter 2 (311), address counter 3 (502), insert start trigger setting memory (303), insert start trigger mask memory (304), and insert stop trigger setting memory (3).
12) and insert stop trigger mask memory (313)
And insert data memory (503), insert mask memory (504), comparator 1 (305) and comparator 2
(310).

When reset, the address counter 1 (3
02), the counter values of the address counter 2 (311) and the address counter 3 (502) become 0. Insert start trigger setting memory (303), insert start trigger mask memory (304), insert stop trigger setting memory (312), insert stop trigger mask memory (313), and insert data memory (503).
Then, the insert mask memory (504) acquires the address value of the internal memory from the address counter. The comparator 1 (305) and the comparator 2 (310) stop the comparison operation. The output of the latch (308) is "
0 ".

Next, an insert start trigger setting memory access start instruction is performed. Insert start trigger setting Memory access start instruction is similar to the reset method described above,
This is realized by performing two write operations on the I / O address mapped to the debug support circuit itself. However, the upper 5 bits of the internal bus address data are 3 and the internal bus write data is 1.

As a result, 3 is set in the upper 5 bits of the address register (208), 1 is set in the write data register (209), and a pulse is output from the AND circuit (218).

The reason why the internal bus address is mapped as 3 in the debug support circuit is that the flip-flop (40) in the insert start trigger setting memory (303) is mapped.
4). This flip-flop latches the internal bus write data at this time with the output from the AND circuit (218).

As a result, the flip-flop (404) in the insert start trigger setting memory is set to 1, the selector (403) selects the address of the internal bus, and the memory (406) can be accessed from the internal bus. Become.
That is, Tables 1 and 2 are transmitted via the interface unit (5).
And can be set based on

Next, data is written to the insert start trigger setting memory. In the case of this example, “A00000000” appears in the processor bus address (702), and R
The fact that / W (703) becomes "1" and TS (704) becomes "0" is used as an insert start trigger. In order to set this condition by writing the insert start trigger setting memory data, the insert start trigger setting memory address is set to “0”, and the write data is stored in the processor bus (S1).
"A000000" in the address line field
0, "1" in the R / W field, and "0" in the TS field.In order to cause a fault three times, the insert start trigger setting address is repeatedly set as "1" and "2". .

Next, an insert start trigger setting memory access stop instruction is issued. This resets the flip-flop (404) in the insert start trigger setting memory, and the selector (403) sets the address counter 1 (30).
2) Select the address.

Another insert start trigger mask memory (304) and an insert stop trigger setting memory (31)
2) and insert stop trigger mask memory (313)
And the insert data memory (503) and the insert mask memory (504) can be written in the same procedure as the insert start trigger setting memory (303).
That is, access to each circuit is started, data is written next, and access is finally stopped.

Next, an insert start trigger mask memory (304) is set. Now, the signal lines to be monitored in the processor bus (S1) are the address signal of the processor bus, the R / W signal, and the TS signal. Therefore, the field corresponding to the processor bus address (702) and the R / W
“1” is set in the field of (703) and the field of TS (704). The other fields are set to “0”. A signal set to “1” is a target of an insert start trigger, and a signal set to “0” is not a target of an insert start trigger.

As in the insert start trigger setting memory, the set addresses are repeatedly set as "1" and "2".

Next, the insert data memory (503) is set. Set the least significant bit of the fault display register to “1”
Therefore, data for setting this field to "1" in the data line of the processor bus (S1) is set. As in the insert start trigger setting memory, the set address is repeatedly set as "1" and "2".

Next, the insert mask memory (504) is set. The insert mask memory (504) specifies which signal line of the processor bus (S1) to insert data. For the signal line not specified, the signal from the peripheral device (6) reaches the processor (7) as it is. In this example, since it is desired to insert only the least significant bit of the fault display register, data is set so that this field in the data line of the processor bus (S1) is "1".

As in the case of the insert start trigger setting memory, the set addresses are repeatedly set as "1" and "2".

Next, writing of insert stop trigger setting memory data is performed. In the case of this example, the condition that “A00000000” appears in the processor bus address (702), the R / W (703) becomes “1”, and the TS becomes “1” is used as an insert stop trigger. The insert stop trigger setting memory address is “0”, the write data is “A00000000” in the address line field and “R / W” field in the address line field of the processor bus (S1).
1 "and" 1 "in the TS field.

As in the insert start trigger setting memory, the set addresses are repeatedly set as "1" and "2".

Next, an insert stop trigger mask memory (313) is set. In the case of this example, the field corresponding to the processor bus address (702) and the R / W (7
03) in the field of TS (704).
1 ". Other fields are set to" 0 "."
The signal set to 1 "is the target of the insert stop trigger.

As in the case of the insert start trigger setting memory, the set addresses are repeatedly set as "1" and "2".

Next, the trigger detection is started based on Table 2. The detection is started based on the set data.

Immediately after the start of the detection, the address counter 1 (30
Since the count value of 2) is "0", the contents of the address 0 are read from the insert start trigger setting memory (303) and the insert start trigger mask memory (304). By the above setting, "A00000000" and R / W are stored in the field corresponding to the address line of the processor bus (S1) at the address 0 of the insert start trigger setting memory.
Since “1” is written in the field corresponding to TS and “0” is written in the field corresponding to TS,
One of the inputs is ND1 (306). AND1
The other data of (306) is the contents of address 0 of the insert start trigger mask memory. This means that the address line of the processor bus (S1), the R / W line,
The field corresponding to the line is “1” and the other fields are “0”. Therefore, the output of AND1 (306) is
The field corresponding to the address line of the processor bus (S1) is "A00000000", the field corresponding to the R / W line is 1 and the field corresponding to the TS line is "0". 1 (305)
Is one of the inputs. The other input is the data on the processor bus and the output of the insert start trigger mask memory (304), which are ANDed by AND2 (309).
Calculated and input.

In order for the firmware to perform fault monitoring,
When the fault register is read, the processor bus (S
Data of "A00000000" appears on the address line, "1" appears on the R / W line, and "0" appears on the TS line in 1).

The comparator 1 (305) compares inputs in synchronization with the bus clock. Therefore, an input match is detected at T1 (706). If they match, comparator 1 (305) outputs a pulse at its output (324). This pulse sets the latch (308) and sends "1" to the selector (2). The AND (603) of the selector (2) receives this signal and passes the output (512) of the insert mask register (507) of the insert memory (501).

The pulse sent from the comparator 1 (305) is input to an insert data register (506), an insert mask register (507) and an address counter 3 (502) of the insert memory (501). Address counter 3 (502) is set to 0 at the time of initial setting.
And is updated to 1 by this pulse. Therefore, the insert data memory (503) and the insert mask memory (504) output the contents of address 0 instead of the contents of address 0. The insert data register (506) and the insert mask register (507) fetch the data of the insert data memory (503) and the insert mask memory (504) by the same pulse. The data, that is, the data at address 0 is taken in. Therefore, the data whose field corresponding to the least significant bit of the fault indication register in the processor bus (S1) is "1" is set in the insert data register (506). In the insert mask register (507), data corresponding to the least significant bit of the fault indication register in the processor bus (S1) is set to "1", and all other fields are set to "0". Sent to 2).

In the selector (2), the output (512) of the insert mask register (507) is ANDed (603)
To receive. Since the input from the latch (308) of the insert trigger which is the other input of the AND (603) is "1" at this time, the least significant bit of the fault indication register corresponds to the AND (603) of the circuit (602). The output of 603) becomes "1". The output of AND (603) is "1"
Then, the three-state driver with gate (604) passes data, and the output (512) of the insert data memory is sent to the processor bus (S1). This becomes the least significant bit of the fault indication register.
Since the output of AND (603) is "1", the bidirectional three-state driver (606) is shut off.

The processor (7) sets the TS (704) to "
1 ", and the data whose least significant bit is replaced by the selector (2) at the next bus clock T2 (707) is
Take it in as the data of the fault register.

The pulse sent from the comparator 1 (305) causes the address counter (302) to be updated, and the contents of the address 1 are stored in the insert start trigger setting memory (303) and the insert start trigger mask memory (304). It has been read and the second comparison has already begun.

Next, the operation of stopping the insertion will be described. Immediately after the start of detection, the address counter 2 (311)
Is 0, the contents of the address 0 are read from the insert stop trigger setting memory (312) and the insert stop trigger mask memory (313). By setting, at the address 0 of the insert stop trigger setting memory, "A00000000" is stored in the field corresponding to the address line of the processor bus (S1), "1" is stored in the field corresponding to TS, and the field corresponding to R / W is stored in the field corresponding to R / W. "
Since “1” has been written, this data is AND4
(321) is one of the inputs.

The other data of AND4 (321) is the contents of address 0 of the insert stop trigger mask memory. This is because the fields corresponding to the address line, the R / W line, and the TS line of the processor bus (S1) are "1".
And the other fields are "0". So AND4
The output of (321) indicates that the field corresponding to the address line of the processor bus (S1) is "A00000000", R
The field corresponding to the / W line is "1", and the field corresponding to the TS line is "1". This data is directly used as one input of the comparator 2 (310). The other input is the data on the processor bus and the output of the insert stop trigger mask memory (313).
D3 (320) performs an AND operation and inputs the result.

The processor (7) has T1 (706) and T2
TS (704) is set to “1” during (707). Here, “A00000000” is added to the address line of the processor bus,
Data "1" appears on the R / W line and "1" appears on the TS line.

The comparator 2 (310) compares inputs in synchronization with the bus clock. Accordingly, an input match is detected at T2 (707). If they match, comparator 2 (310) outputs a pulse at its output. The latch (30
8) is reset, and “0” is sent to the selector (2). By this signal, the AND (60) of the selector (2) is
The output of 3) becomes "0", the 3-state driver with gate (604) is shut off, the bidirectional 3-state driver (606) passes signals, and communication between the peripheral circuit and the processor (7) is established. Will be resumed.

The pulse sent from the comparator 2 (310) causes the address counter 2 (311) to be updated.
The contents of address 1 have been read from the insert stop trigger setting memory (312) and the insert stop trigger mask memory (313), and the second comparison has already started.

With the above operation, the firmware recognizes that a failure has occurred. The debug support circuit (1) repeats the same operation until the firmware notifies the failure, that is, three times. The operation of the firmware failure handling routine can be confirmed. Also, if you want to check the firmware function that does not notify the failure twice,
It is sufficient to set data for which the third start trigger is never established.

In the above, the operation has been described assuming an example. However, the debug support circuit (1) includes the trigger conditions and the insertion of all the signal lines transmitted and received between the processor (7) and the peripheral circuits except for the bus clock. Since it is the target of data, any data can be passed to the firmware.

Debug support circuit according to the embodiment (1)
Is configured as described above, and has the following effects. Since arbitrary data can be given to the program at an arbitrary timing, even if there is no peripheral device (6), if all the signals transmitted from the peripheral device (6) are set, it is possible to debug the firmware, Program debugging becomes easy.

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately changed within the technical idea of the present invention.

[0096]

Since the present invention is configured as described above, the following effects can be obtained. Based on the basic configuration of transmitting or stopping transmission of data in the insert data memory to the processor bus triggered by a match between data set in the insert trigger circuit and signals transmitted and received between the processor and the peripheral device, at an arbitrary timing. A firmware debug environment capable of providing arbitrary data to firmware is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a debug support circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an interface unit of FIG. 1;

FIG. 3 is a block diagram of the insert trigger circuit of FIG. 1;

FIG. 4 is a block diagram of the memory of FIG. 1;

FIG. 5 is a block diagram of the insert memory of FIG. 1;

FIG. 6 is a block diagram of the selector of FIG. 1;

FIG. 7 is a bus timing chart during a read cycle according to the embodiment of the present invention.

[Explanation of symbols]

 S1 Processor bus 1 Debug support circuit 2 Selector 3 Insert trigger circuit 4 Insert memory unit 5 Interface unit 6 Peripheral device 7 Processor 8 ROM 9 RAM 201 Interface unit 205 Comparator 206 NOT circuit 207 Address match signal 208 Address register 209 Write data register 210 Read data register 211 Differentiator circuit 212, 213, 214 AND circuit 217 Write / read control signal line 218 AND circuit 301 Insert trigger circuit 302 Address counter 1 303 Insert start trigger setting memory 304 Insert start trigger mask memory 305 Comparator 1 306 AND1 307 Reset circuit 308 Latch 309 AND2 310 Comparator 2 311 Address counter 2 312 Insert stop trigger setting memory 313 Insert stop trigger mask memory 314 Reset signal line 315 Output 320 AND3 321 AND4 322, 323, 324 Output 325 Internal bus 326 OR1 402 Comparator 403 Selector 404 Flip-flop 405 AND 406 Memory 407 Gate 408 Address 409 Internal Data bus 410 Write / read control signal line 411 Address 412 Output 413 Upper 5 bits of address 414 Least significant bit of internal data bus 415 NOT 501 Insert memory 502 Address counter 3 503 Insert data memory 504 Insert mask memory 505 Reset circuit 506 Insert data Register 507 Insert mask register 509 Internal bus 51 A reset signal line 511 and 512 output 602 circuit 603 the AND 604 gated three-state driver 605 NOT 606 bidirectional three-state driver 702 processor bus address 703 R / W 704 TS 706 T1 707 T2

Claims (8)

(57) [Claims] 1. A program debug support circuit for firmware, comprising: an interface unit for receiving data required for operation of the debug support circuit from a central processing unit via a processor bus; An insert trigger circuit for monitoring the processor bus, a selector for switching and transmitting set data and a signal from a peripheral device to the processor bus according to an instruction of the insert trigger circuit, and a data received from the interface unit. A program debug support circuit, comprising: an insert memory unit that transmits the data to the selector in response to a data transmission instruction from the insert trigger circuit. 2. The data received by the interface unit from the central processing unit are six types of data from first data to sixth data, and “1” or “0” is set in bit units, First data transmitted to the central processing unit in place of the peripheral device, second data for specifying validity or invalidity of the first data in bit units, and "1" or "0" in bit units. The third data to be set and the signal line to be monitored among the signals of the processor bus are specified, and the fourth data to be compared with the third data are set to “1” or “0” in bit units. 5. The program device according to claim 1, wherein the program data comprises: data to be monitored, and a signal line to be monitored among the signals of the processor bus, and sixth data to be compared with the fifth data. Grayed support circuit. 3. The interface unit, wherein the first data and the second data are set in the insert memory unit using an internal bus, and wherein the third data, the fourth data, and the fifth data are set. 3. The program debug support circuit according to claim 1, wherein the data and the sixth data are set in the insert trigger circuit. 4. A program debugging support method for firmware, wherein an insert trigger circuit monitors a processor bus based on third data and fourth data received from an interface unit, and inserts a third signal to a monitored signal line. When the same data as the data appears, it instructs the insert memory unit to transmit data, and instructs the selector to transmit the data in the insert memory unit to the processor bus. The stored first data and second data are transmitted to the selector according to a data transmission instruction from the insert trigger circuit, and the selector transmits the data of the insert memory unit from the insert trigger circuit to the processor. While receiving the instruction to send to the bus, the first data specified by the second data is The insert trigger circuit monitors the processor bus based on the fifth data and the sixth data received from the interface unit, and outputs the fifth data to a monitored signal line. When the same signal appears, the selector instructs the selector to send data of the peripheral device to the processor bus. The selector instructs the insert trigger circuit to send the signal of the peripheral device to the processor bus. Sending a signal from the peripheral device to the processor bus while receiving the program. 5. The insert memory unit stores the first data and the second data received from the interface unit in the insert memory unit in the order of transmission, and stores the first data and the second data in response to a transmission instruction from the insert trigger circuit. 5. The program debugging support method according to claim 4, wherein the data is transmitted to the selector from the data. 6. The insert trigger circuit, wherein the same number of the third data and the fourth data are set in the insert trigger circuit, and each time the same data as the third data appears on the signal line to be monitored, the insert memory 6. An instruction to send data to the processor bus to the unit and the selector, and restart monitoring under the monitoring condition set by the next third data and fourth data.
The described program debugging support method. 7. The same number of the fifth data and the sixth data are set in the insert trigger circuit, and each time the same data as the fifth data appears on the signal line to be monitored, the data is sent to the selector. 7. An instruction to send data of the peripheral device to the processor bus is issued, and monitoring is resumed under monitoring conditions set by the following fifth data and sixth data.
The program debugging support method according to any one of the above. 8. A storage medium in which a program capable of executing the program debugging support method according to claim 4 is recorded.