JP2969822B2 - Semiconductor device manufacturing management system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing management system in a semiconductor device manufacturing process, and more particularly to a system for realizing high-quality semiconductor device manufacturing.

2. Description of the Related Art Conventionally, in a semiconductor device manufacturing process, information on defects such as dust adhesion, mask scratches, and photoresist pattern defects generated in a diffusion process is collected in wafer units, and non-defective / non-defective products for each wafer. It was discarded after a non-defective judgment was made, and no information was accumulated for each chip in the wafer and no inspection based on this was performed.

[Problems to be Solved by the Invention] In this conventional system, even if information on various defects generated in the diffusion process is obtained, it is not necessarily used effectively in the final inspection process, so that a sufficient defect is not necessarily obtained. There is a case where the determination cannot be made and the defective chip is not removed as a defect, which causes a deterioration in the quality of the semiconductor device after being shipped to the market.

[Means for Solving the Problems] A first gist of the present invention is to provide information relating to a defect generated in a wafer manufacturing process of a semiconductor device for performing a predetermined process on a plurality of regions on a wafer corresponding to a plurality of chips. And save in association with chip position information, to determine whether the chip or non-defective is defective based on the information regarding the defect for the chip determined to be non-defective in the electrical characteristics test for each chip, A second gist of the present invention resides in that dust adhesion information generated in a wafer manufacturing process of semiconductor device manufacturing for performing a predetermined process on a plurality of regions on a wafer corresponding to a plurality of chips is stored in association with chip position information on the wafer. The chip determined to be non-defective in the electrical characteristic test for each chip is determined to be non-defective or defective based on the dust adhesion information. It is to determine whether or not.

In other words, the present invention centrally manages information on defects collected for each process, collects and stores defective chip information, defect content information, and the like existing in a wafer in each inspection process, and finally collects one chip. It is provided with an information network that manages and integrates information on one good product / defective product and that can remove defective chips that were not removed in the conventional inspection process as defects in the inspection process.

EXAMPLES Next, the present invention will be specifically described based on examples.

FIG. 1 is a block diagram showing a manufacturing flow of a semiconductor device according to one embodiment of the present invention. First, a semiconductor wafer with a designed pattern undergoes various manufacturing processes such as oxidation, photoresist, and diffusion, and then a predetermined electrode is formed in an electrode forming process. A defective product is determined. here,
In the management system of this embodiment, a chip size and a chip position in a wafer determined at the time of pattern design are used as initial information in an information network, and information i (i) generated as the manufacturing process proceeds with oxidation, photoresist, and diffusion.
= 1, 2, 3, ...), information on defects such as scratch defects, photoresist defects, dust adhesion, etc. is sequentially registered in the information network along with the chip position and number in the wafer, and as process-specific data for each chip accumulate. Then, integrate the initial information and process-specific information registered in the information network,
In the P / W check process, further non-defective / non-defective judgment of chips that are not recognized as defective in the electrical characteristics check is performed based on the information on defects sent from the information network, and only non-defective products are supplied to the next assembly process It is programmed as follows. Therefore, in the assembly process, only high-quality chips determined to be non-defective by this P / W check are put in,
After the defective chips generated in the assembling process are removed in the sorting process, only high-quality chips are finally shipped.

FIG. 2 is a block diagram showing a manufacturing flow of a semiconductor device according to another embodiment of the present invention. First, a semiconductor wafer with a designed pattern is manufactured by repeating the manufacturing process such as oxidation, photoresist, and diffusion several times, and then checking the electrical characteristics using a technician called a P / W check.
A defective product is determined.

In the management system of this embodiment, a chip size and a chip position in a wafer determined at the time of pattern design are used as initial information, and dust is detected by a dust detection device in each step as the manufacturing process proceeds with oxidation, photoresist, and diffusion. The information of adhesion i (i = 1, 2, 3,...) Is sequentially registered together with the chip position and the number in the wafer, and stored as process-specific data for each chip. Based on the dust-related information, the non-defective / defective products are judged based on the dust-related design criteria, and non-defective / defective chip information on chips that are not recognized as defective in the electrical characteristics check is sent to the prober used for P / W check. . At the time of P / W, the prober checks and integrates the results of the electrical characteristics check with the information obtained from the dust detection device, scratches the chip recognized as defective, and supplies only a good product to the next assembly process. Therefore, in the assembly process, only high-quality chips that have been recognized as good products in the P / W check are put into the assembly process. Only quality chips are shipped.

[Effects of the Invention] As described above, the present invention can improve the final shipping quality, prevent the occurrence of defects in the market of shipped products, and eliminate defective products at a relatively early stage of the manufacturing process. Therefore, there is an effect that unnecessary costs are not generated and semiconductor manufacturing costs can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a manufacturing flow of a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a block diagram showing a manufacturing flow of a semiconductor device according to another embodiment of the present invention.

Claims (2)

(57) [Claims] A semiconductor device for performing a predetermined process on a plurality of regions on a wafer corresponding to a plurality of chips; information relating to a defect occurring in a wafer manufacturing process of the semiconductor device; A semiconductor device manufacturing management system comprising: determining whether a chip is a non-defective product or a non-defective product based on information on the defect with respect to the chip determined to be non-defective in each electrical characteristic test. 2. A method of manufacturing a semiconductor device, comprising: performing a predetermined process on a plurality of regions on a wafer corresponding to a plurality of chips; storing dust adhesion information generated in a wafer manufacturing process in association with chip position information on the wafer; A semiconductor device manufacturing management system for determining whether the chip is a non-defective product or a defective product based on the dust adhesion information for the chip determined to be non-defective in an electrical characteristic test for each chip. .