JP2966439B2 - D / A conversion unit for sequencer - Google Patents

Description

The present invention relates to a D / A conversion unit which is a peripheral device of a sequencer.

[Prior Art] FIG. 10 shows a circuit block of a D / A conversion unit already proposed by the present inventor as Japanese Patent Application No. 1-444448. In this conventional circuit example, an address bus is sent from a CPU unit of a sequencer. 1 is decoded by the decoder 2, the decoded output is output to the latch 3 as the chip selector signal ▲ ▼ of the latch 3, and the 16 bits transmitted from the CPU unit of the sequencer via the data bus 4 Of binary data of sequencer
The data is latched by the latch 3 in response to the signal U from the U unit, and D _{0 to} D ₁₁
12-bit binary data (0 to 10 in decimal decimal)
4095) to the D / A converter 5 to obtain an analog output,
The analog output via the analog switch SW ₀ of the analog output circuit 6 is switched by the range switching signal by the Range switch SW is output through -10V~10V range or 1~5V amplifier A ₁ or A ₂ range. The analog outputs of the -10 V to 10 V range and the 1 to 5 V range are indicated by a and b lines in FIG. 11, respectively. By the way, when the above range is used, the user in both ranges
Digital values of 0 _{(H) to} FFF _(H) are given to the D / A conversion unit.

For example, as shown in FIG. 12, in a circuit for providing data from the CPU unit 7 of the sequencer to the D / A conversion unit 8 to perform D / A conversion and providing the obtained analog output to the motor driver 9 to control the motor 10 Considering the case where the -10 V to 10 V range is used, as shown in FIG.
When stopping the motor, give 7FF _(H) to the D / A conversion unit, 800 _(H) [2048] or more for normal rotation, and 7FE _(H) [2046] for reverse rotation.
Perform the following.

[Problems to be Solved by the Invention] By the way, when the motor 5 is controlled as shown in FIG.
Is not suitable for the operation of the motor 5, and has a problem that it is difficult to handle.

The present invention has been made in view of the above-described problems, and has as its object to convert a digital value input from a CPU unit of a sequencer into a form suitable for an analog output or a movement of a device to be actually controlled. The object of the present invention is to provide a sequencer D / A conversion unit that can easily handle input data.

[Means to Solve the Problem] The present invention provides a D / A for a sequencer which uses data of a predetermined number of bits of binary data of a predetermined bit provided from a CPU unit of a sequencer as data for D / A conversion by a D / A converter. In the A conversion unit, a range switch for performing range switching for switching an analog value obtained by D / A conversion between an analog value of positive and negative signs and an analog value of one sign, and a range for obtaining an analog output of positive and negative At the time of switching, the most significant bit of the data to be D / A converted is set as a bit indicating positive or negative, and this bit is
A circuit for inverting input to the A converter and one of the bits not used as D / A conversion data as a bit indicating positive / negative, and the contents of the bit and the remaining bits not used as D / A conversion data A logic circuit for judging whether or not the content and the content of the most significant bit of the data to be subjected to D / A conversion match and preventing input of the D / A conversion data to the D / A converter when there is a mismatch; In the output mode of the analog value of the sign of, from any other logic circuit that blocks the input to the D / A converter when any one of the bits not used as D / A conversion data has a logical content It consists of

[Operation] According to the sequencer D / A conversion unit of the present invention, when obtaining a positive / negative analog output, data indicating positive / negative is written in a predetermined bit of data provided from the CPU unit of the sequencer. Thus, the data can be handled as data expressed in accordance with the positive and negative operations of the external device to be actually controlled. In the case of invalid data other than valid data written in a form to be subjected to D / A conversion, no data is input to the D / A converter by the logic circuit, so that the invalid data is not D / A converted.

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows a circuit of an embodiment. In this embodiment, a data bus 4 from which 16-bit binary data is transmitted from a CPU unit of a sequencer is connected to a latch 3, and the CPU unit passes through an address bus 1 through the address bus 1. and decode output of the decoder 2 to decode the sent come address sent from the CPU unit ▲ ▼ upon coincidence between the signal to the latch 3 by a signal output from the gate G ₁ and the clock CLK is given 16-bit B ₀ binary data .about.B ₁₅ is adapted to be latched. This 11-bit signal of the latch 3 of the latched data in B ₀ .about.B ₁₀ is directly output to the latch 11, the remaining upper bits B ₁₁ uppermost and the three-state buffer 12 outputs inverting the output non-inverting Is input to the latch 11 via a parallel circuit with the three-state buffer 13. When one of these three-state buffers 12, 13 is on, the other is off, and the gate signal of these three-state buffers 12, 13 is given according to the switching of the range switch SW. . The bit B ₁₁ is input together with bit B ₁₅ exclusive OR gate G _2. Bit B ₁₂ of the remaining 4 bits that are not D / A conversion to an exclusive OR gate G ₃ together with the bit B _15, exclusive OR gate G ₄ together with bits B ₁₃ bits B _15, and the data B
₁₄ are input to the exclusive-OR gate G ₅ together with the data B _15, the output of exclusive-OR gate G ₂ ~G ₅ are input to an OR gate G _6. Also the bit B ₁₂ .about.B ₁₅ is input to the OR gate G _7. The output of the OR gate G ₆ is the inverter IN ₁ of the range switch signal of the range switch SW.
Input to the gate G ₈ with inverted signals by, and the output of the OR gate G ₇ is input to the gate G ₉ with the switching signal of the range selector switch SW, the output of the gate G _8, G ₉ is input to the gate G _10, the output of the gate G ₁₀ is a delay circuit
Input to the gate G ₁₁ together with the output of the gate G ₁ through 14, the output of the gate G ₁₁ of the latch 11 clock CLK
Becomes

 Next, the operation of this embodiment will be described.

First, when the range is 1 to 5 V, the relationship between the analog output and the digital input is shown in FIG. 2, and in this case, input data 0 (000 _(H) ) to 4095
(FFF _(H) ) may be input to the D / A converter 5 so that any one of the bits B _{12 to} B ₁₅ does not become a logical value “1” (“H”). Only if 12 bits
The input data of B _{0 to} B ₁₁ is latched by the latch 11 and taken into the D / A converter 5. That is, the 16-bit binary data on the data bus 4 is obtained by the address from the CPU unit of the sequencer and the ▲ ▼ signal. The data is latched in the latch 3.

Here, since the range changeover switch SW has been switched to the 1-5 V range side (ON), the changeover signal becomes "L" and the three-state buffer 13 is turned on.

On the other hand, since the inner bit B ₁₂ .about.B ₁₅ of the 16-bit data of the B ₀ .about.B ₁₅ latched by the latch 3 is not one be "H" as described above, the output of the gate G ₈ "H", the gate the output of the G ₉ becomes "L", the output of the result of the gate ₁₀ becomes "L". A signal of the gate G ₁₁ delayed by the delay circuit 14 therefore latches the data bits B ₀ .about.B ₁₁ is input to the latch 11 clock ▲ ▼ is when the gate G ₁₀ matches 1
1 and the latched 12-bit binary data is input to the D / A converter 5 to perform D / A conversion.
An analog signal obtained by A conversion is converted to an analog output circuit 6.
Output to an external device or the like via the analog switch SW ₀ and the amplifier A ₁ .

Thus, 0 (000 _(H) ) to 4095 at 1V to 5V range
(FFF _(H) ) becomes valid data as shown in FIG.
Invalid data is 4096 (1000 _(H) ) or more and -1 (FFFF _(H) ) or less. Accordingly, as shown in FIG. 5 16-bit B ₀ ~
Input data used in the inner D / A conversion of the input data consisting of B ₁₅ is set to 12-bit data of bits B ₀ ~B _11, bit B ₁₂
Either .about.B ₁₅ becomes invalid data if the logical value "1" as shown in FIG. 4 were included. In this case, the gate G ₂
Since one of the outputs of G ₅ becomes "H", the output becomes "H" of the OR gate G _6, the gate G ₈ for inputting the gate output
Also becomes “H”. On the other hand, since the gate G ₇ is also output becomes "H", the output of the gate G ₉ to enter the gate output also to "H". Therefore, the output becomes "H" of the gate G ₁₀ of the output is also input to the gates G _8, G _9, the output of gate G ₁₁ to enter the result that gate output is fixed to "H", the delay circuit 14
Cannot be given as the clock of the latch 11. That is, the latch 11 does not latch the data composed of the bits B _{0 to} B ₁₁ and does not perform the D / A conversion by the D / A converter 5.

On the other hand, the case of the range of −10 V to 10 V will be described. In this case, the input data is -2048 (F8
00 _(H) ) to 2048 (7FF _(H) ), so this data is
The input format of converter 5 is 0 (000 _(H) )-4095 (FF
To convert to F _(H)) indicates the positive or negative by reversing the inner bit B ₁₁ of the input data in the positive and negative.

And as the data input from the CPU unit of PLC writes the logic value "0" to bits B ₁₅ as shown in FIG. 7, when a positive, writing a logic value "1" when negative, also bit B ₁₁ .about.B _{In 14} , write the logical value “0” when it is positive,
By writing the logical value "1" at the time of a negative value and sending the data, the negative data is represented by a two's complement number and D / A converted.

When the range of -10V to 10V is selected, the range switch SW is turned off in the circuit of FIG. This turning off turns on the three-state buffer 12, and the bit B11 input from the latch 3 to the latch ₁₁ is inverted. Here, since the input data is bit B ₁₅ .about.B ₁₁ is all logical value when the positive "0" ( "L") , the output of all this case the gate G ₂ ~G ₅ "L", and the results the output of the OR gate G ₆ becomes "L". Thus the inverted signal of the switching signal of "H" of the range selector switch SW, whose output for two inputs both become "L" of the gate G ₈ for inputting the output of the OR gate G ₆ becomes "L". Also, since all inputs of the OR gate G ₇ are “L”,
Its output becomes a "L", the output of the gate G ₉ in which the gate output, and the switching signal of "H" of the range selector switch SW to the input becomes "H". Therefore, the output becomes "L" of the gate G ₁₀ to an output of the gate G _8, G _9, as in the case described above the latch 11 via the gate G ₁₁ by the output of the gate output and the delay circuit 14 Clock ▲ ▼ is applied to latch the bits B _{0 to} B ₁₀ and the inverted data of B ₁₁ .

The latched data is D / A converted by the D / A converter 5, an analog signal obtained by D / A converted analog switches SW _0, it being outputted to an external device through an amplifier A _2.

Since all the bit B ₁₅ .about.B ₁₁ when input data is negative the logic value "1" ( "H") , the gate G ₂ ~G ₅ Again
Output becomes "L", so that the output of the OR gate G ₆ is "L"
Become, the output of the gate G ₈ also becomes "L". Meanwhile gate output G ₇ becomes "H", the output of gate G ₉ becomes "H". Thus the gate G ₁₀ as in the case positive, the gate G _11,
The clock 回路 is applied to the latch 11 by the delay circuit 14 in the same manner as described above, and the bits B _{0 to} B ₁₀ and the inverted data of B ₁₁ are latched. Here, the invalid data in this range is data of 2048 (800 _(H) ) or more or -2049 (F7FF _(H) ) or less as shown in FIG. 8 and shown in FIGS. 9 (a) and 9 (b). Bit B ₁₄ against bit B ₁₅
A If any .about.B ₁₁ do not match the data, since one of the outputs of this gate G ₂ ~G ₅ becomes "H",
The output of the OR gate G ₆ becomes "H", the output of gate G ₈ to enter this gate output also to "H". While the gate G ₉ is range switching signal is for a "H" also its output "H". Therefore, the output becomes "H" of the gate G ₁₀ to an output of the gates G _8, G _9, the result that the output of gate G ₁₁ to enter the gate output is fixed to "H", the output from the delay circuit 14 Cannot be given as the clock CLK of the latch 11. That is, the latch 11 does not latch the data composed of the bits B _{0 to} B ₁₁ and does not perform the D / A conversion by the D / A converter 5.

[Effects of the Invention] The present invention relates to a D / A conversion unit for a sequencer which uses data of a predetermined number of bits of binary data of a predetermined bit provided from a CPU unit of a sequencer as data for D / A conversion by a D / A converter. , A range changeover switch for changing over the analog value obtained by the D / A conversion to an analog value over a positive or negative sign and an analog value of one sign, and a D / A The most significant bit of the data to be A-converted is set as a bit indicating positive / negative, and this bit is set to D /
A circuit for inverting input to the A converter and one of the bits not used as D / A conversion data as a bit indicating positive / negative, and the contents of the bit and the remaining bits not used as D / A conversion data A logic circuit for judging whether or not the content and the content of the most significant bit of the data to be subjected to D / A conversion match and preventing input of the D / A conversion data to the D / A converter when there is a mismatch; In the output mode of the analog value of the sign of, from any other logic circuit that blocks the input to the D / A converter when any one of the bits not used as D / A conversion data has a logical content Therefore, in order to obtain a positive / negative analog output, the positive / negative data is written into a predetermined bit of the data provided from the CPU unit of the sequencer, so that the external device to be actually controlled is Can be handled as data expressed in accordance with the positive and negative movements of the container, which has the effect of facilitating data handling.
In the case of invalid data other than valid data written in the form to be A-converted, the data is not input to the D / A converter by the logic circuit, so there is an effect that invalid data is not D / A converted. Further, there is an effect that it is advantageous in terms of cost and space as compared with a case where the CPU is incorporated in the D / A conversion unit and data processing is performed by arithmetic processing of the CPU.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG.
Illustration of switching of 5V range, FIG. 3 is an explanatory diagram of valid and invalid data of 1 to 5V range, and FIG.
Diagram of invalid data in 5V range, Fig. 5 shows 1-5V
FIG. 6 is a diagram illustrating the switching of the -10 V to 10 V range, FIG. 7 is a diagram illustrating the data configuration of the -10 V to 10 V range, and FIG. 8 is a -10 V to 10 V range of the above. FIG. 9 (a) and FIG. 9 (b) are illustrations of -10
FIG. 10 is a configuration diagram of positive and negative invalid data in the V to 10V range, FIG. 10 is a circuit diagram of a conventional example, FIG. 11 is an explanatory diagram of range switching in the above, and FIG. 3 latches, 5 D / A converter, 11 is a latch, 12 and 13 three-state buffer, G ₁ ~G ₁₁ gates, SW is a Range switch.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/00-1/188

Claims (1)

(57) [Claims] A D / A conversion unit for a sequencer which uses data of a predetermined number of bits of binary data of a predetermined bit provided from a CPU unit of the sequencer as data for D / A conversion by a D / A converter, A range changeover switch that switches the analog value obtained by A conversion to an analog value over a positive or negative sign and an analog value of one sign, and a D / A conversion at the time of range changeover to obtain an analog value over a positive or negative sign. Set the most significant bit of the data to be performed as a bit indicating positive or negative, and set this bit to D / A
A circuit for inverting input to the converter, and one bit of bits not used as D / A conversion data is set to a bit indicating positive or negative, and the contents of the bit, the contents of the remaining bits not used for D / A conversion, and A logic circuit that determines whether or not the data to be subjected to D / A conversion matches the contents of the most significant bit and prevents the data of the D / A conversion from being input to the D / A converter when there is a mismatch; In the analog value output mode, if at least one of the bits not used as D / A conversion data has logical content, D / A
A D / A conversion unit for a sequencer, comprising another logic circuit for blocking input to the converter.