JP2964805B2 - Chip capacitors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip capacitor useful for electronic equipment used in a high frequency band.

[0002]

2. Description of the Related Art Heretofore, a multilayer ceramic capacitor has been used as a chip capacitor for use in a high frequency band for temperature compensation and having a low electric capacity. However, this type has a problem that the electric capacity is high, the electric capacity accuracy is poor, and it is difficult to use. Therefore,
In order to solve this problem, Japanese Patent Application Laid-Open No. 51-30955 proposes a ceramic chip capacitor.
This is a configuration in which a dielectric material compacted and molded into a block is fired, cut into a plate shape, and then an electrode is formed.

[0003]

However, the above-mentioned conventional construction has a problem in that the ceramic processing steps and firing steps such as leveling of the cut surface of the dielectric are complicated, costly and not suitable for mass production. I was In addition, there has been a problem that the reduction in electric capacity has been improved, but it is difficult to use it in electronic equipment used in a high frequency band due to poor electric capacity accuracy.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. In order to meet the diversification of required characteristics with a small change in dielectric constant with temperature, high productivity and low electric capacity are required. An object is to provide a highly accurate chip capacitor.

[0005]

Means for Solving the Problems In order to achieve this object, the invention according to claim 1 provides a rod-shaped dielectric element with a plurality of grooves, the dielectric element and the plurality of grooves. A metal electrode layer was provided on the surface of the substrate, a notched gap was provided in the metal electrode layer, and a gap was provided between the plurality of grooves . The invention according to claim 2, in claim 1, formic
The gap width of the gap is 100 to 1000 μm
You. Further, in the invention according to claim 3, in claim 1, a protective film is provided on the gap and the groove .

Here, the dielectric element may be a dielectric ceramic composition for temperature compensation, a ceramic composition such as alumina, forsterite, mullite or silica; a synthetic resin such as a polyimide resin or a fluororesin; Organic polymers and the like are preferably used.

As the metal electrode layer, copper, silver, gold, zinc or nickel is preferably used. When a metal layer such as solder or tin is further formed on the metal electrode layer, if a metal cap plated with solder is used, the metal cap is press-fitted and then heat-treated, so that the dielectric element and the metal cap are soldered. Since it is firmly joined via the layer, the quality and durability can be improved.

As the metal cap, a metal having good conductivity is used, and it is particularly preferable that the inside is plated with solder or the like.

It is preferable from the viewpoint of productivity to press the metal cap on the end of the dielectric element after forming the metal electrode layer. If the metal cap is not required due to dimensional problems or the like, the metal cap may not be used. The gap that regulates the electric capacity is formed by chemically or mechanically removing a part of the metal electrode layer.The chemical method is etching, and the mechanical method is a high-speed rotating diamond disk. This is performed by a layer removing method or the like.

The width of the gap is 100-1000 μm
m, more preferably 200 to 500 μm, from the viewpoints of structure and reliability.

If a protective film covering at least the gap portion is formed after the gap is formed, it is possible to prevent foreign substances and moisture from adhering to the gap portion, thereby improving the durability and the like.

As the protective film, silicon-based and fluorine-based ones are preferable, and an epoxy-based or polyimide-based one may be used as long as the electric capacity and moisture resistance of the chip capacitor are not affected. These are formed by a transfer method or the like.

Further, even if the protective coating is not applied, it is not necessary to apply the chip capacitor if there is no problem in reliability.

[0014]

With this configuration, an electric capacitance is formed between the gap in the outer peripheral portion and the opposing electrode between the groove and the side surface of the groove, so that a high-accuracy and low electric capacitance can be obtained. In addition, high-density mounting can be performed because miniaturization is easy. The capacitance value can be determined by adjusting the distance between the grooves and the depth of the groove, and by adjusting the capacitance between the opposing electrodes and adjusting the depth and width of the gap. Can be obtained. Further, since the structure and the manufacturing process are very similar to the metal film fixed resistor and the manufacturing equipment can use the same equipment, high mass productivity can be obtained as compared with the conventional chip capacitor.

[0015]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a main part of a chip capacitor according to an embodiment of the present invention. 1 is a rod-shaped dielectric element,
Reference numeral 2 denotes two grooves formed circumferentially in the longitudinal direction of the dielectric element 1, reference numeral 3 denotes a metal electrode layer, reference numeral 4 denotes a metal cap, and reference numeral 5 denotes a cutout of the metal electrode layer 3 to regulate electric capacity and the like. The notch-shaped gap 6 formed is a protective film.

A method of manufacturing the chip capacitor configured as described above will be described below.

A. Manufacturing process of dielectric element 1 MgO which is a dielectric ceramic composition for temperature compensation as a porcelain system
-CaO-SrO-TiO ₂ ceramic, alumina,
Silica, mullite, and forsterite were formed using polyimide resin as an organic polymer. The size was 1.0 φ × 1.8 mm.

B. Step of Forming Grooves 2 Two grooves 2 are placed at a symmetrical position substantially at the center in the longitudinal direction of the rod-shaped dielectric element obtained in the step a), with a gap of 0.5 m between the grooves.
m, width 0.1 mm, depth 0.2 mm, and formed circumferentially.

C. Step of Forming Metal Electrode Layer A metal electrode layer 3 having a thickness of 3 to 10 μm is formed on the surface of the dielectric element 1 obtained in the step b by plating using copper, silver, gold or nickel as a metal. did. Note that a solder layer (90% Sn-10% Pb) was formed on the outermost layer of some of the dielectric elements 1 to improve solderability. Metal electrode layer 3
(Table 1) shows the configuration of the plating layer that forms.

[0021]

[Table 1]

D. Step of Capping Metal Cap 4 Metal caps 4 were press-fitted to both ends of the dielectric element 1 and capped.

E. Step of Forming Electric Capacitance Gap 5 The metal electrode layer 3 is trimmed using a high-speed rotating diamond disk while measuring the electric capacitance of the dielectric element 1 obtained in the step d.

F. Protective film coating process A silicon paint is used as the paint, and the thickness of the film is about 10
The chip capacitor of this example was manufactured by setting the thickness to 0 μm.

Next, the capacitance accuracy, minimum capacitance and productivity of the chip capacitor of this embodiment were measured.
As comparative examples, conventional multilayer ceramic capacitors and those described in JP-A-51-30955 were manufactured and used. The results are shown in (Table 2). Here, the capacitance used for measuring the capacitance accuracy was 0.5 pF. The productivity was calculated from man-hour calculations.

[0026]

[Table 2]

As is evident from Table 2, it is understood that the present embodiment is excellent in the electric capacity accuracy, the minimum electric capacity value and the productivity. In particular, in the case of polyimide resin,
With the capacitance accuracy shown in (Table 2), the minimum capacitance value was possible up to 0.01 pF.

Next, an experiment for confirming a reliability test was performed on the electrodes. The results are shown in (Table 3).

[0029]

[Table 3]

The conditions of the humidity resistance load life test are as follows:
The test was performed with 95% Rh and a DC bias of 5 V to 100 h.

As is clear from Table 3, when the electrode is made of copper, nickel or zinc, the rate of change in electric capacity is very small. In the case of silver, the rate of change is slightly higher than that of the other electrodes, but when the dielectric loss is measured, the dielectric loss of the other electrode is 8 to 15 × 10 ^-4 ,
Silver was found to be very excellent at 4 × 10 ⁻⁴ . Therefore, the selection of the metal electrode layer 3 must be properly used depending on the application. Further, a dielectric element 1 having a solder or tin layer formed on the outermost layer and a metal cap
It was also found that when the metal cap 4 was press-fitted and subjected to a heat treatment, the dielectric element 1 and the metal cap 4 were firmly joined via the solder layer.

It has been found that the same effect can be obtained by using other materials having the above structure as the material of the dielectric element 1. Further, in the embodiment, a plating method is used as a method for forming the metal electrode layer 3, but a vapor deposition method,
The same effect was obtained by using a sputtering method or the like.

[0033]

As described above, according to the present invention, the change in the dielectric constant with respect to temperature is small, the electric capacity is extremely low, the precision can be met, and various characteristics can be diversified. This makes it possible to realize an excellent chip capacitor suitable for characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a chip capacitor according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dielectric element 2 Groove part 3 Metal electrode layer 4 Metal cap 5 Gap 6 Protective film

Continuation of front page (72) Inventor Hiromitsu Taki 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-4-306818 (JP, A) JP-A-5-275274 ( JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01G 4/12

Claims (3)

(57) [Claims] [1 claim: a rod-shaped dielectric element, and a plurality of grooves that are made form <br/> in the dielectric element, the dielectric element and the metal electrode layer formed on the plurality of grooves of the surface and , and a notch-shaped gap formed on the metal electrode layer, wherein the double
A chip capacitor , wherein said gap is provided between a number of grooves . 2. The gap width of the gap is 100 to 1000.
2. The chip capacitor according to claim 1 , wherein the thickness of the chip capacitor is μm . 3. The chip capacitor according to claim 1, wherein a protective film is provided on the gap and the groove .