JP2963278B2 - Network element - Google Patents

Network element

Info

Publication number
JP2963278B2
JP2963278B2 JP4189243A JP18924392A JP2963278B2 JP 2963278 B2 JP2963278 B2 JP 2963278B2 JP 4189243 A JP4189243 A JP 4189243A JP 18924392 A JP18924392 A JP 18924392A JP 2963278 B2 JP2963278 B2 JP 2963278B2
Authority
JP
Japan
Prior art keywords
electrode
electrodes
chip
network resistor
network element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4189243A
Other languages
Japanese (ja)
Other versions
JPH0636907A (en
Inventor
雅之 根来
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP4189243A priority Critical patent/JP2963278B2/en
Publication of JPH0636907A publication Critical patent/JPH0636907A/en
Application granted granted Critical
Publication of JP2963278B2 publication Critical patent/JP2963278B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other

Landscapes

  • Details Of Resistors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、チップ型のネットワ
ーク抵抗器等のネットワーク素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network element such as a chip-type network resistor.

【0002】[0002]

【従来の技術】ネットワーク素子は、一個の基板に複数
個の回路素子が形成されるので、複数の電極を有する。
この種のネットワーク素子は、電極間をセパレートする
ために、チップ基板の側面に凹部を設け、従来は、この
凹部と凹部の間の凸部に各電極を形成するか、あるいは
凹部に電極を形成している。図6には、チップ基板61
の側面に設けられる凹部62に、電極63を形成した例
を示している。ここでは、電極63の上面部のみが示さ
れているが、対応してチップ基板61の下面に電極63
の下面部が形成され、さらにチップ基板61の側面の凹
部壁にも電極62の側面部が形成され、電極63は上面
部、下面部及び側面部で一体的に構成されている。また
図示していないが、各電極63は、チップ基板61内で
適宜、回路素子に接続されている。
2. Description of the Related Art A network element has a plurality of electrodes because a plurality of circuit elements are formed on one substrate.
In this type of network element, a concave portion is provided on the side surface of the chip substrate in order to separate between the electrodes, and conventionally, each electrode is formed in a convex portion between the concave portions, or an electrode is formed in the concave portion. doing. FIG. 6 shows a chip substrate 61.
An example is shown in which an electrode 63 is formed in a concave portion 62 provided on the side surface of FIG. Although only the upper surface of the electrode 63 is shown here, the electrode 63 is
Are formed on the concave wall of the side surface of the chip substrate 61, and the electrode 63 is integrally formed of the upper surface, the lower surface and the side surface. Although not shown, each electrode 63 is appropriately connected to a circuit element in the chip substrate 61.

【0003】[0003]

【発明が解決しようとする課題】上記した凹部に電極を
形成するネットワーク素子では、小型のものほど、隣接
電極間の距離が近くなり、フロー半田付時に、図7の
(a)に示すように、電極63の上面部63aでフラッ
クス残渣64によるリーク、また図7の(b)に示すよ
うに、過剰半田65により、電極63の上面部63aの
隣接同士が短絡するおそれがある。またリフロー時の半
田付時に、図7の(c)に示すように、電極63の下面
部63bが、回路基板67のランド電極68に半田付け
される際に、過剰半田66により、やはり隣接同士短絡
するおそれがある。
In the above-described network element in which an electrode is formed in a concave portion, the smaller the element is, the shorter the distance between adjacent electrodes becomes. As shown in FIG. 7A and 7B, there is a possibility that the adjacent upper surface portions 63a of the electrodes 63 may be short-circuited due to the leakage due to the flux residue 64 on the upper surface portions 63a of the electrodes 63, and as shown in FIG. 7C, when the lower surface portion 63b of the electrode 63 is soldered to the land electrode 68 of the circuit board 67 due to excessive solder 66, as shown in FIG. There is a risk of short circuit.

【0004】この発明は上記問題点に着目してなされた
ものであって、、隣接電極間で短絡の生じにくいネット
ワーク素子を提供することを目的としている。
The present invention has been made in view of the above problems, and has as its object to provide a network element in which a short circuit does not easily occur between adjacent electrodes.

【0005】[0005]

【課題を解決するための手段及び作用】この発明のネッ
トワーク素子は、チップ基板の側面から、上面及びもし
くは下面に亘り形成される電極が複数個設けられ、かつ
各電極がチップ基板の凹部に形成されたものにおいて、
チップ基板の上面及びもしくは下面の隣接する電極間に
切欠き凹部を形成している。
The network element according to the present invention is provided with a plurality of electrodes formed from the side surface of the chip substrate to the upper surface and / or the lower surface, and each electrode is formed in a concave portion of the chip substrate. In what was done,
A notch recess is formed between adjacent electrodes on the upper surface and / or lower surface of the chip substrate.

【0006】このネットワーク素子においては、上面の
電極近傍にフラックス残渣が生じ、あるいは過剰半田で
も、それらは、電極間の切欠き凹部に入り、その段差に
より、短絡を免れる。また、下面の電極間に切欠き凹部
を設けている場合には、過剰半田のもり上がりが、この
部分に逃げ、やはり、電極間短絡が生じにくくなる。
In this network element, even if flux residue is generated near the electrode on the upper surface, or even if the solder is excessive, they enter into the notch recess between the electrodes, and a short circuit is avoided by the step. In addition, when a notch recess is provided between the electrodes on the lower surface, excess solder spillage escapes to this portion, which also makes it difficult to cause a short circuit between the electrodes.

【0007】[0007]

【実施例】以下、実施例により、この発明をさらに詳細
に説明する。図1は、この発明の一実施例を示すチップ
型ネットワーク抵抗器の斜視図である。このチップ型ネ
ットワーク抵抗器10は、偏平なセラミック基板1の長
辺側面2に4個ずつ8個の平面視半円孤状の凹部3を設
けている。凹部3には、それぞれ電極4が形成されてい
る。この電極4は、それぞれセラミック基板1の上面に
形成される上面電極部4aと下面に形成される下面電極
部4bと凹部3の側面に形成される側面電極部4cとか
ら一体的に構成されている。なお、各電極間には、セラ
ミック基板1上で、抵抗膜が適宜形成されているが、本
発明の要部でないので、ここでは図示を省略している。
The present invention will be described in more detail with reference to the following examples. FIG. 1 is a perspective view of a chip type network resistor showing one embodiment of the present invention. This chip type network resistor 10 has eight concave semi-circular recesses 3 in plan view on the long side surface 2 of the flat ceramic substrate 1. An electrode 4 is formed in each of the recesses 3. Each of the electrodes 4 is integrally formed of an upper electrode portion 4a formed on the upper surface of the ceramic substrate 1, a lower electrode portion 4b formed on the lower surface, and a side electrode portion 4c formed on the side surface of the concave portion 3. I have. Although a resistive film is appropriately formed between the electrodes on the ceramic substrate 1, it is not shown here because it is not a main part of the present invention.

【0008】この実施例ネットワーク抵抗器10の最も
特徴とするところは、隣接する各電極4間のセラミック
基板1の上面端縁から側面に至る、切欠き凹部5を設
け、またさらに隣接する各電極4間のセラミック基板1
の下面端縁から側面に至る切欠き凹部6を設けたことで
ある。このネットワーク抵抗器10に対し、フロー半田
を行う場合に、上面電極部4aの近傍にフラックス残渣
が生じても、図4の(a)に示すように、切欠き凹部5
の底にフラックス残渣7がたまるが、切欠き凹部5と上
面電極4aとの段差のため、隣接する上面電極部4a間
は、フラックス残渣7によって導通する度合が軽減す
る。また同じく、フロー半田付け時に、上面電極部4a
にて過剰半田が生じても、図4の(b)に示すように、
切欠き凹部5の側壁部に過剰半田8が流れ込むが、切欠
き凹部5がない場合に比し、隣接電極間の距離が長くな
り、隣接上面電極部4a間の過剰半田8によって、短絡
が生じることはない。
The most characteristic feature of the network resistor 10 is that a notch 5 is provided between the adjacent electrodes 4 and extends from the top edge to the side face of the ceramic substrate 1. Ceramic substrate 1 between 4
Is provided with a notched concave portion 6 extending from the lower surface edge to the side surface. When flow soldering is performed on the network resistor 10, even if a flux residue is generated in the vicinity of the upper surface electrode portion 4 a, as shown in FIG.
Flux residue 7 accumulates at the bottom of the substrate, but due to the step between the notch recess 5 and the upper surface electrode 4a, the degree of conduction between the adjacent upper surface electrode portions 4a due to the flux residue 7 is reduced. Similarly, at the time of flow soldering, the upper surface electrode portion 4a
Even if excess solder occurs, as shown in FIG.
The excess solder 8 flows into the side wall of the notch 5, but the distance between adjacent electrodes is longer than when there is no notch 5, and the excess solder 8 between the adjacent upper electrode 4 a causes a short circuit. Never.

【0009】また、このネットワーク抵抗器10におい
て、リフロー半田付け時に下面電極部と回路基板のラン
ド電極との間に過剰半田が生じても、図5に示すよう
に、ネットワーク抵抗器10の、下面電極部4bと、回
路基板11のランド電極12との間の半田付け部13
で、多少の過剰半田があっても、切欠き凹部6に、半田
の盛り上がった部分が逃げるので、隣接する下面電極部
4bが、過剰半田のため短絡することはない。
In this network resistor 10, even if excessive solder occurs between the lower electrode portion and the land electrode of the circuit board during reflow soldering, as shown in FIG. Soldering part 13 between electrode part 4b and land electrode 12 of circuit board 11
Thus, even if there is some excess solder, the raised portion of the solder escapes into the notch recess 6, so that the adjacent lower surface electrode portion 4b does not short-circuit due to excessive solder.

【0010】図2は、この発明の他の実施例チップ型ネ
ットワーク抵抗器を示す斜視図である。この実施例ネッ
トワーク抵抗器20の特徴は、図1のネットワーク抵抗
器がセラミック基板1の上面と下面の両方に、切欠き凹
部5、6を設けているに対し、上面にのみ、つまり、隣
接する各電極4間のセラミック基板1の上面端縁から側
面に至る切欠き凹部5を設けたことである。この切欠き
凹部5を設けたことにより、図4の(a)(b)に示す
ように、フロー半田時のフラックス残渣による両隣接電
極間のリークや、過剰半田による両隣接電極間の短絡の
発生が軽減される。
FIG. 2 is a perspective view showing a chip type network resistor according to another embodiment of the present invention. The feature of the network resistor 20 of this embodiment is that the network resistor of FIG. 1 has cutout recesses 5 and 6 on both the upper surface and the lower surface of the ceramic substrate 1, whereas the network resistor of FIG. That is, a notch concave portion 5 extending from the upper edge to the side surface of the ceramic substrate 1 between the electrodes 4 is provided. As shown in FIGS. 4 (a) and 4 (b), the provision of the notch recesses 5 causes leakage between the adjacent electrodes due to flux residue during flow soldering and short-circuit between the adjacent electrodes due to excessive soldering. Occurrence is reduced.

【0011】図3は、この発明のさらに他の実施例チッ
プ型ネットワーク抵抗器を示す斜視図である。この実施
例ネットワーク抵抗器30の特徴は、図1のネットワー
ク抵抗器がセラミック基板1の上面と下面の両方に、切
欠き凹部5、6を設けているに対し、下面にのみ、つま
り隣接する各電極4間のセラミック基板1の下面端縁か
ら側面に至る切欠き凹部6を設けたことである。この切
欠き凹部6を設けたことにより、図5に示すように、リ
フロー半田付時の過剰半田分が切欠き凹部6に逃がされ
るので、過剰半田による隣接電極間の短絡を防止でき
る。
FIG. 3 is a perspective view showing a chip type network resistor according to still another embodiment of the present invention. The feature of the network resistor 30 of this embodiment is that the network resistor of FIG. 1 has cutout recesses 5 and 6 on both the upper surface and the lower surface of the ceramic substrate 1, whereas only the lower surface, that is, That is, a notched concave portion 6 extending from the lower edge to the side surface of the ceramic substrate 1 between the electrodes 4 is provided. By providing the notch recess 6, as shown in FIG. 5, excess solder at the time of reflow soldering is released to the notch recess 6, so that a short circuit between adjacent electrodes due to excess solder can be prevented.

【0012】なお、上記実施例ネットワーク抵抗器を例
に上げたが、この発明はこれに限ることなく、他のネッ
トワーク素子にも適用できる。
Although the network resistor in the above embodiment has been described as an example, the present invention is not limited to this, and can be applied to other network elements.

【0013】[0013]

【発明の効果】この発明によれば、チップ基板の上面及
びもしくは下面の隣接する電極間に切欠き凹部を設けた
ので、フロー半田時の上面電極部のフラックス残渣によ
る両極間のリーク、過剰半田による短絡、リフロー半田
付時の下面電極間の過剰半田による短絡が生じるのを軽
減できる。
According to the present invention, the notch recess is provided between the adjacent electrodes on the upper surface and / or the lower surface of the chip substrate, so that leakage between the two electrodes due to flux residue of the upper electrode portion during flow soldering and excessive soldering And the occurrence of short circuit due to excessive solder between lower electrodes during reflow soldering can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施例を示すチップ型ネットワー
ク抵抗器の斜視図である。
FIG. 1 is a perspective view of a chip type network resistor showing one embodiment of the present invention.

【図2】この発明の他の実施例を示すチップ型ネットワ
ーク抵抗器の斜視図である。
FIG. 2 is a perspective view of a chip type network resistor showing another embodiment of the present invention.

【図3】この発明のさらに他の実施例を示すチップ型ネ
ットワーク抵抗器の斜視図である。
FIG. 3 is a perspective view of a chip-type network resistor showing still another embodiment of the present invention.

【図4】図1、図2に示すチップ型ネットワーク抵抗器
のフロー半田付時のフラックス残渣及び過剰半田の影響
を説明するための部分断面図である。
FIG. 4 is a partial cross-sectional view for explaining the influence of a flux residue and excess solder during flow soldering of the chip-type network resistor shown in FIGS. 1 and 2;

【図5】図1、図3に示すチップ型ネットワーク抵抗器
のリフロー半田付時の過剰半田の影響を説明するための
部分断面図である。
FIG. 5 is a partial cross-sectional view for explaining the influence of excessive soldering during reflow soldering of the chip type network resistor shown in FIGS. 1 and 3;

【図6】従来のチップ型ネットワーク抵抗器を示す平面
図である。
FIG. 6 is a plan view showing a conventional chip-type network resistor.

【図7】同従来のチップ型ネットワーク抵抗器のフロー
半田付時、リフロー半田付時のフラックス残渣、過剰半
田の影響を説明するための部分断面図である。
FIG. 7 is a partial cross-sectional view for explaining the influence of a flux residue and excess solder during flow soldering and reflow soldering of the conventional chip-type network resistor.

【符号の説明】[Explanation of symbols]

1 セラミック基板 4 電極 5、6 切欠き凹部 DESCRIPTION OF SYMBOLS 1 Ceramic substrate 4 Electrode 5, 6 Notch recess

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】チップ基板の側面から、上面及びもしくは
下面に亘り形成される電極が複数個設けられ、かつ各電
極がチップ基板の凹部に形成されたネットワーク素子に
おいて、 チップ基板の上面及びもしくは下面の隣接する電極間に
切欠き凹部を形成したことを特徴とするネットワーク素
子。
1. A network element in which a plurality of electrodes are provided extending from the side surface of a chip substrate to the upper surface and / or lower surface, and each electrode is formed in a concave portion of the chip substrate. Wherein a notch recess is formed between adjacent electrodes.
JP4189243A 1992-07-16 1992-07-16 Network element Expired - Fee Related JP2963278B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4189243A JP2963278B2 (en) 1992-07-16 1992-07-16 Network element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4189243A JP2963278B2 (en) 1992-07-16 1992-07-16 Network element

Publications (2)

Publication Number Publication Date
JPH0636907A JPH0636907A (en) 1994-02-10
JP2963278B2 true JP2963278B2 (en) 1999-10-18

Family

ID=16238020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4189243A Expired - Fee Related JP2963278B2 (en) 1992-07-16 1992-07-16 Network element

Country Status (1)

Country Link
JP (1) JP2963278B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929746A (en) * 1995-10-13 1999-07-27 International Resistive Company, Inc. Surface mounted thin film voltage divider

Also Published As

Publication number Publication date
JPH0636907A (en) 1994-02-10

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