JP2954785B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in modulation characteristics of a phase locked loop. In particular, the present invention relates to control means for modulating a signal in a signal format in which an analog signal is transmitted after a digital signal.

[0002]

2. Description of the Related Art FIG. 2 shows a circuit diagram of a conventional example of a phase locked loop circuit. In this phase locked loop circuit, the output of a reference oscillator 1 is input to a frequency divider 2, and the output of the frequency divider 2 is applied as a reference input of a phase comparator 3. The phase difference output of the phase comparator 3 is input to the charge pump 11, converted from a digital signal to an analog signal, and input to the voltage controlled oscillator 5 via the low-pass filter 7. The output of the voltage controlled oscillator 5 is used as the output 6 and is input to the frequency divider 4 at the same time. The output of the frequency divider 4 is input to the comparison input of the phase comparator 3.

The charge pump 4 has a resistor Rs between the base, the phase comparator 3 and the ground. PNP
A switch 9 is inserted between both ends of one resistor R2 of two resistors R1 and R2 connected to respective emitters, and the switch 9 is controlled by a phase lock signal 10. Have been. The signal from the modulator 11 is input to the reference oscillator 1 and the voltage controlled oscillator 5 and is modulated.

In FIG. 2, except for a switch 9, a commonly used phase locked loop circuit outputs a frequency determined by the frequency division ratio of the frequency divider 2 and the frequency divider 4. Here, if the drive current of the charge pump is changed by turning on and off the switch 9, the response of the system can be changed.

If the switch 9 is driven by the phase lock signal 10, the phase-locked loop circuit has a small cut-off frequency (hereinafter referred to as Wn) and a narrow noise band at the time of synchronization, and has a large Wn and a high response speed at the time of synchronization pull-in. Can be configured. Normally, modulation is performed by inputting a signal when the phase synchronization circuit is synchronized and Wn is reduced.

[0006]

As described above, in the above-mentioned prior art, modulation is performed when the start-up and synchronization are performed by switching the phase-locked loop (Wn) with a switch. There was a disadvantage that it was long. SUMMARY OF THE INVENTION It is an object of the present invention to solve these disadvantages and to provide a phase locked loop circuit having a fast modulation rise. In particular, in a case where a modulation signal modulates a signal of a signal format in which an analog signal is transmitted following a digital signal, it is an object of the present invention to realize a phase-locked loop circuit whose modulation rises quickly.

[0007]

According to the present invention, in order to achieve the above object, when the modulation signal is an analog signal, the S / N
However, in the case of a digital signal, this problem is alleviated, so when modulating a signal in the form of a signal in which an analog signal is sent after a digital signal, the cutoff frequency is switched to a higher frequency and synchronization is established. At the time when the signal is obtained, the digital signal is modulated, the cutoff frequency is switched to a lower frequency, and when the synchronization is obtained, control is performed so that the analog signal is modulated. Is realized.

[0008]

As a result, when the modulation signal is digital, it is operated by a phase synchronization circuit having a short pull-in time, and when the modulation signal includes analog and digital signals, the phase synchronization circuit has a small Wn. A phase locked loop can be configured.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 2 is a circuit block diagram, and FIG. 3 is a timing chart of signals. The components 11 to 9 and 11 are the same as those of the conventional phase locked loop circuit shown in FIG. In the present invention, the control circuit 12 which is operated by the press switch ON signal 13 and controls the changeover switch 9 and the switches 14 and 15 for switching the modulation input to the modulator 11 is provided. In this example, a wireless device of a signal format in which a modulation input initially flows in the form of a digital signal in which the other party's number or the like continuously flows and an analog signal flows. First, when the press signal 13 is input, the control circuit 12 operates the switch 9 to form a phase-locked circuit with a fast pull-in, and after a predetermined time (FIG. controlled or fast phase pull-in mode - de end (Fig. 3t ₁₎ controls to open the switch 9. Further, the cutoff frequency Wn
When a predetermined time elapses after the selection of the mode in which is smaller (t _{2 in} FIG. 3), the switch 14 is switched so that the analog modulation input is input to the modulator 11. When modulating both the digital signal and the analog signal to the phase locked loop, it is assumed that the rise is completed. There is no problem if the digital signal is input to the modulator at a stage where there is some noise. As described above, the modulation starts from time t _{2 in the related} art, whereas the time t in the present invention. , And a phase-locked loop with fast modulation rise can be constructed.

[0010]

According to the present invention, it is possible to realize a phase locked loop circuit having a fast modulation rise time at the time of frequency switching, and the effect is remarkable. Further, since the means of the present invention is extremely simple, not only the circuit scale can be reduced, but also the economic efficiency is excellent, and its application range is wide.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional phase locked loop circuit.

FIG. 3 is a characteristic diagram showing a rising edge of the modulation of the phase locked loop.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference oscillator 2 Divider 3 Phase comparator 4 Divider 5 Voltage controlled oscillator 6 Output 7 Low-pass filter 8 Charge pump 9 Changeover switch 10 Phase lock signal 11 Modulator 12, Control circuit 14, 15 switch

Claims (1)

(57) [Claims] A charge pump for dividing the output of a voltage controlled oscillation circuit by a frequency divider controlled by a frequency division ratio designating signal, comparing a phase with a reference frequency, and converting a digital signal of the comparison result into an analog signal. In a phase locked loop circuit that performs synchronous control of a voltage controlled oscillator via a loop filter and modulates the output of the voltage controlled oscillator to a reference frequency or a voltage controlled oscillator, the cutoff frequency of the loop filter is increased at the rise of the press signal, and after a predetermined time elapses. When the cutoff frequency of the loop filter is changed so as to be lowered and a signal of a signal format in which an analog signal is transmitted following a digital signal is modulated, the cutoff frequency is switched to a higher cutoff frequency and the digital When the signal is modulated and the cutoff frequency is switched to a lower frequency, and the synchronization is established, the analog signal is modulated. A phase-locked loop, comprising means for controlling the phase-locked loop.