JPH066138A - Fm modulation circuit - Google Patents

Abstract

PURPOSE:To obtain the FM modulation circuit reducing a distortion factor in a demodulation characteristic without increasing a current of a compensation circuit. CONSTITUTION:An output signal of a frequency divider 15 in a PLL loop of a PLL circuit 10 and a signal of a reference oscillator 17 are compared by a phase comparator 161 comprising a counter 161a and a D/A converter 161b, a compared output and an input signal are added and the sum is used for a frequency control signal of a VCO 13. The output of the VCO 13 is fed to the frequency divider 15 and extracted at an output 14 as a modulation output. The counter 16a stops its count by a control signal from a control terminal 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM modulation circuit which can improve the distortion rate of demodulation characteristics by using a PLL circuit.

[0002]

2. Description of the Related Art FIG. 4 shows an FM using a conventional PLL circuit.
It shows a modulation circuit. In FIG. 4, the input signal supplied to the input 11 of the PLL circuit 10 is supplied to one input of the adder 12. The output of the adder 12 is supplied to a voltage controlled oscillator (VCO) 13 as a control signal,
The oscillation frequency of 13 is determined. The oscillation signal of the VCO 13 is led to the output 14 as an FM modulated wave output and supplied to the frequency divider 15. The frequency divider 15 frequency-divides the FM modulated wave output, and the frequency-divided output of the frequency divider 15 is supplied to one comparison input of the counter 16a of the phase comparator 16 including the counter 16a and the D / A converter 16b. Supply. Counter 1
The oscillation signal from the reference oscillator 17 is supplied to the other comparison input of 6a, the phase comparator 16 compares the phase of the signal of the frequency divider 15 with the phase of the signal of the reference oscillator 17, and the amplifier 18
Supply to. The comparison output obtained via the amplifier 18 is
The signal is supplied to the other side of the adder 12 and is added here to the input signal supplied to the above-mentioned input 11 to form a control signal for the VCO 13.

In the PLL circuit having the above configuration, when the modulated signal is supplied to the input 11, the output signal of the phase comparator 16 is added by the adder 12 to control the VCO 13.
An FM-modulated stable carrier can be obtained at the output 14 from which the FM-modulated signal is output.

Generally, the PLL circuit 10 having the above-described structure has a wide lock range, a low loop gain can be set, and a PLL circuit which can be integrated into an IC can be realized.

To set the loop gain low, it is necessary to increase the counting capability of the counter 16a and increase the variable width of the phase that the PLL circuit 10 follows. When the modulation signal has a very low frequency like a voice signal, the PLL circuit 10 must not respond to the lower limit of 20 (Hz) of the voice frequency, so that the counting ability must be particularly enhanced. When the number of bits of the counter 16a increases, the number of bits of the D / A converter 16b connected to the subsequent stage of the counter 16a also increases, and it becomes difficult to realize linear characteristics. If the D / A converter 16b has a non-linear component and a circuit having a non-linear element is used for modulation, the post-demodulation distortion rate deteriorates.

The non-linear component may exist not only in the D / A converter 16b, but also in the fluctuation of the reference voltage of the D / A converter 16b which occurs at the time of counting, or in the loop, for example. There are many factors that cause non-linear characteristics such as the non-linearity of the amplifier 18. If all of the above-mentioned non-linear components are reduced and the characteristics are attempted to be satisfied by the IC, not only the size of the compensation circuit increases but also the current increases.
There is a possibility that the merit of conversion to C will decrease.

As described above, when the PLL loop is operating with the non-linear component present in the PLL loop, the non-linear component is superposed on the input signal although the frequency stability can be maintained. There was a new problem that the demodulation distortion ratio deteriorates and the circuit scale increases if a compensation circuit is inserted as a countermeasure.

[0008]

When the above-mentioned conventional device is integrated into an IC, the compensation circuit and the current may be increased as a means for reducing the non-linear component, and the merit of the IC may be reduced.

The present invention provides an FM modulation circuit which reduces the distortion factor of the demodulation characteristic without increasing the compensation circuit and the current.

[0010]

The FM modulation circuit of the present invention has a function of stopping the PLL circuit for a unit time instead of always operating it. When the PLL circuit is in the stopped state, the loop is added. Make sure that the non-linear component inside does not affect the modulation characteristics.

[0011]

By the means described above, when the PLL circuit is operating, the frequency is stabilized, and when the operation is stopped after that, the output voltage of the phase comparator continues to maintain the previous state. The nonlinear component of the PLL circuit will not be superimposed on the input signal while it remains stable, and the deterioration of the demodulation distortion rate can be reduced.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals, and different parts will be mainly described here.

The frequency divider 15 to which the FM modulated wave output is supplied from the VCO 13 divides this frequency, and the frequency divided output of the frequency divider 15 is a phase comparator composed of a counter 161a and a D / A converter 161b. It supplies to one input of the counter 161a of 161. The oscillation signal from the reference oscillator 17 is supplied to the other of the counters 161 a, the phase comparator 16 compares the phase of the signal of the frequency divider 15 with the phase of the signal of the reference oscillator 17, and the signal is supplied to the amplifier 18. A control signal is supplied from the control terminal 20 to the counter 161a. The control signal serves as a switching signal for switching the counter 161a to the operating state or the stop state.

When the control signal is supplied from the control terminal 20 after waiting the time for the PLL loop of the PLL circuit to stabilize,
The counter 161a stops counting. At this time, the output signal of the phase comparator 161 necessary for stabilizing the frequency holds the value before the stop of the count 161a.
The frequency remains stable. As for the superimposition of the nonlinear component, the VCO1
Only the non-linear component of 3 itself affects the FM modulated wave.
Therefore, since the non-linear components of the other blocks forming the PLL circuit can be ignored at all, the non-linear component due to the PLL circuit does not exist in the FM modulated wave, and as a result, the demodulation distortion rate can be reduced.

Thus, even if the PLL circuit has a circuit configuration having some non-linear component without increasing the compensation circuit and the current, the demodulation distortion rate is reduced.
It is possible to realize an FM modulation circuit using a circuit.

Next, another embodiment of the present invention will be described with reference to FIG. This embodiment differs from the above-described embodiments in that the signal supplied to the input 11 is voice and the control signal for stopping the counter 161a is generated by controlling the level of the input voice signal.

That is, the audio signal supplied to the input 11 is supplied to the PLL circuit 10 and the detector 21. The output of the detector 21 is used as a control signal for the VCO 22 which is composed of a multivibrator capable of incorporating an IC.
The oscillation frequency of the VCO 22 is set to be low when the amplitude of the input signal 11 is large. The oscillation frequency of the VCO 22 becomes the clock of the counter and logic 23,
This produces a control signal.

A voice signal is input to the input 11, and the voice signal has the same distortion rate (about 2 to 3%) and the amplitude of the voice signal,
That is, it is assumed that two signals having different levels exist. In this case, the louder the human hearing,
The degree of distortion feels great. Taking advantage of this property,
The counter and logic 23 generates a pulse control signal having a different pulse width depending on the input voice level.

The oscillation frequency of the VCO 22 is set in advance so that the clock frequency of the counter and logic 23 becomes low when an input signal having a large amplitude is input. V
The oscillation frequency of the CO 22 is the counter and logic 23.
3A, a control signal of a pulse having a long cycle is generated from the output of FIG. 3A and the cycle for turning off the counter 161a is lengthened.

When the carrier wave modulated by the voice signal is demodulated, the period in which the counter in the PLL circuit 10 is OFF is set long, so that the demodulation distortion rate can be reduced.

Similarly, when an input signal having a small amplitude is input, the clock frequency of the counter and the logic 23 is set to be high, so that the output thereof is as shown in FIG. A control signal of a pulse having a short cycle is generated, and the counter 161a of the PLL circuit 10 is turned off.
Make the cycle shorter.

Therefore, when demodulating the carrier wave modulated by the audio signal, the counter 161a in the PLL circuit 10 is O even if a non-linear component exists in the PLL circuit 10.
Since the FF period is short, the demodulation distortion rate can be reduced. When the amplitude of the input signal is small, the clock frequency of the counter and the logic 23 becomes high, so that the control signal turns off the counter 161a in the PLL circuit 10.
Make the cycle shorter.

Therefore, when demodulating the carrier wave modulated by the audio signal, the non-linear component in the PLL circuit deteriorates the demodulation distortion rate. However, since the signal input in this case has a small amplitude, even if the demodulation distortion rate is somewhat deteriorated, it is possible to reproduce the sound without any particular audible problem.

The present invention is not limited to the above-described embodiment, but the frequency stability of the PLL circuit may not be maintained due to changes in the surrounding environment due to temperature or the like. Therefore, in the embodiment shown in FIG. The counter of the phase comparator is operated for a predetermined time at a rate of about once per second, and P
It is also possible to stabilize the PLL loop of the LL circuit.

[0025]

As described above, according to the FM modulation circuit of the present invention, even if a non-linear component exists in the PLL circuit, the demodulation characteristic can be improved by adding a simple circuit capable of incorporating an IC. It can be stabilized to a level that does not cause any problems in hearing.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram for explaining an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram for explaining another embodiment of the present invention.

FIG. 3 is an output waveform diagram of a main part of FIG.

FIG. 4 is a conventional circuit configuration diagram.

[Description of Codes] 11 ... Input, 12 ... Adder, 13 ... VCO, 14 ... Output, 15 ... Divider, 16 ... Phase comparator, 16a ... Counter, 16b ... D / A converter, 17 ... Reference oscillator , 18 ...
Amplifier, 20 ... Control terminal.

Claims (5)

[Claims] 1. An FM modulator using a PLL circuit, comprising: a comparator forming a part of the PLL circuit, which compares a desired signal in a PLL loop and a signal of a reference oscillator with different phases by a counter; And a means for stopping the operation of the FM modulation circuit. 2. The FM modulation circuit according to claim 1, wherein the comparator is controlled to be in an operating state every predetermined time. 3. The F according to claim 1, wherein the modulated signal supplied to the PLL circuit is a voice signal.
M modulation circuit. 4. The FM modulation circuit according to claim 1, wherein the FM modulation circuit is used for a voice modulation method of an RF modulator. 5. Based on the level of the input audio signal,
The FM modulation circuit according to claim 1, further comprising means for varying the operation and stop time of the comparator.