JP2948058B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit for detecting burst data synchronization in, for example, an optical network system of a time division multiple access system, and more particularly to a pseudo synchronization using a pseudo synchronization pattern. It is related to what prevents pulling in.

[0002]

2. Description of the Related Art FIG. 2 shows, for example, NTTR & D, Vol.
41, No. 1, 1992, "Method of detecting false synchronization in new synchronization interface", Hiromi Ueda et al. In the figure, reference numeral 101 denotes a terminal to which the received burst data RxD is input. This burst data RxD101
Includes the information signal (2) as shown in FIG.
A synchronization pattern (1) and error calculation code information (error detection code) (3) are added to this.
Reference numeral 1 denotes a frame synchronization circuit pattern comparison circuit which detects a synchronization pattern inserted in the input burst data RxD101. Numeral 2 is an encoding / decoding circuit for error operation code information, which decodes the error operation code information inserted in the burst data RxD101 and performs error operation encoding of the burst data RxD. The error information is compared with the code information to detect occurrence of an error. Reference numeral 3 denotes a frame synchronization protection circuit, which draws in frame synchronization from the synchronization pattern detected by the frame synchronization circuit pattern comparison circuit 1 passed through the gate circuit 10 and monitors loss of synchronization. Reference numeral 4 denotes a frame counter, which counts a frame period from an output of the frame synchronization protection circuit 3 and an output of a frame erroneous synchronization determination circuit 5 described later. 5 is a frame erroneous synchronization determination circuit,
Output 22 of the encoding / decoding circuit 2 for the error operation code information
Thus, monitoring is performed to determine whether or not the current frame synchronization pattern is a frame erroneous synchronization pattern. A gate circuit 10 performs AND gate control of a frame recognition pulse from the frame synchronization pattern comparison circuit 1 and a frame cycle pulse from the frame counter 4. Also,
Reference numeral 30 denotes the frame synchronization circuit pattern comparison circuit 1, the gate circuit 10, the frame synchronization protection circuit 3, and the frame synchronization circuit 3.
A main synchronization circuit including a counter 4, and a CRC (Cyclic Red) 31 composed of an error decoding code information encoding / decoding circuit 2.
An undancy check detection circuit 36 is an error continuation number counter composed of the frame erroneous synchronization determination circuit 5.

FIGS. 6 (a) and 6 (b) show received data 101 and respective circuit units 1 to 1 of the frame synchronization circuit of the conventional example 1 shown in FIG.
5 is an operation timing chart for explaining the output signal waveforms 21 to 25 of No. 5 with the temporal relationship between them. The numbers in parentheses in FIGS. 6 (a) and 6 (b) are also used in the case of Conventional Example 2.

Next, the operation will be described with reference to FIG. The received burst data RxD101 is input to the frame synchronization pattern comparison circuit 1, and the frame synchronization pattern comparison circuit 1 performs frame synchronization detection. When frame synchronization is detected, a synchronization pulse 21 is output to the gate circuit 10. The frame counter 4 counts the frame period at a certain phase, and outputs a synchronization pulse 24 to the gate circuit 10 according to the counting. The output of the gate circuit 10, which is the result of ANDing the two, is output to the frame synchronization protection circuit 3, where the burst data RxD101 and the frame counter 4 are output.
It is determined whether or not the phase matches. If the phases do not match, the frame synchronization protection circuit 3 outputs the mismatch pulse 2
3 is output to the frame counter 4, where the value of the internal counter is changed and the phase is shifted by one bit. Then, again, the burst data RxD101
It is determined whether or not the phase matches the phase of the frame counter 4. These series of operations are performed until the phases match. If the phases match, no mismatch pulse 23 is output, and the frame counter 4 stops changing the value of the internal counter.

On the other hand, received burst data RxD101
Is also input to the error-operation code information encoding / decoding circuit 2 and decodes the error-operation code information inserted into the burst data RxD 101 and outputs the burst data RxD
The error calculation coding of 101 is performed, the decoded information is compared with the code information, and the occurrence of an error is detected. When an error occurs, the mismatch information pulse 22 is output from the frame erroneous synchronization determination circuit 5.
Output to The frame mis-synchronization determination circuit 5 counts the mismatch information pulses 22. If the counted value exceeds a certain value (in the example of FIG. 6B, it exceeds "2" and becomes "3"). Judgment of synchronization, false synchronization occurrence pulse 2
5 is output to the frame counter 4. Upon receiving the false synchronization occurrence pulse 25, the frame counter 4 changes its internal counter value as described above, and starts frame synchronization hunting again. This series of operations continues until the erroneous synchronizing pulse 25 disappears.

FIG. 3 shows, for example, NTTR & D, Vol. 4
1, No. 1, 1992, "Method of Detecting False Synchronization in New Synchronous Interface", Hiromi Ueda et al. In the figure, first, reference numeral 101 denotes received burst data RxD. This burst data RxD includes, as shown in FIG.
In addition to the information signal (2), a synchronization pattern (1) and error operation code information (error detection code such as CRC code) (3) are added. In FIG.
2, 10, 3, 4, and 5 are the same as those shown in FIG. 2, and 6 is an auxiliary frame counter which has the same function as the frame counter 4. is there. Reference numeral 7 denotes a rear protection counter having the same function as the frame synchronization protection circuit 3. A gate circuit 11 performs an AND gate control of a frame recognition pulse 21 from the frame synchronization circuit pattern comparison circuit 1 and a frame synchronization pulse 26 from the auxiliary frame counter 6. Reference numeral 30 denotes the circuits 1 and 2 as in FIG.
A main synchronization circuit including 10, 3, and 4; a CRC error detection circuit 31 including the circuit 2; a continuous error counter 36 including the circuit 5; 33; an auxiliary frame counter 6; a gate circuit 11; This is a sub-synchronous circuit including a counter 7.

FIGS. 6 (a) and 6 (b) show the output signal waveforms of the circuits 1 to 5 of the conventional example 1 of FIG. 2 as described above. FIG. 6 shows an output signal waveform, and the operation of the second conventional example will be described with reference to FIG.

[0008] The received burst data RxD101 is input to a frame synchronization pattern comparison circuit 1, and the frame synchronization pattern comparison circuit 1 performs frame synchronization detection. When the frame synchronization detection is performed, the synchronization pulse 21
Is output to the gate circuit 10. The frame counter 4 counts the frame period at a certain phase, and outputs a synchronization pulse 24 to the gate circuit 10 according to the count. The output of the gate circuit 10, which is the result of ANDing the two, is output to the frame synchronization protection circuit 3, where the burst data RxD101 and the frame data are output.
It is determined whether or not the phase of the counter 4 matches. If the phases do not match, the non-coincidence pulse 23 is output from the frame synchronization protection circuit 3 to the frame counter 4, and the frame counter 4 changes the value of the internal counter and sets the phase to 1
Shift a bit. Then, again, the burst data RxD1
It is determined whether 01 and the phase of the frame counter 4 match. These series of operations are performed until the phases match. If the phases match, no mismatch pulse 23 is output, and the frame counter 4 stops changing the value of the internal counter.

On the other hand, received burst data RxD101
Is also input to the error-operation code information encoding / decoding circuit 2 and decodes the error-operation code information inserted into the burst data RxD101 and outputs the burst data Rx
The error calculation coding of D101 is performed, the decoded information is compared with the code information, and the occurrence of an error is detected. When an error occurs, the mismatch information pulse 22 is output to the frame erroneous synchronization determination circuit 5. The frame mis-synchronization determination circuit 5 counts the mismatch information pulses 22. If the counted value exceeds a certain value (in the example of FIG. 6B, it exceeds "2" and becomes "3"). Judgment of synchronization, false synchronization occurrence pulse 2
5 is output to the auxiliary frame counter 6. The auxiliary frame counter 6 starts synchronous hunting when receiving the false synchronization occurrence pulse 22. This series of operations continues until the erroneous synchronization occurrence pulse 22 disappears. Frame counter 4
Does not perform synchronous hunting and maintains the current state, that is, its continuous operating state. When the auxiliary frame counter 6 detects the synchronization state, the counter value of the auxiliary frame counter 6 is loaded into the frame counter 4, and
Thereafter, the frame counter is operated by the frame counter 4, and the synchronization state is maintained.

FIG. 8 is disclosed as a conventional example in Japanese Patent Application Laid-Open No. 62-264743, and is disclosed in, for example, "PCM Communication Technology" (published by Sanho Publishing Co., Ltd.) (Naoshi Kaneko, 5-4 frame synchronization). 1 shows the configuration of the shown conventional frame synchronization circuit. In FIG. 8, reference numeral 801 denotes received burst data RxD from the master station. This received burst data R
As shown in FIGS. 4 and 5, the xD has a synchronization pattern (1) inserted at its head and an error detection code (3) added at its rear end. A synchronization pattern detection circuit 802 detects the synchronization pattern (1) inserted in the data RxD1. Reference numeral 803 denotes a gate generation circuit for detecting a synchronization pattern. 804 and 805 are gate signals GP and WGP. Reference numeral 806 denotes a synchronization pattern detection pulse SDP. 807 is a frame control circuit. 80
8 is a frame pulse. 809 and 810 are gate circuits G1 and G2, respectively. 811 is a synchronization pulse S
P and 812 are asynchronous pulse ASPs. 813,81
Reference numeral 4 denotes a counter circuit. One counter circuit 813 is incremented by the synchronous pulse SP, and the asynchronous pulse A
Reset by SP. The other counter circuit 814 is
It is incremented by the asynchronous pulse ASP and reset by the synchronous pulse SP. Reference numeral 815 denotes a pulse SSP indicating a frame synchronization establishment state, which is output when the counter content of the counter circuit 813 exceeds the backward protection threshold value 821. Reference numeral 816 denotes a pulse NSP for instructing resynchronization pull-in, and is output when the count of the counter circuit 814 exceeds the forward protection threshold 819. A control pulse CP 817 is sent from the frame control circuit 807 and controls the gate generation circuit 803.

FIG. 9 is a timing chart showing a frame synchronization pull-in process from the hunting state to the synchronization establishment state of the frame synchronization circuit of FIG. In the figure, reference numeral 818 denotes a stepping pulse of the counter circuit 814;
19 is a forward protection threshold, 820 is a counter circuit 813
821 indicates a backward protection threshold value.

One frame has a configuration in which burst data of a master station into which a synchronization pattern is inserted is headed, and a plurality of burst data from a plurality of slave stations are multiplexed by time division.

Next, the operation will be described with reference to FIGS. The burst data RxD 801 transmitted at the frame period and received by each station is input to the synchronization pattern detection circuit 802 and matched with the synchronization pattern in the gate signal WGP 805.

The synchronization pattern detection circuit 802 sends a synchronization pattern detection pulse SDP 806 to the frame control circuit 807, the gate generation circuit 803 for detecting the synchronization pattern, the gate circuits G1, 809, and the gate circuits G2, 810 when the synchronization pattern is detected. .

The frame control circuit 807 includes a frame counter for transmitting a frame pulse FP 808 having a frame period, and a circuit for monitoring a frame synchronization state and transmitting a control pulse CP 817 to the gate generation circuit 803. The frame counter is given a frame reference by the sync pattern detection pulse SDP806.

The gate generation circuit 803 outputs the gate signal GP8
04, a circuit for controlling transmission of the WGP 805. Once the synchronization pattern detection pulse SDP806 is output, the gate signal WGP805 is closed, and after the next frame, the gate signal WGP805 is located at the position where the synchronization pattern detection pulse SDP806 is detected. , A gate signal GP804 for limiting the detection position is output.

Received burst data RxD of next frame
(I-3 in FIG. 9) is input to the synchronous pattern detection circuit 802, and pattern matching is performed in the gate signal GP804.

Here, if the detection in the previous frame is an erroneous detection, the detection of the synchronization pattern in the gate signal GP804 is not performed. In this case, the gate circuits G2, G8
The asynchronous pulse ASP is output from 10, the asynchronous pulse counter circuit 814 is incremented, and the synchronous pulse counter circuit 813 is reset.

If the synchronous pattern is not detected continuously after the next frame (i-2 in FIG. 9), the asynchronous pulse
The counter circuit 814 is sequentially incremented.

When the count exceeds the forward protection threshold 819, the asynchronous pulse counter 814
A pulse NSP 816 for instructing resynchronization is sent to the frame control circuit 807. Frame control circuit 807
Outputs a control pulse CP817 to the gate generation circuit 803, and outputs a gate signal WGP805 to the gate generation circuit 803.
Is sent. As a result, the state shifts to the frame synchronization re-lock state.

In the above state, the synchronization pattern of the received burst data RxD1 of the next frame is detected (i-1 in FIG. 9), and when the synchronization pattern detection pulse SDP806 is output, the frame control circuit 807 as described above. Of the frame reference and setting of the gate signal GP804.

When a synchronization pattern is detected in the gate signal GP804 from RxD (i in FIG. 9) of the next frame, the synchronization pattern detection circuit 802 outputs the synchronization pattern detection signal SDP806 of the frame period to the gate circuits G1 and 809,
G2, 810.

The synchronous pattern detection signal SDP806 is ANDed with a frame pulse FP808 having a frame period by gate circuits G1 and 809. As a result, the gate circuits G1 and 809 output the synchronization pulse SP8
17 is output. In addition, the synchronous pulse counter circuit 81
3 is incremented by receiving the synchronous pulse SP817, and the asynchronous pulse counter circuit 814 is reset.

When the synchronous pattern detection signal SDP806 is continuously output after the next frame (i + 1 in FIG. 9),
The synchronization pulse SP811 is sequentially output, and the synchronization pulse
The counter circuit 813 is sequentially incremented.

When the count exceeds the backward protection threshold value 821, the synchronization pulse counter circuit 813 sends a pulse SSP 815 indicating a frame synchronization established state to the frame control circuit 807. As a result, the frame control circuit 807 determines that a stable state has been established in which frame synchronization has been established, and raises the forward protection threshold 819 to create a state in which a transition to a hunting state due to a bit error or the like is prevented.

However, in the conventional frame synchronization circuit shown in FIG. 8, in a system in which the same pattern is likely to be continuously transmitted, such as industrial process state information, the frame synchronization pattern happens to be coincident with the above information. However, when the same pattern as that of the above, that is, the pseudo frame synchronization pattern is included, there is a problem that the pseudo frame synchronization pattern may be mistaken for a normal synchronization pattern to cause an erroneous synchronization state.

Japanese Patent Laid-Open No. Sho 62-2647 discloses a frame synchronization circuit which solves this problem and can prevent a malfunction due to a pseudo frame synchronization pattern transmitted continuously.
No. 43 discloses an embodiment of the invention, which is shown in FIG. 10 and described below with reference to FIG. 11 showing a timing chart thereof. FIG. 10 shows such a frame synchronization circuit, and FIG. 11 is a timing chart showing an operation example of this frame synchronization circuit. In FIG. 10, the same symbols as those in FIGS. 8 and 9 indicate the same or corresponding parts.

The differences between the circuit of FIG. 10 and the frame synchronization circuit of FIG. 8 will be described below. First, in FIG. 10, reference numeral 830 denotes the reception burst data Rx including the information signal (1) as shown in FIGS.
DT with a frame synchronization pattern at the beginning
(2) is inserted, and an error detection code (3) is added to the last part. An error detection code decoding circuit 831 decodes the error detection code. Reference numeral 832 denotes error detection information EPO, which is output from the error detection code decoding circuit 831. This error detection information EPO is composed of 1-bit information. 833 is a gate circuit G3. 834 is an error information pulse EP1 output from the gate circuit G3. Reference numeral 835 denotes a counter circuit which outputs an error information pulse E
Stepped by P1. Reference numeral 836 denotes a frame false synchronization pulse FEP, which is output when the content of the counter circuit 835 exceeds a certain value. 837 is a gate circuit G
4. Reference numeral 838 denotes a pulse NSP1 for instructing frame synchronization re-pulling, which is supplied from the gate circuits G4 and 837 to the frame control circuit 807. 839 is a gate circuit G5. 840 is a reset pulse RS for resetting the counter circuit 813. Reference numeral 841 denotes a set-reset type flip-flop circuit which has a set state in the initial state and a pulse SS indicating the frame synchronization established state.
It is reset (R) at P and set (S) at a pulse NSP for commanding resynchronization pull-in. 842 is a set output (Q) pulse ST of the flip-flop circuit 841.

The received burst data RxDT 830 is
As shown in FIGS. 4 and 5, fixed length (l bit)
Data, a synchronization pattern (m bits) (2), an information signal (n bits) (1), an error detection code (k bits)
(3) are inserted at the designated fixed time positions in the form of time division multiplexing.

FIG. 11 shows a transition process from the frame erroneous synchronization state to the synchronization established state in the frame synchronization circuit. In the figure, reference numeral 843 denotes a counter circuit 8
35 shows stepping pulses. 844 indicates an error information pulse EP generated by frame mis-synchronization or bit error.
This is a threshold value of the counter circuit 835 for protecting 1. One frame has a configuration in which burst data from the master station having a synchronization pattern is at the head and burst data from each slave station is multiplexed.

First, the reception burst data RxDT83
0 is a signal obtained by adding an error code (3) to an information signal (2) encoded by a cyclic code or the like having a high error detection capability,
It is input to the synchronization pattern detection circuit 802 and the error detection code decoding circuit 831.

The synchronization pattern detection circuit 802 detects a synchronization pattern in the gate signal WGP805 and outputs a synchronization pattern detection pulse SDP806. The synchronization pattern detection pulse SDP806 is transmitted to the frame control circuit 807.
This is used only for giving a frame reference to the CDMA and setting the gate signal GP804 to the gate generation circuit 803, and is also provided to the error detection code decoding circuit 831.

On the other hand, reception burst data RxDT83
Since the information signal (2) of 0 has its insertion time position fixedly specified in advance, its first bit position can be determined to be a position delayed by a predetermined bit (m bits) from the synchronization pattern detection pulse SDP806. .

When receiving the synchronization pattern detection pulse SDP806, the error detection code decoding circuit 831 starts decoding the error detection code (3) after a predetermined bit (m bits) from the reception position, and outputs the information signal. (2) + error detection code
(3) Perform decoding for n + k bits, which is the bit length.
When a decoding error occurs, the error detection information EPO
832 to the gate circuits G3, 833. If a decoding error occurs and error detection information EPO832 is issued, the error information pulse E is output from the gate circuits G3 and 833.
P1,834 is output, and this error information pulse EP1,834 is output.
The counter circuit 835 is incremented by 834.

Received burst data R after the next frame
When a synchronization pattern is continuously detected in the gate signal GP804 from the xDT 830 (i-3 and thereafter in FIG. 12), as described above, the synchronization pulse counter circuit 813 sequentially steps by the synchronization pattern detection signal SDP806 every frame period. Is advanced. At the same time, decoding by the error detection code decoding circuit 831 is also performed sequentially. When a decoding error occurs continuously, the counter circuit 83 generates an error detection pulse EPO and an error information pulse EPI each time the decoding error occurs.
5 is advanced.

The two counter circuits 813 and 835 compete with each other, and the content of the counter circuit 835 is changed to the forward protection threshold value 8.
If it exceeds 44, it is determined that the synchronization pattern detected in the gate signal GP804 is a pseudo synchronization pattern,
The Fresn false synchronization pulse FEP836 is applied to the gate circuit G4.
837.

Then, the gate circuits G4 and 837 output the pulse NSP1 for instructing the re-locking of the frame synchronization, and give the frame control circuit 838 a frame synchronization pull-in instruction. On the other hand, the gate generation circuit 803 outputs the gate signal WGP
805 is output immediately. Also, the gate circuits G5, 83
9 outputs a reset pulse RE840 to reset the counter circuit 813.

As a result, the synchronization pattern is detected again. When the synchronization pattern is detected, the reference of the frame reference to the frame control circuit 807 and the gate signal G are transmitted again.
The setting of P804 is performed.

Next, the reception burst data RxDT
830 (i in FIG. 12) and thereafter, the gate signal GP804
The synchronization pattern is detected within the error detection information EP
When O832 does not occur, the synchronous counter circuit 8
13 exceeds the backward protection threshold 821. At this time, the synchronization counter circuit 813 sends a pulse SSP indicating a frame synchronization establishment state to the set / reset flip-flop circuit 841 and the frame control circuit 807. The set / reset type flip-flop circuit 841 is reset to make its set output (Q) pulse ST a meaningless signal. Further, the frame control circuit 807 determines that the frame synchronization is in a stable state in which the frame synchronization is established, and increases the forward protection threshold value of the asynchronous counter circuit 814.
This prevents a transition to a hunting state due to a bit error or the like.

In the frame synchronization circuit of FIG. 10, when an erroneous synchronization occurs in the pseudo frame synchronization pattern, a decoding error 834 of the error detection code is generated, and the number of occurrences, which is a count output by the counter circuit 835, is reduced. With the configuration in which the re-synchronization is performed when a certain threshold value is continuously exceeded, erroneous synchronization with the pseudo-frame synchronization pattern can be prevented and reliable frame synchronization can be performed.

[0041]

SUMMARY OF THE INVENTION The first and second prior arts described with reference to FIGS. 2 and 6, FIGS. 3 and 6, respectively.
The example frame synchronization circuit was configured and operated as described above.However, in a system where there is a high possibility that continuous transmission of the same pattern is performed, such as, for example, industrial process state information, etc. In the case where the above information happens to be the same pattern as the frame synchronization pattern, that is, the pseudo synchronization state is included and the pseudo synchronization state is included, and the frequency of occurrence of the pseudo synchronization pattern is equal to or higher than a set certain threshold value. When the re-hunting is determined as the pseudo-synchronization, if the frequency of occurrence of the pseudo-synchronization is smaller than the threshold in the conventional frame synchronization circuits of FIGS. 2 and 3, erroneous synchronization due to the pseudo-frame synchronization cannot be prevented. There is a problem that a case may occur.

In the third conventional frame synchronization circuit described with reference to FIGS. 8 and 9, the same pattern is continuously transmitted as described above, for example, as in the case of industrial process state information. In a system that is likely to be performed, if the information happens to be the same pattern as the frame synchronization pattern, that is, if the pseudo frame synchronization pattern is included and in the pseudo synchronization state, the pseudo frame synchronization pattern is replaced with the normal synchronization pattern. A false synchronization state may occur by mistake, and in order to improve this, it has been made for the purpose of preventing a malfunction due to a pseudo frame synchronization pattern transmitted continuously,
In the frame synchronization circuit described with reference to FIGS. 10 and 11, when an erroneous synchronization occurs in the pseudo frame synchronization pattern, a decoding error of the error detection code is generated, and the number of occurrences is a certain threshold. With a configuration in which re-synchronization is performed when the value is exceeded, erroneous synchronization to the pseudo frame synchronization pattern can be prevented so that reliable frame synchronization can be performed. When the frequency of occurrence of the pseudo-synchronization pattern is equal to or higher than a predetermined threshold value and the re-hunting is determined as pseudo-synchronization, if the frequency of occurrence of the pseudo-synchronization is smaller than the threshold value, false synchronization by pseudo-frame synchronization is performed. There is a problem that it may not be possible to prevent the problem.

Here, "when the frequency of occurrence of pseudo-synchronization is smaller than the threshold value" is a precondition that the number of error detections is continuously counted by the error detection at the frame synchronization position by the pseudo-sync frame. It is assumed that rehunting occurs when the threshold value is exceeded, but error detection is not performed before the threshold value is exceeded (for example, when the same data as the result of the CRC operation comes depending on the data), the threshold value is set. Is reset once, and this state is referred to as "the above case." However, in the above conventional rehunting method, the rehunting due to error detection exceeds a certain threshold. It is done only by things.

Therefore, in these conventional frame synchronization circuits, even if an error is detected, rehunting is not executed unless the error exceeds a certain threshold value, and malfunction due to pseudo frame synchronization cannot be prevented. Was something.

In these conventional circuits, when error detection exceeds a certain threshold value, as shown in FIG. 12, the pseudo synchronization after the normal frame synchronization pattern NP in the burst data RxD is performed. When synchronization is applied in the pattern PP, the subsequent operations are: PP frame synchronization → error detection → exceeding the threshold → rehunting start → P
The sequence of frame synchronization of P → error detection → exceeding the threshold → rehunting start → synchronization by a normal frame has the disadvantage that it takes time.

The present invention has been made to solve the above-mentioned problems, and it is possible to reliably prevent a false synchronization operation due to a pseudo frame synchronization pattern even if the frequency of occurrence of the pseudo synchronization pattern is lower than a threshold value. It is another object of the present invention to provide a frame synchronization circuit capable of quickly performing the operation of shifting to the synchronization by the normal frame.

[0047]

A frame synchronization circuit according to the present invention is a frame synchronization circuit for counting a frame period at a certain phase.
And its phase and transmitted at regular intervals.
And synchronization pattern of the phase included in the burst data that are
By determining whether the burst data matches, the burst data
Frame synchronization circuit that performs frame synchronization
In the frame synchronization pull-in process,
The only when the synchronizing pattern included in the data is detected
Error detection for outputting the disagreement information pulses when an error occurs by decoding the previously error detecting code added to the burst data
A code decoding circuit, sending the burst data at a predetermined period
A frame length counter circuit for counting the same time length as one frame length for output by the phase-free, the frame length counting times
The burst data within one frame length of time counted by the
A synchronization pattern counting circuit for counting the number of synchronization patterns over data, and counts the number of the mismatch information pulse, its value
It exceeds a certain value, and the synchronization pattern counting circuit a total
The number of synchronization patterns of the above burst data is 2
A frame that outputs a false synchronization occurrence pulse when
An erroneous synchronization determination circuit, and synchronization included in the burst data.
When receiving the pattern and the above-mentioned erroneous synchronization generation pulse,
And a sub-synchronous circuit for starting the ringing .

Further, according to the frame synchronization circuit of the present invention, the discrepancy information counted by the frame erroneous synchronization determination circuit is provided.
The above-mentioned constant value serving as the threshold value of the number of pulses is a variable value.

Further, the frame synchronization circuit according to the present invention distributes and arranges the error detection code of the synchronization pattern into a plurality of burst data, and synthesizes the error detection codes over the plurality of burst data. The error detection can be performed.

[0050]

In the frame synchronization circuit according to the present invention, the pseudo-frame synchronization pattern is detected by the error detection code decoding circuit, and at the same time, it is monitored whether or not a plurality of synchronization patterns exist in one frame. Is exceeded, and only when there are two or more synchronization patterns in one frame, re-pulling into frame synchronization is performed, whereby false synchronization due to the pseudo frame synchronization pattern can be reliably prevented. Can be done quickly.

Further, in the frame synchronization circuit according to the present invention, the mismatch information counted by the frame erroneous synchronization determination circuit is counted.
Since the above-mentioned constant value, which is the threshold value of the number of report pulses, is a variable value, erroneous synchronization due to the pseudo frame synchronization pattern can be more reliably prevented.

[0052]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a frame synchronization circuit according to an embodiment of the present invention. In the figure, the same reference numerals as those in FIGS. 2 and 3 denote the same or corresponding parts. The difference between the frame synchronization circuit of the present embodiment and the frame synchronization circuits of FIGS. 2 and 3 will be described. First, in FIG.
Reference numeral 102 denotes a clock, and the received burst data Rx
It has the same speed as the reception clock of D101. 9
Is a frame counting circuit, which counts one frame length by counting the clock 102. Reference numeral 8 denotes a synchronization pattern counting circuit which receives a frame pulse from the frame counting circuit 9 and a synchronization pulse from the frame synchronization pattern comparison circuit 1 and counts the number of frame synchronization patterns in one frame. One frame is a head of burst data from the master station having a synchronization pattern, and has a configuration in which burst data RxD from each slave station is multiplexed in a time division manner.

In FIG. 1, each part surrounded by a dashed line is a main synchronization circuit 30 similar to that in FIG.
Is a CRC error detection circuit, 32 is a pseudo-synchronization determination circuit comprising the frame erroneous synchronization determination circuit 5, 33 is a sub-synchronization circuit similar to that in FIG. 3, and 34 is a synchronization pattern counting circuit provided for the first time in the first embodiment. A counting circuit (2),
Reference numeral 35 denotes a counting circuit (1), which is a frame counting circuit provided for the first time in the first embodiment.

FIG. 6 shows each of the circuits 1 to 9 of the first embodiment of FIG.
2 is an operation timing chart for explaining the output signal waveforms of FIG. The received burst data RxD101 as shown in FIG. 4 is obtained by adding a synchronization pattern (1) before an information signal (2) encoded with a cyclic code or the like having a high error detection capability, and an error detection code ( The received burst data RxD101 is input to the frame synchronization pattern comparison circuit 1, and the frame synchronization pattern comparison circuit 1 performs frame synchronization detection.

When the frame synchronization is detected, a synchronization pulse 21 is output to the gate circuit 10. The frame counter 4 counts the frame period at a certain phase, and outputs a synchronization pulse 24 to the gate circuit 10 according to the count. The output of the gate circuit 10 is output to the frame synchronization protection circuit 3 and the frame synchronization protection circuit 3
Then, it is determined whether or not the burst data RxD101 matches the phase of the frame counter 4. If the phases do not match, the non-coincidence pulse 23 is output from the frame synchronization protection circuit 3 to the frame counter 4, and the frame counter 4 changes the value of the internal counter and sets the phase to 1
Shift a bit. Then, again, the burst data RxD1
It is determined whether or not 01 and the phase of the frame counter 4 match. This is called synchronous hunting. These series of operations are performed until the phases match. If the phases match, no mismatch pulse 23 is output, and the frame counter 4 stops changing the value of the internal counter.

On the other hand, received burst data RxD101
Is also input to the error operation code information code decoding circuit 2 to decode the error operation code information (3) inserted in the burst data RxD101 and perform error operation encoding of the burst data RxD101. The decoding information and the code information are compared to detect the occurrence of an error. When an error occurs, the mismatch information pulse 22 is output to the frame erroneous synchronization determination circuit 5.

The clock 102 is input to the frame counting circuit 9 and counts the clock 102 to make 1
The frame length is counted. The synchronous pattern counting circuit 8 includes:
The frame pulse 29 from the frame counting circuit 9 and the synchronization pulse 21 from the frame synchronization pattern comparison circuit 1 are input, and the synchronization pattern counting circuit 8 counts the number of frame synchronization patterns in one frame. When there are two or more frame synchronization patterns (two synchronization pulses 21 in frames i-3 and i-2 in FIG. 7), the counting circuit (1) 35 (frame counting circuit 9) and the counting circuit (2)
At 34 (synchronous pattern counting circuit 8), it is determined that two or more frame patterns exist in one frame length in this way, and a plurality of synchronous pattern existence information pulses 2
8 (frame i-2 in FIG. 7) is output to the frame erroneous synchronization determination circuit 5. Here, actually, the frame synchronization
Since there may be two patterns when the phase is free, the counting circuit (1) 35 must be synchronized with the frame counter 4 and the auxiliary frame counter 6, but they are not shown here. ing.

The counter circuit included in the frame mis-synchronization determination circuit 5 counts the non-coincidence information pulse 22, and the count value of the counter in the frame mis-synchronization determination circuit 5 is a certain value (threshold). For example, when the number exceeds 3, and when the plurality of synchronization pattern information pulses 28 indicating that two synchronization pulses 21 are included in the one frame are input to the frame false synchronization determination circuit 5, , And outputs a false synchronization occurrence pulse 25 to the auxiliary frame counter 6. Here, even if two synchronization pulses 21 are included in one frame,
Since the synchronization may be normally performed, the condition that the count value of the counter exceeds a certain threshold value and the condition that the two synchronization pulses 21 are included in one frame are as follows. When the AND condition is satisfied, the frame mis-synchronization determination circuit 5 outputs a mis-synchronization occurrence pulse 25.

When the auxiliary frame counter 6 receives the erroneous synchronization occurrence pulse 25 from the frame erroneous synchronization determination circuit 5, it starts frame synchronization hunting. This series of operations continues until the erroneous synchronizing pulse 25 disappears. On the other hand, the frame counter 4 holds the current state. When the auxiliary frame counter 6 detects the frame synchronization state, the counter value of the auxiliary frame counter 6 is loaded into the frame counter 4, and thereafter, the frame
The frame counter is operated by the counter 4, and the synchronous state is maintained.

In the frame synchronization circuit according to the first embodiment, the error detection code decoding circuit 2 detects a pseudo frame synchronization pattern and simultaneously monitors whether or not a plurality of synchronization patterns exist in one frame. Re-pulling into frame synchronization is performed only when the detection information exceeds a certain value and when there are a plurality of synchronization patterns in one frame. The rehunting does not take much time unlike the conventional example, and the operation can be performed quickly.

In this regard, in the circuit of FIG. 3 of the conventional example 2 and the circuit of FIG. 10 of the conventional example 4, only re-hunting by synchronization detection → synchronization protection → error detection is performed.

The operation of the first embodiment will be described below for easier understanding. That is, in the first embodiment, first, as shown in FIG. 4, the received burst data RxD is converted into an information signal encoded with a cyclic code having a high error detection capability in one burst data. In FIG. 4, one burst data includes a synchronization pattern (1) and an information signal (2). ) And an error detection code (3).

As described above, the error detection code is added to the information signal (2).
When (3) is added, it depends on the method, but 1. 1. Perform synchronization detection based on the synchronization pattern (1) and determine the position of the information signal (2). When the information signal (2) and the synchronization pattern (1) determined as described above are subjected to an operation for obtaining a “cyclic code having a high error detection capability”, for example, a CRC operation,
An “error detection code” is calculated. Here, the CRC operation includes CRC5, CRC6, and the like. The above information signal
After the data of (2) and the synchronization pattern (1), the above 2. By adding the “error detection code” (3) calculated in (1), one burst data can be constituted.

Normally, the synchronization pattern and the error detection code may be closed in one burst data. Depending on the method, the synchronization pattern and error detection code may be spread over several frames, for example, three frames, that is, closed in three frames. Is also good. This case indicates that the three-frame synchronization pattern is regarded as one synchronization pattern and the three-frame error detection code is regarded as one synchronization pattern.

Here, erroneous synchronization means that the same pattern as the synchronization pattern appears at a position where the synchronization pattern is not originally located, and the frame synchronization circuit operates by regarding the same as a synchronization pattern. To prevent this, a CRC operation is performed to detect whether a transmission error has occurred, and the like. However, there is a limit to CRC calculation (because the detection capability is not 100%), and
In rare cases, a CRC operation may be skipped in the data (ie, CRC
In some cases, the same pattern as that of the synchronization frame may appear. Also, in the circuits of the conventional examples 2 and 4 shown in FIGS. 3 and 10, the CRC calculation error is counted up to a certain threshold value, and when it exceeds this threshold value, it is regarded as erroneous synchronization. If data that surpasses the operation appears, it will not be regarded as erroneous synchronization.

In order to cope with the above, one of the rehunting conditions includes a condition as to whether or not there are two or more synchronization patterns in one frame to prevent erroneous synchronization of the frame synchronization circuit. This is the present invention, and as described above, the circuits of Conventional Examples 2 and 4 do not have this condition.

That is, the difference in this point will be more easily understood with reference to the flowcharts of FIGS.
In the circuits of the conventional examples 2 and 4, as shown in a simplified operation flow of FIG. 13, frame synchronization is obtained in step S1, error detection is performed in step S2, and error detection is performed in step S3.
It is determined whether or not the threshold value has been exceeded. If the determination is NO, the process returns to step S2. If the determination is YES, erroneous synchronization is determined, and re-hunting is performed in step S5. In this method, when frame synchronization is performed at the position of the pseudo synchronization pattern as shown in FIG. 12, it is assumed that a CRC calculation error occurs because the position indicating the calculation result such as CRC is shifted. However, since a CRC operation error due to a real transmission error also needs to occur, a threshold is set and the CRC
It is monitoring whether an arithmetic error has occurred. Therefore, if the same data as the operation result appears at the operation result position corresponding to the pseudo synchronization pattern position before the threshold value is exceeded, no operation error occurs, and the counter for counting the threshold value is returned to 0. When this phenomenon occurs periodically, it becomes impossible to escape from pseudo-synchronization, and the pseudo-synchronization state is maintained.

On the other hand, according to the first embodiment of the present invention, as shown in FIG. 14, after detecting the frame synchronization in step S1 and then in step S6, as shown in FIG.
Thus, there are two or more synchronization patterns in one frame (FIG. 7).
Synchronization pulses 2 in frames i-3 and i-2 of FIG.
1) and whether a CRC calculation error has occurred at that time to determine whether or not pseudo-synchronization has occurred.

That is, in the flow of FIG. 14, if there is only one synchronization pattern in one frame,
In step S7, a normal threshold value is set and the same operation as in the conventional example is performed. However, if there are two or more synchronization patterns in step S6 (YES in step S6), a CRC calculation error occurs at that time. Is determined, that is, since there is a real transmission error as described above, CR
In step S8, whether the C operation error has occurred continuously is changed to a threshold value smaller than the above-mentioned normal threshold value for pseudo synchronization, and then error detection is performed in step S2. By performing the determination in step S3 to determine whether or not the threshold value has been exceeded, the pseudo-synchronous determination can be performed with certainty and re-hunting can be performed quickly.

Embodiment 2 FIG. In the second embodiment of the present invention, even if the data transmission becomes abnormal even in the flow of FIG. 14 of the first embodiment, as shown in the flow of FIG.
In step 9, the threshold value for pseudo synchronization can be changed.

The basic configuration of the second embodiment is the same as that of the first embodiment shown in FIG. 1. However, in the second embodiment, the contents of the count value of the counter circuit included in the frame erroneous synchronization detection circuit are When the threshold value for pseudo synchronization is exceeded, and when two or more synchronization patterns included in the burst data transmitted at a fixed period are detected, and synchronization cannot be detected even when synchronization hunting is performed. , The threshold value for the pseudo synchronization can be changed, that is, the threshold value can be made smaller, so that the synchronization hunting can be performed more reliably, and the determination of the pseudo synchronization can be further improved. It is something that can be assured.

Embodiment 3 FIG. Next, a third embodiment of the present invention, which is an embodiment for multi-burst data, will be described. The received burst data RxD1 to RxD3 of the third embodiment shown in FIG. 5 are composed of three burst data and constitute the received burst data having the error detection code corresponding to the received burst data RxD shown in FIG. Things. That is, in the third embodiment, an error detection code such as a CRC code is scattered in three burst data, and error detection is performed by combining three synchronization pattern error detection codes in each of the burst data RxD1 to RxD3. It constitutes a possible error detection code.

The basic structure of the third embodiment is the same as that of the first embodiment shown in FIG.
The circuit configuration such as 6, 9 recognizes one frame but recognizes three frames.

The third embodiment performs the same operation as the first embodiment. That is, when erroneous synchronization occurs in a pseudo frame synchronization pattern in three burst data, a decoding error of an error detection code is generated. is there. That is, as in the description of the first embodiment, in FIG. 5, the “synchronization pattern” in the 1.3 burst data RXD1 to RXD3 is regarded as one “synchronization pattern”, and synchronization is detected. The “sync pattern” and “information signal” in the 2.3 burst data RXD1 to RXD3 are regarded as one “sync pattern” and “information signal”. A CRC operation is performed on the “synchronization pattern” and the “information signal” regarded as one in section 3.2. Then, the CRC calculation result is calculated. 4.3 Insert the CRC calculation result calculated in section “Error Detection Code” in the three burst data.

According to the third embodiment, the frame counting circuit 9 counts the same time length as one frame length in a phase-free manner in the pseudo synchronization determination, and counts the number of occurrences of the synchronization pattern within the counting time. Synchronous pattern counting circuit 8
With this configuration, it is configured to monitor the absence of a plurality of frame synchronization patterns in one frame, and to perform re-frame synchronization pull-in when the number of decoding errors continuously exceeds a certain threshold. Thus, it is possible to prevent the pseudo synchronization with the pseudo frame synchronization pattern and perform the reliable frame synchronization.

In the third embodiment, the synchronization pattern and the error detection code are not closed in one burst data, but are dispersed in a plurality of frames such as three frames, so that the three-frame synchronization pattern is changed to one synchronization pattern. And the present invention can be applied to the case where the error detection code of three frames is regarded as one synchronization pattern, the effect of preventing the pseudo synchronization with the pseudo frame synchronization pattern and performing the reliable frame synchronization. Is obtained.

[0077]

As described above, according to the frame synchronization circuit of the present invention, when erroneous synchronization occurs in the pseudo frame synchronization pattern, the error detection code decoding circuit decodes the error detection code. A frame counting circuit for generating a synchronization error and counting the same time length as one frame length in a phase-free manner in the pseudo synchronization determination, and a synchronization pattern counting circuit for counting the number of occurrences of the synchronization pattern within the counting time. Since it is monitored that there is no more than one frame synchronization pattern in the frame, and when the number of decoding error occurrences continuously exceeds a certain threshold, it is configured to perform re-frame synchronization pull-in. There is an effect that pseudo synchronization with the pseudo frame synchronization pattern is prevented, and reliable frame synchronization can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a frame synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a frame synchronization circuit according to Conventional Example 1.

FIG. 3 is a diagram showing a configuration of a frame synchronization circuit according to Conventional Example 2.

FIG. 4 is a diagram showing one received burst data input to the frame synchronization circuit according to the first embodiment.

FIG. 5 is a diagram showing three received burst data input to a frame synchronization circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an operation timing chart of a frame synchronization circuit according to Conventional Examples 1 and 2.

FIG. 7 is a diagram showing an operation timing chart of the frame synchronization circuit according to the first embodiment of the present invention.

FIG. 8 shows a frame synchronization circuit according to Conventional Example 3
FIG. 1 is a diagram illustrating a configuration of a frame synchronization circuit disclosed as a conventional example in JP-A-264743.

FIG. 9 is an operation timing chart of the circuit in FIG. 8;

FIG. 10 shows a frame synchronization circuit according to Conventional Example 4 (Japanese Unexamined Patent Application Publication No.
FIG. 2 is a diagram illustrating a configuration of a frame synchronization circuit disclosed as an embodiment in Japanese Patent Application Laid-Open No. 2-264743.

FIG. 11 is an operation timing chart of the circuit in FIG. 10;

FIG. 12 is a diagram showing a configuration of burst data for explaining a re-hunting operation of the frame synchronization circuit according to Conventional Example 4.

FIG. 13 is a diagram showing the operation of a frame synchronization circuit according to Conventional Example 4 as a simple flow.

FIG. 14 is a diagram showing the operation of the first embodiment of the present invention as a simple flow.

FIG. 15 is a diagram showing another operation of the first embodiment of the present invention as a simple flow.

[Explanation of symbols]

 Reference Signs List 1 frame synchronization pattern comparison circuit 2 code decoding circuit for error operation code information 3 frame synchronization protection circuit 4 frame counter 5 frame false synchronization determination circuit 6 auxiliary frame counter 7 backward protection circuit 8 synchronization pattern counting circuit 9 frame counting circuit 10 Gate circuit 11 Gate circuit 101 Received burst data RxD 21 Synchronization pulse 22 Mismatch information pulse 23 Mismatch pulse 24 Synchronization pulse 25 False synchronization generation pulse 29 Frame pulse 28 Multiple synchronization pattern information pulse 102 Clock 30 Main synchronization circuit 31 CRC error detection circuit 32 Pseudo-synchronous judgment circuit 33 Sub-synchronous circuit 34 Counting circuit often used for synchronous pattern counting circuit (2) 35 Counting circuit using frame counting circuit (1)

Claims (3)

(57) [Claims] A frame counter for counting a frame period at a certain phase, and determining whether or not the phase coincides with a phase of a synchronization pattern included in burst data transmitted at a constant period, in the frame synchronizing circuit which performs synchronization pull Shi pair to the burst data frame, in the course synchronization pull frame, the burst data
The burst only when the included synchronization pattern is detected.
Data to decode the pre-error detecting code added error detection code decoding to output a mismatch information pulse at the error occurrence
Circuit and a frame length <br/> counting circuit for counting phase free the same time length as one frame length for delivering the burst data at a fixed period, 1 frame length the frame length counter circuit has counted A synchronous pattern counting circuit that counts the number of synchronous patterns of the burst data within the time period, and counts the number of the non-coincidence information pulses.
Exceeded the fixed value and counted by the synchronous pattern counting circuit .
If the number of synchronization patterns of the burst data is 2 or more,
Frame erroneous synchronization that outputs erroneous synchronization occurrence pulse in some cases
A determination circuit; a synchronization pattern included in the burst data ;
The sub-unit that starts hunting when it receives the synchronization generation pulse
Frame synchronization circuit is characterized in that a synchronizing circuit. 2. The frame synchronization circuit according to claim 1, wherein the mismatch information packet counted by said frame error synchronization detection circuit is counted.
3. The frame synchronization circuit according to claim 1, wherein the constant value, which is a threshold value of the number of data, is a variable value. 3. The frame synchronization circuit according to claim 1, wherein the error detection code of the synchronization pattern includes a plurality of burst codes.
A frame synchronization circuit which distributes and arranges data and combines error detection codes over the plurality of burst data to perform error detection.