JP2943833B2 - Method of manufacturing semiconductor integrated circuit device having Schottky junction field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor integrated circuit device having a Schottky junction field effect transistor.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit device (hereinafter, referred to as a Schottky junction type field effect transistor) having a Schottky junction type field effect transistor described below.
(For simplicity, referred to as a semiconductor integrated circuit device).

[0003] That is, a semi-insulating semiconductor substrate made of a III-V compound semiconductor is prepared in advance, and then a first semiconductor having a required first pattern is formed on the semi-insulating semiconductor substrate.
Next, ions of the first n-type impurity from the main surface side of the semi-insulating semiconductor substrate with respect to the semi-insulating semiconductor substrate using the first mask layer as a mask are formed. By the injection treatment, the semi-insulating semiconductor substrate is
On the main surface side, a first n-type impurity ion-implanted region is formed, and then on the semi-insulating semiconductor substrate, at a position different from that on the first n-type impurity-ion implanted region.
Forming a second mask layer having a required second pattern, and then forming a second mask layer on the semi-insulating semiconductor substrate;
The ion implantation of the second n-type impurity from the main surface side of the semi-insulating semiconductor substrate is performed by using the mask layer as a mask. Forming an n-type impurity ion implanted region of
By the heat treatment on the semi-insulating semiconductor substrate, the first
And activating the second n-type impurity ion-implanted region, so that the first and second n-type impurity ion-implanted regions are formed in the semi-insulating semiconductor substrate from the first and second n-type impurity ion-implanted regions. A semiconductor region is formed respectively, and then the semiconductor region is formed on the semi-insulating semiconductor substrate.
First and second gate electrodes connected to each other to form first and second Schottky junctions on the type semiconductor region, the n-type semiconductor region for the first operation layer, and the first and second gate electrodes, respectively. A first source electrode and a first drain electrode that are ohmically connected to each other with the first gate electrode interposed therebetween; the second n-type semiconductor region for an operating layer; A second source electrode and a second drain electrode which are ohmically connected to each other at both positions sandwiching the two gate electrodes are formed.

The above is a method of manufacturing a conventionally proposed semiconductor integrated circuit device (hereinafter, referred to as a conventionally proposed method of manufacturing a first semiconductor integrated circuit device).

A semiconductor integrated circuit device manufactured by such a conventionally proposed method of manufacturing a first semiconductor integrated circuit device includes an n-type semiconductor region for a first operation layer and a first gate.
A first Schottky junction field effect transistor including a gate electrode, a first source electrode, and a first drain electrode; a second n-type semiconductor region for an operation layer; and a second gate.
A second Schottky junction field effect transistor having characteristics different from those of the first Schottky junction field effect transistor, the second Schottky junction field effect transistor being configured to include a gate electrode, a second source electrode, and a second drain electrode. It is clear that it has.

Therefore, the above-described first proposed method has been proposed.
According to the method of manufacturing a semiconductor integrated circuit device described above, a semiconductor integrated circuit device having first and second Schottky junction field effect transistors having mutually different characteristics can be easily manufactured.

Further, according to the above-mentioned method of manufacturing the first semiconductor integrated circuit device, the first and second n-type semiconductor regions for the operating layer are formed by forming n-type semiconductor regions into a semi-insulating semiconductor substrate.
Since the first and second n-type semiconductor regions for the operation layer are formed based on the implantation of the ions of the type impurity, the planar dimensions, the three-dimensional depth, and the n-type impurity What is formed as a substance whose concentration or the like is controlled to a desired value is that “(i) an n-type semiconductor layer is formed on a semi-insulating semiconductor substrate body, A semiconductor substrate having a configuration in which the n-type semiconductor layer is laminated, and then (ii) etching the n-type semiconductor layer from the n-type semiconductor layer by etching the semiconductor layer having the n-type. Having a pattern,
Forming first and second n-type semiconductor layers for an operation layer;
(Iii) a first and a second connection respectively on the semiconductor substrate so as to form first and second Schottky junctions on the first and second n-type semiconductor layers for the operation layer; The first source electrode and the first source electrode and the second source electrode, which are connected to each other at both positions with the first operating layer n-type semiconductor layer and the first gate electrode interposed therebetween. A second drain electrode, and a second source electrode and a second source electrode that are each connected ohmicly at both positions sandwiching the second n-type semiconductor layer for the operating layer and the second gate electrode. Forming the first and second operating layers in another conventional semiconductor integrated circuit device manufacturing method (hereinafter referred to as a conventionally proposed second semiconductor integrated circuit device manufacturing method). This is easier than forming an n-type semiconductor layer for use.

Therefore, the above-mentioned first proposed first method has been proposed.
According to the method of manufacturing a semiconductor integrated circuit device described above, the semiconductor integrated circuit device is characterized in that the first and second Schottky junction field effect transistors have desired characteristics. The semiconductor integrated circuit device can be easily manufactured as compared with the method of manufacturing a semiconductor integrated circuit device.

Conventionally, a method for manufacturing a semiconductor integrated circuit device described below has also been proposed.

That is, a semi-insulating semiconductor substrate made of a III-V compound semiconductor is prepared in advance, and then a first semiconductor having a required first pattern is formed on the semi-insulating semiconductor substrate.
Next, ions of the first n-type impurity from the main surface side of the semi-insulating semiconductor substrate with respect to the semi-insulating semiconductor substrate using the first mask layer as a mask are formed. By the injection treatment, the semi-insulating semiconductor substrate is
On the main surface side, a first n-type impurity ion-implanted region is formed, and then, on the semi-insulating semiconductor substrate, the first n-type impurity ion-implanted region corresponds to two different regions of the first n-type impurity ion-implanted region. Forming a second and a third mask layer having a required second pattern which does not mask the two regions, and then forms the second and third mask layers on the semi-insulating semiconductor substrate.
The ion implantation of the second n-type impurity from the main surface side of the semi-insulating semiconductor substrate is performed by using the mask layer as a mask. Forming two second and third n-type impurity ion-implanted regions in two mutually different regions extending into the two different regions of one n-type impurity ion-implanted region; The first, second and third n-type impurity ion-implanted regions are activated by heat treatment on the semi-insulating semiconductor substrate, and thus the first n-type impurity ion-implanted regions are formed in the semi-insulating semiconductor substrate. And forming the n-type semiconductor region for the operation layer from
Forming an n-type semiconductor region for a source electrode and an n-type semiconductor region for a drain electrode from the n-type impurity ion implanted region, and then forming the n-type semiconductor region for the operation layer on the semi-insulating semiconductor substrate. A gate electrode connected to form a Schottky junction on the region, and a source electrode connected to the n-type semiconductor region for the source electrode and the n-type semiconductor region for the drain electrode, respectively. Forming a source electrode and a drain electrode;

The above is a method of manufacturing a conventionally proposed semiconductor integrated circuit device (hereinafter, referred to as a conventionally proposed method of manufacturing a third semiconductor integrated circuit device).

A semiconductor integrated circuit device manufactured by such a conventionally proposed third semiconductor integrated circuit device manufacturing method comprises an n-type semiconductor region for an operation layer, an n-type semiconductor region for a source electrode, and a drain. An n-type semiconductor region for an electrode;
A Schottky junction field effect transistor including a source electrode, a source electrode, and a drain electrode, and in this case, an n-type semiconductor region for a source electrode and an n-type semiconductor region for a drain electrode. Can be formed as having a sufficiently high n-type impurity concentration.

Therefore, according to the above-described conventional method for manufacturing a semiconductor integrated circuit device, the semiconductor integrated circuit device includes a Schottky junction field effect transistor having a low source electrode resistance and a low drain electrode resistance.
It can be easily manufactured.

Further, according to the above-mentioned third conventional method for manufacturing a semiconductor integrated circuit device, the n-type semiconductor region for the operating layer, the n-type semiconductor region for the source electrode, and the n-type semiconductor region for the drain electrode are provided. With the previously proposed first
In accordance with the method of manufacturing a semiconductor integrated circuit device described above, the semiconductor integrated circuit device is formed based on a process of implanting ions of an n-type impurity into a semi-insulating semiconductor substrate. The n-type semiconductor region for the source electrode and the n-type semiconductor region for the drain electrode are formed in a planar dimension and a three-dimensional shape according to the above-described method of manufacturing the first conventionally proposed semiconductor integrated circuit device. What is formed as a material whose depth, n-type impurity concentration, and the like are controlled to desired values is “(i) a configuration in which an n-type semiconductor layer is stacked on a semi-insulating semiconductor substrate body. Obtaining a semiconductor substrate, then (i
i) forming an n-type semiconductor layer for an operation layer having a desired pattern from the semiconductor layer having the n-type by etching the semiconductor layer having the n-type;
(Iii) An n-type semiconductor region for a source electrode and an n-type semiconductor region for a drain electrode into which an n-type impurity is introduced at a high concentration are provided at two different positions in the n-type semiconductor layer for the operation layer. And (iv) a gate electrode connected to the semiconductor substrate so as to form a Schottky junction at a position on the n-type semiconductor layer for the operating layer, and Forming a source electrode and a drain electrode that are in ohmic connection with the n-type semiconductor region for drain and the n-type semiconductor region for drain electrode, respectively. In the case of forming the n-type semiconductor layer for the operating layer, the n-type semiconductor region for the source electrode, and the n-type semiconductor region for the drain electrode in the conventionally proposed method of manufacturing a fourth semiconductor integrated circuit device). And, it is easy.

Therefore, the above-described third conventionally proposed method is used.
According to the method of manufacturing a semiconductor integrated circuit device described above, the semiconductor integrated circuit device is characterized in that the Schottky junction field effect transistor has desired characteristics. It can be easily manufactured as compared with the manufacturing method.

[0016]

SUMMARY OF THE INVENTION In a semiconductor integrated circuit device manufactured by the above-mentioned conventionally proposed method of manufacturing a first semiconductor integrated circuit device, the first and second Schottky junction field effect transistors are of the first type. Since the first and second n-type semiconductor regions for the operation layer are formed in the semi-insulating semiconductor substrate, the n-type semiconductor region for the operation layer has the same material as the semi-insulating semiconductor substrate. . On the other hand, a semi-insulating semiconductor substrate tends to contain a non-negligible amount of undesirable impurities.

[0017] From the above, the first conventionally proposed first.
According to the method of manufacturing a semiconductor integrated circuit device, the semiconductor integrated circuit device is characterized in that the first and second Schottky junction field effect transistors have characteristics dependent on the material of the semi-insulating semiconductor substrate, and the characteristics are Does not have the expected characteristics,
However, it has the disadvantage that it can only be formed.

Further, in the semiconductor integrated circuit device manufactured by the above-mentioned conventionally proposed method of manufacturing the first semiconductor integrated circuit device, the first and second Schottky junction type field effect transistors are composed of the first and second semiconductor integrated circuit devices. The n-type semiconductor region for an operating layer partially forms the surface of the semi-insulating semiconductor substrate, and therefore, the n-type semiconductor region for the first and second operating layers and the surface of the semi-insulating semiconductor substrate Between the first and second n-type semiconductor layers for the operation layer, there is no layer formed between the first and second n-type semiconductor layers for the operation layer, which acts as a barrier to the surface of the semi-insulating semiconductor substrate. . For this reason,
When a defect layer is formed on the surface of the semi-insulating semiconductor substrate at the time of manufacturing the semiconductor integrated circuit device or after the semiconductor integrated circuit device is manufactured, the n-type first and second operating layers are used. A layer between the semiconductor region and the defect layer on the surface of the semi-insulating semiconductor substrate, which serves as a barrier against electrons of the first and second n-type semiconductor regions for the operation layer going to the defect layer; Is not interposed at all, so that the electrons in the first and second n-type semiconductor regions for the operation layer easily reach the defect layer on the surface of the semi-insulating semiconductor substrate, and the
When the device operates as a Schottky junction type field effect transistor, the noise is caused by a defect layer.

From the above, in the case of the above-described conventional method for manufacturing a semiconductor integrated circuit device, the semiconductor integrated circuit device is manufactured by forming a defect layer on the surface of a semi-insulating semiconductor substrate,
If they are formed, they can be manufactured only when they operate as the first and second Schottky field-effect transistors because they cause non-negligible noise due to the defective layer. Had.

According to the above-mentioned third method of manufacturing a semiconductor integrated circuit device, a Schottky junction field-effect transistor is manufactured in the semiconductor integrated circuit device manufactured by the method. According to the semiconductor integrated circuit device manufactured by the method of manufacturing the first semiconductor integrated circuit device, the n-type semiconductor region for the operation layer has a configuration formed in a semi-insulating semiconductor substrate. Although omitted, the Schottky junction field-effect transistor has a characteristic depending on the material of the semi-insulating semiconductor substrate according to the above-described method of manufacturing the first semiconductor integrated circuit device, and In addition, it has a drawback that it can be produced only as a material having no desired characteristics.

Further, the above-mentioned third conventionally proposed method is used.
According to the method of manufacturing a semiconductor integrated circuit device, in the semiconductor integrated circuit device manufactured by the method, the Schottky junction type field effect transistor is manufactured by the above-described conventionally proposed method of manufacturing the first semiconductor integrated circuit device. As in the case of a semiconductor integrated circuit device, between the n-type semiconductor region for the operating layer and the surface of the semi-insulating semiconductor substrate, electrons in the semiconductor region for the operating layer are directed toward the surface of the semi-insulating semiconductor substrate body. On the other hand, since a layer serving as a barrier is not formed, a detailed description thereof will be omitted, but according to the above-described method of manufacturing the first semiconductor integrated circuit device conventionally proposed,
If a Schottky junction field-effect transistor has a defect layer formed or formed on the surface of a semi-insulating semiconductor substrate, when the Schottky junction field-effect transistor operates, non-negligible noise due to the defect layer is generated. Can only be produced as it occurs,
Had the disadvantage that

Thus, the present invention is free from the disadvantages mentioned above,
It is intended to propose a method of manufacturing a new semiconductor integrated circuit device.

[0023]

A method of manufacturing a semiconductor integrated circuit device according to the first invention of the present application includes the steps of (i) first III-
On a semi-insulating semiconductor substrate body made of a group V compound semiconductor,
(A) a semi-insulating semiconductor layer made of a second III-V compound semiconductor, and a third III- semiconductor layer having a wider energy band gap than the second III-V compound semiconductor.
A semi-insulating barrier layer made of a group V compound semiconductor, or (b) a semi-insulating semiconductor layer made of a second III-V compound semiconductor, and wider than the second III-V compound semiconductor. Third III- having energy band gap
A semi-insulating barrier layer comprising a group V compound semiconductor;
A semi-insulating protective layer made of a fourth III-V compound semiconductor having an energy band gap narrower than that of the IV compound semiconductor; (A) the semi-insulating semiconductor layer and the semi-insulating barrier layer, or (b) the semi-insulating semiconductor layer, the semi-insulating barrier layer, and the semi-insulating protective layer in that order. Obtaining a semiconductor substrate having a stacked configuration; and (ii) forming a semiconductor substrate on the semiconductor substrate.
A step of forming a first mask layer having a required first pattern; and (iii) the semi-insulating semiconductor substrate body side with respect to the semiconductor substrate using the first mask layer as a mask. By implanting ions of the first n-type impurity from the opposite side, a predetermined depth is provided in the semiconductor substrate from the semi-insulating barrier layer side of the semi-insulating semiconductor layer to the semi-insulating semiconductor substrate body side. Forming a first n-type impurity ion-implanted region in the removed region;
v) After or before the step of forming the first n-type impurity ion-implanted region, the first n-type impurity ion-implanted region is formed on the semiconductor substrate.
Forming a second mask layer having a required second pattern at a position different from that on the n-type impurity ion-implanted region, and (v) forming the second mask layer on the semiconductor substrate. The semi-insulating barrier layer of the semi-insulating semiconductor layer is formed in the semiconductor substrate by implanting ions of a second n-type impurity from a side opposite to the semi-insulating semiconductor substrate body side as a mask. Forming a second n-type impurity ion-implanted region in a region having a required depth from the side to the semi-insulating semiconductor substrate body side;
i) after the step of forming the first and second n-type impurity ion-implanted regions, the first and second n-type impurity ion-implanted regions are activated by a heat treatment on the semiconductor substrate; In a region of the semi-insulating semiconductor layer, which is only a required depth from the semi-insulating barrier layer side of the semi-insulating semiconductor layer, the first n-type impurity ion-implanted region has a first depth. N for operation layer
Forming a second semiconductor layer and forming a second operating layer n-type semiconductor region from the second n-type impurity ion implanted region, and (vii) forming the semi-insulating barrier layer on the semiconductor substrate. Alternatively, the semi-insulating protective layer and the first
First and second gate electrodes connected to each other to form first and second Schottky junctions on the n-type semiconductor region for the second operating layer and the first gate electrode, respectively;
A first source electrode and a first drain electrode that are ohmically connected to both the n-type semiconductor region for an operation layer and the first gate electrode at both positions with the second gate electrode interposed therebetween;
Forming an n-type semiconductor region for an operation layer and a second source electrode and a second drain electrode which are ohmically connected to each other at both positions sandwiching the second gate electrode. And

The method of manufacturing a semiconductor integrated circuit device according to the second invention of the present application includes the steps of: (i) forming a (a) second II on a semi-insulating semiconductor substrate body made of a first III-V compound semiconductor;
A semi-insulating semiconductor layer made of an IV group compound semiconductor, and a semi-insulating barrier layer made of a third group III-V compound semiconductor having a wider energy band gap than the second group III-V compound semiconductor Or (b) the second II
A semi-insulating semiconductor layer made of an IV group compound semiconductor, and a semi-insulating barrier layer made of a third group III-V compound semiconductor having a wider energy band gap than the second group III-V compound semiconductor And a semi-insulating protective layer made of a fourth III-V compound semiconductor having an energy band gap narrower than that of the III-V compound semiconductor. (A) the semi-insulating semiconductor layer and the semi-insulating barrier layer, or (b) the semi-insulating semiconductor layer, the semi-insulating barrier layer, and the semi-insulating protective layer on the substrate body. (Ii) forming a first mask layer having a required first pattern on the semiconductor substrate; and (ii) forming a first mask layer having a required first pattern on the semiconductor substrate.
i) ion implantation of a first n-type impurity into the semiconductor substrate from the side opposite to the semi-insulating semiconductor substrate body using the first mask layer as a mask;
In the semiconductor substrate, a first n-type impurity ion-implanted region is formed in a region of a required depth from the semi-insulating barrier layer side of the semi-insulating semiconductor layer to the semi-insulating semiconductor substrate body side. Forming; and (iv) the first n
After or before the step of forming the impurity ion-implanted region, two regions corresponding to the two different regions of the first n-type impurity ion-implanted region are not masked on the semiconductor substrate. Forming a second mask layer having a required second pattern, and (v) forming a second mask layer on the semi-insulating semiconductor substrate body side with respect to the semiconductor substrate using the second mask layer as a mask. Is injected into the semiconductor substrate from the opposite side from the semi-insulating barrier layer side of the semi-insulating semiconductor layer to the semi-insulating semiconductor substrate body side by ion implantation of a second n-type impurity. The second and third n-type impurity ion-implanted regions in two different regions extending only into two different regions of the first n-type impurity ion-implanted region, each having a depth only. To And (vi) forming the first and second n-type impurity ion-implanted regions, and then heat-treating the semiconductor substrate to form the first, second, and third n-type impurity ions. Activating the implantation region, and thus, within the semiconductor substrate, in a region taken from the semi-insulating barrier layer side of the semi-insulating semiconductor layer by a required depth to the semi-insulating semiconductor substrate main body,
Forming an n-type semiconductor region for an operating layer from the n-type impurity ion-implanted region, and forming an n-type semiconductor region for a source electrode and an n-type semiconductor for a drain electrode from the second and third n-type impurity ion-implanted regions. Forming a region, and (vii) forming a Schottky junction on the semiconductor substrate, on the semi-insulating semi-insulating barrier layer or the semi-insulating protective layer and the n-type semiconductor region for the operating layer, respectively. The gate electrode and the source electrode and the drain electrode that are in ohmic connection with the n-type semiconductor region for the source electrode and the n-type semiconductor region for the drain electrode, respectively, are connected as described above. Forming.

[0025]

The semiconductor integrated circuit device manufactured by the method for manufacturing a semiconductor integrated circuit device according to the first aspect of the present invention comprises an n-type semiconductor region for a first operation layer, a first gate electrode, and a first gate electrode. A first Schottky junction field effect transistor including a source electrode and a first drain electrode, a second n-type semiconductor region for an operation layer, a second gate electrode, and a second gate electrode; It is apparent that the semiconductor device has a second Schottky junction field effect transistor having characteristics different from those of the first Schottky junction field effect transistor, the source Schottky junction field effect transistor including a source electrode and a second drain electrode. .

Therefore, according to the method for manufacturing a semiconductor integrated circuit device according to the first invention of the present application, the semiconductor integrated circuit device is
It can be easily manufactured as having the first and second Schottky field effect transistors having different characteristics from each other.

Further, according to the method of manufacturing a semiconductor integrated circuit device according to the first invention of the present application, the first and second semiconductor integrated circuit devices are manufactured in the same manner as in the above-mentioned conventionally proposed method of manufacturing the first semiconductor integrated circuit device. The first and second n-type semiconductor regions for the operating layer, which constitute the Schottky junction field effect transistor, respectively, are formed based on ion implantation of n-type impurities into the semi-insulating semiconductor layer. Therefore, the first and second n-type semiconductor regions for the operation layer are formed so that the planar dimensions, the three-dimensional depth, the n-type impurity concentration, and the like are controlled to desired values. However, the method is easier than the above-described method of manufacturing the second conventional semiconductor integrated circuit device.

Therefore, according to the method for manufacturing a semiconductor integrated circuit device according to the first invention of the present application, the semiconductor integrated circuit device is
Assuming that the first and second Schottky field-effect transistors having mutually different characteristics have desired characteristics, the first and second Schottky field effect transistors have the same characteristics as in the case of the above-mentioned conventionally proposed method of manufacturing the first semiconductor integrated circuit device. It can be easily manufactured as compared with the case of the above-mentioned other conventionally proposed second semiconductor integrated circuit device manufacturing method.

Further, in the semiconductor integrated circuit device manufactured by the method for manufacturing a semiconductor integrated circuit device according to the first invention of the present application, the first and second Schottky junction type field effect transistors include first and second operation layers. The n-type semiconductor region for use is formed in a semi-insulating semiconductor layer formed on a semi-insulating semiconductor substrate main body.
In this case, the semi-insulating semiconductor layer can be easily formed on the assumption that the semi-insulating semiconductor layer contains a much smaller amount of undesired impurities than the semi-insulating semiconductor substrate body. The layers, and thus the first and second n-type semiconductor regions for the active layer, can be formed of a different material than the semi-insulating semiconductor substrate body.

As described above, according to the method for manufacturing a semiconductor integrated circuit device according to the first invention of the present application, the semiconductor integrated circuit device is formed by using the first and second Schottky junction type field effect transistors with a semi-insulating semiconductor substrate. First and second in the body
It can be easily manufactured as having characteristics different from those in the case where the semiconductor layer for an operation layer is formed, and having excellent characteristics.

Further, in the semiconductor integrated circuit device manufactured by the method for manufacturing a semiconductor integrated circuit device according to the first invention of the present application, the first and second Schottky junction type field effect transistors include first and second operation layers. The n-type semiconductor region for semiconductor does not form the surface of the semiconductor substrate, and a semi-insulating barrier layer is provided between each of the first and second n-type semiconductor regions for operation layer and the surface of the semiconductor substrate. Or a configuration in which a semi-insulating barrier layer and a semi-insulating protective layer are interposed. For this reason, even if the defect layer is formed on the surface of the semiconductor substrate at the time of manufacturing the semiconductor integrated circuit device or formed after the manufacturing of the semiconductor integrated circuit device, the first and second operating layer n A layer that acts as a barrier between electrons of the first and second n-type semiconductor regions for an operation layer directed toward the defect layer between each of the type semiconductor regions and the defect layer; Electrons in the first and second n-type semiconductor regions for the operation layer hardly reach the defect layer on the surface of the semiconductor substrate, and therefore, when the first and second Schottky field-effect transistors operate, they have defects. The generation of noise due to layers can be effectively avoided.

As described above, according to the method of manufacturing a semiconductor integrated circuit device according to the first aspect of the present invention, a semiconductor integrated circuit device can be formed even if a defect layer is formed on the surface of a semiconductor substrate. In addition, it can be easily manufactured that the first and second Schottky junction field effect transistors do not generate non-negligible noise due to a defective layer during operation.

Further, in the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the first invention of the present application, the first and second Schottky field effect transistors are formed on a semiconductor substrate by the first and second Schottky junction field effect transistors. A second gate electrode is formed on the semi-insulating barrier layer or the semi-insulating protective layer, respectively, so as to form first and second Schottky junctions therewith; Therefore, the first gate between the first and second gate electrodes and the semi-insulating barrier layer or the semi-insulating protective layer, respectively.
And the second Schottky junction forms a barrier for electrons from the side of the first and second gate electrodes to the side of the first and second n-type semiconductor regions for the operating layer, respectively. Because of the presence of the insulating barrier layer, it also has a semi-insulating protective layer, and it is formed of a material that has a lower conduction band energy than the material of the semi-insulating barrier layer. However, if the thickness is not so large, the energy of the conduction band bottom on the surface of the semi-insulating protective layer, that is, the surface of the semiconductor substrate, is reduced to the energy at or near the conduction band bottom of the semi-insulating barrier layer. To lift,
The height of the barrier formed by the first and second Schottky junctions from the side of the first and second gate electrodes to the side of the first and second n-type semiconductor regions for the operation layer is different from that of the semi-insulating barrier layer. It is configured to be higher than when it is not provided. For this reason, when the first and second Schottky junction field effect transistors are used as binary logic circuit elements (on / off elements), the logic amplitude is increased as compared with the case without a semi-insulating barrier layer. Therefore, the operation margin as a binary logic circuit element can be increased.

As described above, according to the method for manufacturing a semiconductor integrated circuit device according to the first aspect of the present invention, the semiconductor integrated circuit device is provided with the first and second Schottky junction field effect transistors having a high operation margin. It can be easily manufactured as having a function as a binary logic circuit element.

The semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the first invention of the present application is formed by first and second Schottky junction field effect transistors on a semi-insulating barrier layer. When manufactured as having an insulating protective layer, the first and second Schottky junction field effect transistors are configured such that the first and second gate electrodes form first and second Schottky junctions, respectively. And a semi-insulating protective layer connected to the substrate. Therefore, the first and second gate electrodes and the semi-insulating protective layer are connected to each other when the first and second Schottky junction field effect transistors are applied with relatively high heat. 2 is a material having a relationship that the element of the material constituting the gate electrode and the element of the material constituting the semi-insulating protective layer do not contain an element which easily reacts with each other. With this configuration, when a relatively high heat is applied to the first and second Schottky field-effect transistors, the semi-insulating protective layer is formed with the element of the material forming the gate electrode. It is possible to effectively prevent the elements of the material being used from reacting with each other. In this case, since the semiconductor device has the semi-insulating protective layer, if the thickness of the semi-insulating protective layer is increased as long as the effect of increasing the operation margin as the above-described binary logic circuit element is not lost, First
Even if relatively high heat is applied to the first and second Schottky field effect transistors,
The first electrode and the semi-insulating barrier layer form the first and second gate electrodes when relatively high heat is applied to the first and second Schottky field effect transistors. The first and second materials are required to be composed of a material in which the element of the material and the element of the material constituting the semi-insulating barrier layer contain an element which easily reacts with each other. Gay
It is possible to effectively avoid that the element of the material constituting the gate electrode and the element of the material constituting the semi-insulating barrier layer react with each other via the semi-insulating protective layer.

Therefore, according to the method for manufacturing a semiconductor integrated circuit device according to the first invention of the present application, the first and second Schottky field effect transistors in the semiconductor integrated circuit device are formed on the semi-insulating barrier layer by the first method. And when the second and second gate electrodes are formed as having a semi-insulating protective layer connected to form first and second Schottky junctions, respectively. The semi-insulating barrier layer is an element of a material constituting the first and second gate electrodes when relatively high heat is applied to the first and second Schottky field effect transistors. Although the semiconductor integrated circuit device is required to be composed of the first and the second semiconductor integrated circuit devices, Second Schottky junction type Effect transistors, even if a relatively high heat is applied to them, as operating at the desired characteristics can be easily manufactured.

A semiconductor integrated circuit device manufactured by the method for manufacturing a semiconductor integrated circuit device according to the second invention of the present application is:
Schottky junction type field effect including n-type semiconductor region for operation layer, n-type semiconductor region for source electrode, n-type semiconductor region for drain electrode, gate electrode, source electrode and drain electrode Having a transistor, and in this case,
It is apparent that the n-type semiconductor region for the source electrode and the n-type semiconductor region for the drain electrode can be formed as having a sufficiently high n-type impurity concentration.

Therefore, according to the method of manufacturing a semiconductor integrated circuit device according to the second invention of the present application, the semiconductor integrated circuit device is
It can be easily manufactured as having a Schottky junction type field effect transistor having low source electrode resistance and low drain electrode resistance.

Further, according to the method of manufacturing a semiconductor integrated circuit device according to the second invention of the present application, a Schottky junction field effect transistor can be formed according to the method of manufacturing the semiconductor integrated circuit device of the first invention of the present application. The n-type semiconductor region for the operating layer, the n-type semiconductor region for the source electrode, and the n-type semiconductor region for the drain electrode to be formed are formed based on the ion implantation of n-type impurities into the semi-insulating semiconductor layer. It is formed.

For this reason, although a detailed description is omitted, according to the method of manufacturing a semiconductor integrated circuit device according to the second invention of the present application, the semiconductor integrated circuit device is manufactured by the method of manufacturing a semiconductor integrated circuit device of the first invention of the present application. In accordance with the case, the Schottky junction field-effect transistor having desired characteristics can be easily manufactured as compared with the above-described fourth conventional method of manufacturing a semiconductor integrated circuit device. it can.

Further, in the semiconductor integrated circuit device manufactured by the method for manufacturing a semiconductor integrated circuit device according to the second invention of the present application, the Schottky junction field effect transistor has an n-type semiconductor region for an operation layer which is the first type of the present invention. A semi-insulating semiconductor formed on a semi-insulating semiconductor substrate body according to the first and second Schottky junction type field effect transistors in a semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention. It is configured to be formed in a layer.

For this reason, although a detailed description is omitted, according to the method for manufacturing a semiconductor integrated circuit device according to the second invention of the present application, the semiconductor integrated circuit device is formed by a Schottky junction field effect transistor. According to the method of manufacturing a semiconductor integrated circuit device according to the above, the semiconductor device has characteristics different from those in the case where the semiconductor region for the operating layer is formed in the semi-insulating semiconductor substrate body, and the characteristics are excellent. , Can be easily formed.

In a semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the second invention of the present application, the Schottky junction field effect transistor is manufactured by the method of manufacturing a semiconductor integrated circuit device of the first invention of the present application. First in a semiconductor integrated circuit device to be manufactured
And the second Schottky field-effect transistor, the n-type semiconductor region for the operation layer does not form the surface of the semiconductor substrate, and the n-type semiconductor region for the operation layer and the surface of the semiconductor substrate A semi-insulating barrier layer or a semi-insulating barrier layer and a semi-insulating protective layer are interposed between them.

For this reason, although a detailed description is omitted, according to the method for manufacturing a semiconductor integrated circuit device according to the second invention of the present application, the semiconductor integrated circuit device is manufactured by the method for manufacturing a semiconductor integrated circuit device according to the first invention of the present application. In accordance with the case, even if a defect layer is formed on the surface of the semiconductor substrate, or even if it is formed, at the time of operation of the Schottky junction type field effect transistor,
In addition, it can be easily manufactured because there is no non-negligible noise caused by a defective layer.

Further, in the semiconductor integrated circuit device manufactured by the method for manufacturing a semiconductor integrated circuit device according to the second invention of the present application, the Schottky junction field effect transistor is manufactured by the method for manufacturing a semiconductor integrated circuit device according to the first invention of the present application. As in the case of the first and second Schottky field-effect transistors in the semiconductor integrated circuit device to be manufactured, the gate electrode is formed on a semi-insulating barrier layer or a semi-insulating protective layer on a semiconductor substrate. Are formed so as to form a Schottky junction between the gate electrode and the Schottky junction between the gate electrode and the semi-insulating barrier layer or the semi-insulating protective layer. , Gay
A barrier for electrons as viewed from the side of the n-type semiconductor region for the active layer from the electrode side, but because of the presence of a semi-insulating barrier layer for electrons, it also has a semi-insulating protective layer,
And, even if it is formed of a material having a lower conduction band energy than the material of the semi-insulating barrier layer, if the thickness is not so large, the surface of the semi-insulating protective layer Therefore, the energy at the bottom of the conduction band on the surface of the semiconductor substrate is lifted to the energy at or near the bottom of the conduction band of the semi-insulating barrier layer. The barrier height due to the Schottky junction is higher than that without the semi-insulating barrier layer.

For this reason, although a detailed description is omitted, according to the method for manufacturing a semiconductor integrated circuit device according to the second invention of the present application, the semiconductor integrated circuit device is formed by using a Schottky junction type field effect transistor. According to the method of manufacturing a semiconductor integrated circuit device described above, the semiconductor integrated circuit device can be easily manufactured as having a function as a binary logic circuit element having a high operation margin.

In the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the second invention of the present application, a Schottky junction field effect transistor has a semi-insulating protective layer on a semi-insulating barrier layer. In the case where the Schottky junction field effect transistor is manufactured as a semiconductor device, the Schottky junction field effect transistor can be manufactured by the same method as the first and second Schottky junction field effect transistors manufactured by the method of manufacturing a semiconductor integrated circuit device according to the first invention. The semiconductor device has a semi-insulating protective layer connected so as to form a Schottky junction.

For this reason, although detailed description is omitted, according to the method of manufacturing the semiconductor integrated circuit device according to the second invention of the present application, the semiconductor integrated circuit device is manufactured according to the method of manufacturing the semiconductor integrated circuit device of the first invention of the present application. In the case where a Schottky junction field effect transistor in an integrated circuit device is formed as having a semi-insulating protective layer on which a gate electrode is connected to form a Schottky junction on a semi-insulating barrier layer, The gate electrode and the semi-insulating barrier layer form the semi-insulating barrier layer with the element of the material constituting the gate electrode when relatively high heat is applied to the Schottky junction field effect transistor. Semiconductor integrated circuit devices can be converted to Schottky junction type field effect transistors even if it is unavoidable that the semiconductor integrated circuit device is composed of materials that contain elements that easily react with each other. Star is, even if a relatively high heat is applied to them, as operating at the desired characteristics can be easily manufactured.

[0049]

Embodiment 1 Next, a first embodiment of a method of manufacturing a semiconductor integrated circuit device according to the present invention will be described with reference to FIGS.

In the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the first and second Schottky junction field effect transistors having mutually different characteristics are formed by the following sequential steps. To manufacture a semiconductor integrated circuit device having the same.

That is, a semi-insulating semiconductor substrate main body 1 made of, for example, GaAs is prepared as a first semi-insulating III-V compound semiconductor (FIG. 1A).

Then, on the semi-insulating semiconductor substrate body 1, a second semi-insulating III-V having a relatively large thickness is formed.
A semi-insulating semiconductor layer 2 made of, for example, GaAs as a group III compound semiconductor; and a third semi-insulating semiconductor layer 2 having a wider energy band gap than that of the second semi-insulating III-V compound semiconductor and having a thickness of, for example, 100 A. A semi-insulating barrier layer 3 made of, for example, InGaP as a semi-insulating group III-V compound semiconductor is formed in that order by a known epitaxial growth method. A semiconductor substrate 4 having a configuration in which the insulating semiconductor layer 2 and the semi-insulating barrier layer 3 are stacked in that order is obtained (FIG. 1B).

Next, a first mask layer 5A having a required first pattern is formed on the semiconductor substrate 4 by various methods known per se (FIG. 1C).

Next, while the semiconductor substrate 4 is masked by the first mask layer 5A, ions 6A of, for example, Si as n-type impurities are applied from the semi-insulating barrier layer 3 side to, for example, 25 KeV. Accelerating voltage, for example 1.5 ×
By performing an implantation process at an implantation amount of 10 ¹³ / cm ² , a required depth from the semi-insulating barrier layer 3 side of the semi-insulating semiconductor layer 2 to the semi-insulating semiconductor substrate body 1 side in the semiconductor substrate 4 A first n-type impurity ion implanted region 7A is formed in the region that has been removed (FIG. 1D).

Next, the first mask layer 5A is removed from the semiconductor substrate 4 by various methods known per se (FIG. 2E).

Next, a second mask layer 5B having a required second pattern is formed on the semiconductor substrate 4 at a position different from that on the first n-type impurity ion implantation region 7A. It is formed by various known methods (FIG. 2F).

Next, while the semiconductor substrate 4 is masked by the second mask layer 5B, for example, Si ions 6B as n-type impurities are applied from the semi-insulating barrier layer 3 side to the above-described ions. Higher than 6A, for example, 30K
The accelerating voltage of eV, which is the same as the ion 6A described above, for example, 1.
By performing an implantation process at an implantation amount of 5 × 10 ¹³ / cm ² , the first semi-insulating semiconductor layer 2 is moved from the semi-insulating barrier layer 3 side to the semi-insulating semiconductor substrate main body 1 side in the semiconductor substrate 4.
A second n-type impurity ion implantation region 7B is formed in a region having a required depth which is deeper than that of the n-type impurity ion implantation region 7A (FIG. 2G).

Next, the second mask layer 5B is removed from the semiconductor substrate 4 by various methods known per se (FIG. 2H).

Next, a heat treatment protection layer 8 made of, for example, SiN and having a thickness of, for example, 1500 A is formed on the semiconductor substrate 4 by various methods known per se (FIG. 3I).

Next, for example, 80
The first and second n-type impurity ion implanted regions 7A are heat-treated at a temperature of 0 ° C., for example, by heating for 10 minutes.
And 7B are activated, and therefore, in the semiconductor substrate 4, in a region taken only a required depth from the semi-insulating barrier layer 3 side of the semi-insulating semiconductor substrate main body 1 to the semi-insulating semiconductor substrate main body 1 side, 1 from the n-type impurity ion implantation region 7A.
And the second n-type semiconductor region for operating layer 9B is formed from the second n-type impurity ion implanted region 7B (FIG. 3J).

Next, after removing the heat treatment protective layer 8 from the semiconductor substrate 4, the semi-insulating barrier layer 3 and the first and second n-type semiconductor regions 9 A for the operating layer and 9
B and the first and second Schottky junctions 1 respectively
First and second gate electrode layers 11 made of, for example, WSiN, which are connected to form 0A and 10B, respectively.
A and 11B, and the first which is ohmic-connected through the semi-insulating barrier layer 3 at both positions sandwiching the first operating layer n-type semiconductor region 9A and the first gate electrode 11A. Source electrode 12A and first drain electrode 13
A, the second operating layer n-type semiconductor region 9B and the second gate.
The second source electrode 12B and the second drain electrode 13B, which are ohmically connected to each other through the semi-insulating barrier layer 3 at both positions with the gate electrode 11B interposed therebetween, are connected to various publicly known per se. (FIG. 3)
K). In FIG. 3K, reference numeral 14 denotes a protective layer formed of an insulating material on the semiconductor substrate 4.

The first embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention has been described above.

A semiconductor integrated circuit device (FIG. 3K) manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3 has an n-type semiconductor region 9A for a first operation layer and a first gate. Electrode 11A and the first source electrode 12A and the first
A first Schottky field effect transistor MA including the first drain electrode 13A, a second n-type semiconductor region 9B for an operation layer, a second gate electrode 11B, and a second source. It is obvious that the second Schottky junction field effect transistor MB includes the electrode 12B and the second drain electrode 13B and has different characteristics from the first Schottky junction field effect transistor MA. is there.

Therefore, according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the semiconductor integrated circuit device is provided with the first and second Schottky junction field effect transistors MA having different characteristics from each other. And MBs can be easily manufactured.

Further, according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the first and the second methods of manufacturing the semiconductor integrated circuit device according to the above-described conventionally proposed first method are used. The first and second operating layer n-type semiconductor regions 9A and 9B constituting the second Schottky junction field effect transistors MA and MB, respectively, are converted into the semi-insulating semiconductor layer 2 by the ion 6A of the n-type impurity. Since the first and second n-type semiconductor regions for operation layer 9A and 9B are formed based on the implantation process, the planar dimensions, three-dimensional depth, n-type impurity concentration, etc. Is easily controlled as compared with the above-described other conventional method of manufacturing the second semiconductor integrated circuit device.

Therefore, according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the semiconductor integrated circuit device is provided with the first and second Schottky junction field effect transistors MA having different characteristics. And MB are both
Similar to the above-described method of manufacturing the first conventionally proposed semiconductor integrated circuit device, it is assumed that the second semiconductor integrated circuit device has the desired characteristics. It can be easily manufactured as compared with.

Further, in the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the first and second Schottky junction field effect transistors MA and MB include And the second operating layer n-type semiconductor regions 9A and 9B are formed in the semi-insulating semiconductor layer 2 formed on the semi-insulating semiconductor substrate body 1. And in this case,
The semi-insulating semiconductor layer 2 can be easily formed on the assumption that the semi-insulating semiconductor layer 2 contains much less undesirable impurities than the semi-insulating semiconductor substrate body 1. It can be formed of a material different from the semi-insulating semiconductor substrate body 1.

As described above, according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the semiconductor integrated circuit device is formed by the first and second Schottky junction field effect transistors MA and MB. First and second semiconductor layers 9A and 9B for an operation layer in a semi-insulating semiconductor substrate body 1.
Can be easily formed as having different characteristics from those in the case of forming, and having excellent characteristics.

In the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the first and second Schottky junction field effect transistors MA and MB include And the second operating layer n-type semiconductor regions 9A and 9B do not form the surface of the semiconductor substrate 4, and the first and second n-type semiconductor regions 9A and 9B for operating layer and the semiconductor substrate 4 respectively. Has a configuration in which a semi-insulating barrier layer 3 is interposed therebetween. Therefore, on the surface of the semiconductor substrate 4,
Even if the defective layer is formed at the time of manufacturing the semiconductor integrated circuit device or formed after the manufacturing of the semiconductor integrated circuit device, the first and second n-type semiconductor regions 9A and 9 for the operation layer are formed.
B, between each of the B and the defect layer, a layer that acts as a barrier for the electrons of the first and second n-type semiconductor regions 9A and 9B for the operation layer toward the defect layer is interposed. First
In addition, the electrons of the n-type semiconductor regions 9A and 9B for the second operation layer hardly reach the defect layer on the surface of the semiconductor substrate 4, and therefore, the operation of the first and second Schottky junction field effect transistors MA and MB Sometimes it can be effectively avoided that they are noisy due to defective layers.

As described above, according to the method for manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, even if a defect layer is formed on the surface of the semiconductor substrate 4, Also, even when formed, the first and second Schottky junction field effect transistors MA and MB operate during operation.
They can be easily manufactured, as they do not produce non-negligible noise due to defective layers.

Further, in the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the first and second Schottky junction field effect transistors MA and MB are formed on a semiconductor substrate. 4, first and second gate electrodes 11A and 11B are connected to the semi-insulating barrier layer 3 to form first and second Schottky junctions 10A and 10B therebetween, respectively. Is formed, and therefore,
The Schottky junctions 10A and 10B between the first and second gate electrodes 11A and 11B and the semi-insulating barrier layer 3, respectively, form the first and second gate electrodes 11A and 11B.
Although a barrier for electrons is formed when the first and second n-type semiconductor regions 9A and 9B for the operation layer are viewed from the B side, the first and second n-type semiconductor regions 9A and 9B are formed because the semi-insulating barrier layer 3 exists for electrons. The height of the barrier formed by the Schottky junctions 10A and 10B from the side of the first and second n-type semiconductor regions 9A and 9B for the operating layer from the side of the gate electrodes 11A and 11B, respectively, is equal to that of the semi-insulating barrier layer 3. It is configured to be higher than when it is not provided. Therefore, when the first and second Schottky field effect transistors MA and MB are used as binary logic circuit elements (ON / OFF elements), the logic amplitude is reduced when the semi-insulating barrier layer 2 is not provided. Therefore, the operating margin as a binary logic circuit element can be increased.

As described above, according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, the semiconductor integrated circuit device is formed by the first and second Schottky junction field effect transistors MA and MB. It can be easily manufactured as a device having a function as a binary logic circuit element having a high operation margin.

[0073]

Second Embodiment Next, a second embodiment of the method of manufacturing a semiconductor integrated circuit device according to the present invention will be described with reference to FIGS.

In FIGS. 4 to 6, parts corresponding to those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 4 to 6 takes the following sequential steps to produce first and second Schottky junction field effect transistors having mutually different characteristics. To manufacture a semiconductor integrated circuit device having the same.

That is, similar to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, a similar semi-insulating semiconductor substrate body 1 is prepared (FIG. 4A).

Then, on the semi-insulating semiconductor substrate body 1 in accordance with the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. Semi-insulating semiconductor layer 2 and semi-insulating barrier layer 3 and semi-insulating barrier layer 3 as in the case of the method of manufacturing a circuit device.
As a fourth semi-insulating group III-V compound semiconductor having a narrow energy band gap and a thickness of, for example, 100 A, as compared with the third semi-insulating group III-V compound semiconductor constituting The semi-insulating protective layer 15 made of GaAs is formed in that order by the epitaxial growth method, and thus the semi-insulating semiconductor layer 2, the semi-insulating barrier layer 3, and the semi-insulating protective layer 3 are formed on the semi-insulating semiconductor substrate body 1. A semiconductor substrate 4 having a configuration in which the layer 15 and the layer 15 are stacked in that order is obtained (FIG. 4B).

Next, the same first mask layer 5A is formed on the semiconductor substrate 4 as in the case of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3 (FIG. 4C).

Next, the semiconductor substrate 4 is masked by the first mask layer 5A in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. By similarly implanting n-type impurity ions 6A, a similar first n-type impurity ion implanted region 7A is formed in a similar region in the semiconductor substrate 4 (FIG. 4D).

Next, the first mask layer 5A is removed from the semiconductor substrate 4 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3 (FIG. 5E).

Next, the same second mask layer 5B is formed on the semiconductor substrate 4 at the same position as in the case of the semiconductor integrated circuit device according to the present invention shown in FIGS. 5F).

Next, as in the case of the semiconductor integrated circuit device according to the present invention shown in FIGS.
While being masked by the second mask layer 5B,
By similarly implanting ions 6B of the same n-type impurity, a similar second n-type impurity ion implanted region 7B is formed in the same region in the semiconductor substrate 4 (FIG. 5G).

Next, the second mask layer 5B is removed from the semiconductor substrate 4 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3 (FIG. 5H).

Next, a heat treatment protection layer 8 is formed on the semiconductor substrate 4 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3 (FIG. 6I).

Next, the semiconductor substrate 4 shown in FIGS.
The first and second n-type impurity ion implanted regions 7A and 7B are activated by the same heat treatment as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIG. From the first n-type impurity ion-implanted region 7A to the first operating-layer n-type semiconductor region 9A.
And a second n-type semiconductor region for operating layer 9B is formed from the second n-type impurity ion implanted region 7B (FIG. 6J).

Next, the heat treatment protective layer 8 is removed from the semiconductor substrate 4 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. According to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, a Schottky junction is formed on the semi-insulating protective layer 15 and the first and second n-type semiconductor regions 9A and 9B for operation layers, respectively. Gate electrode layers 11A and 11B made of the same material and connected so as to form 10A and 10B, and n-type semiconductor region 9A for the first operation layer and first gate electrode 11A are sandwiched therebetween. The first source electrodes 12 ohmically connected to each other through the semi-insulating protective layer 15 and the semi-insulating barrier layer 3 at both positions.
A and the first drain electrode 13A and the second operating layer n
Source electrodes 12B ohmicly connected to each other through the semi-insulating protective layer 15 and the semi-insulating barrier layer 3 at both positions sandwiching the type semiconductor region 9B and the second gate electrode 11B. And a second drain electrode 13B (FIG. 6K).

The above is the second embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention.

The method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 4 to 6 has a structure in which a semiconductor substrate 4 is formed by stacking a semi-insulating semiconductor layer 2 and a semi-insulating barrier layer 3 in that order. Instead of the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3 which is formed as a semiconductor device, the semi-insulating semiconductor layer 2, the semi-insulating barrier layer 3, and the semi-insulating protective layer In this case, the first and second gate electrodes 11A and 11B are connected to the semi-insulating barrier layer 3 and the first and second Schottky junctions 10A. 1 to 3 formed as being connected to form each of FIGS.
Instead of the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIG. 1, the semi-insulating protective layer 15 and the first and second Schottky junctions 10A and 10B are formed so as to be connected to each other. Except for this point, the process is the same as that of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS.

Therefore, according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 4 to 6, detailed description is omitted, but the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. Has the same effect as described above.

However, in the semiconductor integrated circuit device manufactured by the method of manufacturing the Schottky junction field effect transistor according to the present invention shown in FIGS. 4 to 6, the first and second Schottky junction field effect transistors MA and MB are used.
Means that the first and second gate electrodes 11A and 11B have a semi-insulating protective layer 15 connected to form first and second Schottky junctions 10A and 10B, respectively. Having a configuration. For this reason, the first and second
When the relatively high heat is applied to the first and second Schottky junction field effect transistors MA and MB, the first and second gate electrodes 11A and 11B and the semi-insulating protective layer 15 are separated from each other. Second gate electrodes 11A and 11B
And the element of the material constituting the semi-insulating protective layer 15 are made of a material using an element which does not easily react with each other. The first and second gate electrodes 11A and 11B can be made of a material such as WSiN as described above, and the semi-insulating protective layer 15 can be made of a material such as GaAs as described above. If the first and second Schottky field effect transistors MA and MB have relatively high heat (the first and second gate electrodes 11A and 11B are made of a material such as WSiN as described above, When the semi-insulating protective layer 15 is made of a material made of, for example, GaAs as described above, for example, at 800 ° C. or higher, the first and second gate electrodes 11A and 11A 11 Configure to have the material (e.g., WSi
The element N) and the element of the material (for example, GaAs) constituting the semi-insulating protective layer 15 can be effectively prevented from reacting with each other. Further, if the thickness of the semi-insulating protective layer 15 is made thicker as long as the effect of increasing the operation margin as the binary logic circuit element is not lost, that is, the semi-insulating protection layer The layer 15 is, for example, Ga
In the case of As, for example, if it has a thickness of 50 to 250 A, the first and second Schottky junction field effect transistors MA and MB have relatively high heat (such as 800 ° C. or higher as described above). , The first and second gate electrodes 11A and 11B and the semi-insulating barrier layer 3 are relatively high in the first and second Schottky junction field effect transistors MA and MB. When heat is applied, the first and second gate electrodes 11A and 11B
And the material constituting the semi-insulating barrier layer 3 are likely to react with each other. That is, as described above, the first and second gate electrodes 11
A and 11B are made of a material made of, for example, WSiN;
Further, even if the semi-insulating barrier layer 3 is made of a material made of, for example, InGaP, the element of the material constituting the first and second gate electrodes 11A and 11B and the semi-insulating barrier layer 3
That the elements of the material constituting the first and second gate electrodes 1 and 2 react with each other, that is, as described above.
When 1A and 11B are made of a material made of, for example, WSiN, and the semi-insulating barrier layer 3 is made of a material made of, for example, InGaP, the material of the first and second gate electrodes 11A and 11B (for example, It is possible to effectively avoid mutual reaction between elements constituting WSiN), particularly W and elements constituting the material of the semi-insulating barrier layer 3 (for example, InGaP), particularly In.

Therefore, according to the method of manufacturing the Schottky junction field effect transistor according to the present invention shown in FIGS.
The semiconductor integrated circuit device can be easily manufactured by assuming that the first and second Schottky field effect transistors MA and MB operate with desired characteristics even when relatively high heat is applied thereto. it can.

[0092]

Third Embodiment Next, a third embodiment of the method of manufacturing a semiconductor integrated circuit device according to the present invention will be described with reference to FIGS.

7 to 9, parts corresponding to those in FIGS. 1 to 3 are denoted by the same reference numerals.

In the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, a semiconductor integrated circuit device having a transistor is manufactured through the following sequential steps.

That is, similar to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3, a similar semi-insulating semiconductor substrate body 1 is prepared (FIG. 7A).

Then, on the semi-insulating semiconductor substrate main body 1, the same semi-insulating semiconductor layer 2 as in the case of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS.
A similar semi-insulating barrier layer 3 is formed in that order by an epitaxial growth method, so that the semi-insulating semiconductor layer 2 and the semi-insulating barrier layer 3 are laminated on the semi-insulating semiconductor substrate body 1 in that order. A semiconductor substrate 4 having the configuration described above is obtained (FIG. 7B).

Next, on the semiconductor substrate 4, the first method in the case of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS.
Similarly, the same first mask layer 5 is formed (FIG. 7C).

Next, the semiconductor substrate 4 is formed with n in the case of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS.
As in the case of the impurity ion implantation region 7A, the same ions 6 are masked by the first mask layer 5.
Is similarly implanted to form the same n-type impurity ion implanted region 7 in the semiconductor substrate 4 in the same region (FIG. 7D).

Next, the first mask layer 5 is removed from the semiconductor substrate 4 in the same manner as the first mask layer 5A in the case of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. (FIG. 8E).

Next, on the semiconductor substrate 4, two n-type impurity ion implanted regions 7 corresponding to two different regions are provided.
A second mask layer 5 having a required second pattern which does not mask one region is used for the method of manufacturing a semiconductor integrated circuit device using the semiconductor integrated circuit device according to the present invention shown in FIGS. It forms according to it (FIG. 8F).

Next, in the case where the semiconductor substrate 4 is masked by the second mask layer 5 ', the method of manufacturing the semiconductor integrated circuit device by the semiconductor integrated circuit device according to the present invention shown in FIGS. From the side of the semi-insulating barrier layer 3, for example, an Si ion 6 ′ as an n-type impurity is
An acceleration voltage of, for example, 30 KeV, which is higher than that of the ion 6 described above, and 1.5 × 10 ^13, for example, which is the same as the ion 6A described above
/ Cm ² , the first n-type impurity is introduced into the semiconductor substrate 4 from the semi-insulating barrier layer 3 side of the semi-insulating semiconductor layer 2 to the semi-insulating semiconductor substrate body 1 side. Only the required depth deeper than the ion implantation region 7 was taken,
In two mutually different regions extending into two mutually different regions of the first n-type impurity ion implantation region 7, the second and third n-type impurity ion implantation regions 7S
And 7D (FIG. 8G).

Next, the second mask layer 5 'is removed from the semiconductor substrate 4 in the same manner as the second mask layer 5B in the case of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. (FIG. 8H).

Next, a heat treatment protection layer 8 is formed on the semiconductor substrate 4 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 1 to 3 (FIG. 9I).

Next, with respect to the semiconductor substrate 4, FIGS.
The first, second, and third n-type impurity ion implanted regions 7, 7S, and 7D are activated by the same heat treatment as in the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIG. In the region of the semi-insulating semiconductor substrate main body 1 having a required depth from the semi-insulating barrier layer 3 side to the semi-insulating semiconductor substrate main body 1 side, the first n-type impurity ion implanted region 7 An n-type semiconductor region 9 is formed, and an n-type semiconductor region for source electrode 9S and an n-type semiconductor region for drain electrode 9D are formed from the second and third n-type impurity ion implanted regions 7S and 7D, respectively ( (FIG. 9J).

Next, after the heat treatment protective layer 8 is removed from the semiconductor substrate 4, the heat treatment protective layer 8 is removed on the semiconductor substrate 4 in accordance with the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. A gate electrode layer 11 made of, for example, WSiN, which is connected to form a Schottky junction 10 on the semi-insulating barrier layer 3 and the n-type semiconductor region 9 for an operation layer, and an n-type semiconductor region for a source electrode A source electrode 12 and a drain electrode 13 are formed which are connected to the 9S and the n-type semiconductor region 9D for the drain electrode through the semi-insulating barrier layer 3 and the ohmic contact, respectively (FIG. 9K). In FIG. 9K, 1
Reference numeral 4 denotes a protective layer formed of an insulating material on the semiconductor substrate 4.

The above is the third embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention.

A semiconductor integrated circuit device (FIG. 8K) manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9 has an n-type semiconductor region 9 for an operation layer and an n-type semiconductor for a source electrode. A Schottky junction type field effect transistor M including a region 9S, an n-type semiconductor region 9D for a drain electrode, a gate electrode 11, a source electrode 11S, and a drain electrode 11D; Obviously, the source electrode n-type semiconductor region 9S and the drain electrode n-type semiconductor region 9D can be formed as having a sufficiently high n-type impurity concentration.

Therefore, according to the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, the semiconductor integrated circuit device is formed by a Schottky junction field effect transistor M having a low source electrode resistance and a low drain electrode resistance. It can be easily manufactured.

Further, according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, the Schottky junction type is manufactured according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. N-type semiconductor region 9 for operation layer and N-type semiconductor region 9 for source electrode constituting field effect transistor M
The n-type semiconductor region 9D for S and drain electrodes is formed based on the process of implanting ions 6 of the n-type impurity into the semi-insulating semiconductor layer 2.

For this reason, although detailed description is omitted, FIGS.
According to the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIG. 9, the semiconductor integrated circuit device is manufactured in the same manner as the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. Assuming that the transistor M has desired characteristics, the above-described fourth conventionally proposed fourth transistor is used.
It can be easily manufactured as compared with the method of manufacturing a semiconductor integrated circuit device described above.

Further, in the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, the Schottky junction field effect transistor M has an n-type semiconductor region 9 for an operation layer. A semi-insulating semiconductor according to the first and second Schottky junction field effect transistors MA and MB in the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. It is formed in a semi-insulating semiconductor layer formed on the substrate body.

For this reason, although detailed description is omitted, FIGS.
According to the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIG. 9, the semiconductor integrated circuit device is manufactured by using the Schottky junction type field effect transistor M in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. In accordance with the above, it is possible to easily manufacture the semiconductor device having characteristics different from those in the case where the semiconductor layer 9 for the operation layer is formed in the semi-insulating semiconductor substrate main body 1 and having excellent characteristics. it can.

In the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, the Schottky junction field effect transistor M is the same as that shown in FIGS. According to the first and second Schottky junction field effect transistors MA and MB in the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device, the n-type semiconductor region 9 for the operation layer No surface is formed, and a semi-insulating barrier layer 3 or a semi-insulating barrier layer and a semi-insulating protective layer are provided between the active layer n-type semiconductor region 9 and the surface of the semiconductor substrate 4. It is configured to be interposed.

For this reason, although detailed description is omitted, FIGS.
According to the method for manufacturing a semiconductor integrated circuit device according to the present invention shown in FIG. 9, the semiconductor integrated circuit device is formed on the surface of the semiconductor substrate 4 according to the method for manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. A Schottky junction field effect transistor M
In operation, they can easily be manufactured as if they did not produce non-negligible noise due to defective layers.

Further, in the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, the Schottky junction field effect transistor M is the same as that shown in FIGS. As in the case of the first and second Schottky junction field effect transistors MA and MB in the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device, the gate electrode 11 The gate electrode 11 is formed so as to be connected to the insulating barrier layer 3 so as to form a Schottky junction 10 therebetween.
The Schottky junction 10 between the semiconductor and the semi-insulating barrier layer 3
Although a barrier for electrons is formed when the n-type semiconductor region 9 for the operation layer is viewed from the gate electrode 11 side, since the semi-insulating barrier layer 3 exists for the electrons, the operation layer is formed from the gate electrode 11 side. The height of the barrier by the Schottky junction 10 as viewed from the side of the n-type semiconductor region 9 for use is higher than that without the semi-insulating barrier layer 3.

For this reason, although detailed description is omitted, FIGS.
According to the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIG. 9, a semiconductor integrated circuit device is manufactured by using a Schottky junction type field effect transistor M according to the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. According to the above, it can be easily manufactured as a device having a function as a binary logic circuit element having a high operation margin.

[0117]

Embodiment 4 Next, a fourth embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention will be described with reference to FIGS.

10 to 12, parts corresponding to those in FIGS. 7 to 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention shown in FIGS. 10 to 12, a semiconductor integrated circuit device having a Schottky junction type field effect transistor is manufactured through the following sequential steps.

That is, similar to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, the same semi-insulating semiconductor substrate body 1 is prepared (FIG. 10A).

Then, on the semi-insulating semiconductor substrate body 1 in accordance with the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, the semiconductor integrated circuit according to the present invention shown in FIGS. Semi-insulating semiconductor layer 2 and semi-insulating barrier layer 3 and semi-insulating barrier layer 3 as in the case of the method of manufacturing a circuit device.
As a fourth semi-insulating group III-V compound semiconductor having a narrow energy band gap and a thickness of, for example, 100 A, as compared with the third semi-insulating group III-V compound semiconductor constituting A semi-insulating protective layer 15 made of GaAs is formed in that order by an epitaxial growth method, so that the semi-insulating semiconductor layer 2, the semi-insulating barrier layer 3, and the semi-insulating protective layer 3 are formed on the semi-insulating semiconductor substrate body 1. A semiconductor substrate 4 having a configuration in which the layer 15 and the layer 15 are stacked in that order is obtained (FIG. 10B).

Next, the same first mask layer 5 is formed on the semiconductor substrate 4 as in the case of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9 (FIG. 10C).

Next, the semiconductor substrate 4 is masked by the first mask layer 5 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. The same first n-type impurity ion implantation region 7 is formed in the same region in the semiconductor substrate 4 by similarly implanting the ion 6 of the n-type impurity (FIG. 10D).

Next, the first mask layer 5 is removed from the semiconductor substrate 4 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9 (FIG. 11E).

Next, similar to the case of the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, a similar second mask layer 5 'is formed at a similar position on the semiconductor substrate 4 (FIG. 7 to FIG. 9). (FIG. 11F).

Next, as in the case of the semiconductor integrated circuit device according to the present invention shown in FIGS.
While being masked by the second mask layer 5, the same ion 6 ′ of the n-type impurity is similarly implanted, so that the same region is formed in the semiconductor substrate 4 in the same region.
Similar second and third n-type impurity ion implanted regions 7S and 7D are formed (FIG. 11G).

Next, the second mask layer 5 'is removed from the semiconductor substrate 4 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9 (FIG. 11H).

Next, a heat treatment protection layer 8 similar to that shown in FIGS. 7 to 9 is formed on the semiconductor substrate 4 in the same manner as in the method of manufacturing a semiconductor integrated circuit device according to the present invention (FIG. 12I).

Next, FIG. 7 to FIG.
In the same region, the same n-type semiconductor region 9 for the operating layer and the same n-type semiconductor region for the source electrode 9S and the drain electrode n-type semiconductor region 9D are formed (FIG. 12J).

Next, the heat treatment protective layer 8 is removed from the semiconductor substrate 4 in the same manner as in the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. According to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9, the semi-insulating protective layer 15 and the Schottky junction 10 are formed on the n-type semiconductor region 7 for the operation layer so as to be formed. Through a gate electrode layer 11 made of the same material, a source electrode n-type semiconductor region 9S and a drain electrode n-type semiconductor region 9D, a semi-insulating protective layer 15 and a semi-insulating barrier layer 3. A source electrode 12 and a drain electrode 13 that are connected to each other are formed (FIG. 12K).

The above is the fourth embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention.

The method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 10 to 12 has a structure in which a semiconductor substrate 4 is formed by stacking a semi-insulating semiconductor layer 2 and a semi-insulating barrier layer 3 in that order. Instead of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS.
The semi-insulating semiconductor layer 2, the semi-insulating barrier layer 3, and the semi-insulating protective layer 15 are formed in such a configuration that they are laminated in that order, and the gate electrode 11 is accordingly formed.
Instead of the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9 which is formed as being connected to form the Schottky junction 10 with the semi-insulating barrier layer 3,
This is the same as the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 7 to 9 except that the semi-insulating protective layer 15 and the Schottky junction 10 are connected so as to form the Schottky junction 10. .

Therefore, according to the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. 10 to 12, the detailed description is omitted, but the method of manufacturing the semiconductor integrated circuit device according to the present invention shown in FIGS. Has the same effect as described above.

However, the Schottky junction field effect transistor M manufactured by the method of manufacturing the Schottky junction field effect transistor according to the present invention shown in FIGS.
Has a configuration in which a gate electrode 11 has a semi-insulating protective layer 15 connected to form a Schottky junction 10. For this reason, the gate electrode 11 and the semi-insulating protective layer 15 are formed by the element of the material forming the gate electrode 11 when relatively high heat is applied to the Schottky junction field effect transistor M. And the element of the material constituting the semi-insulating protective layer 15, it is easy to react with each other.
That is, as described above, for example, WS
If the semi-insulating protective layer 15 is made of a material made of, for example, GaAs as described above, the Schottky junction field-effect transistor M has relatively high heat (the gate electrode 11). As described above, for example, WSi
When the semi-insulating protective layer 15 is made of a material such as GaAs as described above, for example, at a temperature of 800 ° C. or higher, the gate electrode 11 (for example, WS
It is possible to effectively prevent the element of iN) and the element of the material (for example, GaAs) constituting the semi-insulating protective layer 15 from reacting with each other. Further, if the thickness of the semi-insulating protective layer 15 is made thicker as long as the effect of increasing the operation margin as the binary logic circuit element is not lost, that is, the semi-insulating protection layer The layer 15 is, for example, Ga
In the case of As, for example, if it has a thickness of 50 to 250 A, even if relatively high heat (for example, 800 ° C. or more as described above) is given to the Schottky junction field effect transistor M, When relatively high heat is applied to the Schottky junction field effect transistor M, the gate electrode 1 and the semi-insulating barrier layer 3
1 and the material constituting the semi-insulating barrier layer 3 are likely to react with each other. That is, as described above, the gate electrode 11 is, for example, WS
Even if the semi-insulating barrier layer 3 is made of a material made of, for example, InGaP, the element of the material constituting the gate electrode 11 and the semi-insulating barrier layer 3 are made of iN.
That the elements of the material constituting the gate electrode 11 react with each other, that is, as described above, the gate electrode 11
When the semi-insulating barrier layer 3 is made of, for example, a material made of InGaP, the element made of the material (for example, WSiN) of the gate electrodes 11A and 11B, particularly, W And the elements constituting the material of the semi-insulating barrier layer 3 (for example, InGaP),
It is possible to effectively prevent n and n from reacting with each other.

Therefore, according to the method of manufacturing the Schottky junction field effect transistor according to the present invention shown in FIGS. 10 to 12, the semiconductor integrated circuit device and the Schottky junction field effect transistor M receive relatively high heat. Even so, it can be easily manufactured as it operates with the desired characteristics.

In the above description, only a few embodiments of the present invention have been described, and various modifications and changes may be made without departing from the spirit of the present invention.

[Brief description of the drawings]

FIG. 1 shows a first method of manufacturing a semiconductor integrated circuit device according to the present invention.
FIG. 9 is a schematic cross-sectional view in a sequential step for describing the example.

FIG. 2 is a first view illustrating a method of manufacturing a semiconductor integrated circuit device according to the present invention;
FIG. 2 is a schematic cross-sectional view in a sequential step following FIG. 1 for explaining the example.

FIG. 3 is a first view illustrating a method of manufacturing a semiconductor integrated circuit device according to the present invention;
FIG. 3 is a schematic cross-sectional view in a sequential step following FIG. 2 for describing the example.

FIG. 4 is a second view of the method for manufacturing a semiconductor integrated circuit device according to the present invention;
FIG. 9 is a schematic cross-sectional view in a sequential step for describing the example.

FIG. 5 shows a second method of manufacturing the semiconductor integrated circuit device according to the present invention.
FIG. 5 is a schematic cross-sectional view in a sequential step following FIG. 4 for describing the example.

FIG. 6 shows a second method of manufacturing a semiconductor integrated circuit device according to the present invention.
FIG. 6 is a schematic cross-sectional view in a sequential step following FIG. 5 for describing the example of FIG.

FIG. 7 shows a third method of manufacturing the semiconductor integrated circuit device according to the present invention.
FIG. 9 is a schematic cross-sectional view in a sequential step for describing the example.

FIG. 8 shows a third method of manufacturing the semiconductor integrated circuit device according to the present invention.
FIG. 8 is a schematic cross-sectional view in a sequential step following FIG. 7 for explaining the example.

FIG. 9 shows a third method of manufacturing a semiconductor integrated circuit device according to the present invention.
FIG. 9 is a schematic cross-sectional view in a sequential step following FIG. 8 for describing the example.

FIG. 10 is a schematic cross-sectional view in a sequential step for describing a fourth embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention.

FIG. 11 is a schematic cross-sectional view in a sequential step following FIG. 10 for describing a fourth embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention.

FIG. 12 is a schematic cross-sectional view in a sequential step following FIG. 11 for describing a fourth embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semi-insulating semiconductor substrate main body 2 semi-insulating semiconductor layer 3 semi-insulating barrier layer 4 semiconductor substrate 5, 5 ', 5A, 5B mask layer 6, 6', 6A, 6B n-type impurity ions 7, 7A, 7B , 7S, 7D n-type impurity ion implanted region 8 heat treatment protection layer 9, 9A, 9B n-type semiconductor region for operation layer 10, 10A, 10B Schottky junction 11, 11A, 11B Gate electrode 12, 12A, 12B source Electrode 13, 13A, 13B Drain electrode 14 Protective layer 15 Semi-insulating protective layer M, MA, MB Schottky field effect transistor

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuyoshi Asai Nippon Telegraph and Telephone Corporation, 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo (56) References JP-A-2-191346 (JP, A) JP-A-Hei 1-204475 (JP, A) JP-A-3-36761 (JP, A) JP-A-59-99717 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/337 -21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29/80-29/812

Claims (2)

(57) [Claims] A semi-insulating semiconductor substrate made of a first group III-V compound semiconductor, comprising: (a) a second group III-V compound semiconductor;
A semi-insulating semiconductor layer made of a group III compound semiconductor and a semi-insulating barrier layer made of a third group III-V compound semiconductor having a wider energy band gap than the second group III-V compound semiconductor, Or (b) a second III-V
A semi-insulating semiconductor layer made of a group III compound semiconductor, a semi-insulating barrier layer made of a third group III-V compound semiconductor having a wider energy band gap than the second group III-V compound semiconductor, A fourth III having a narrow energy band gap as compared with the group III-V compound semiconductor
A semi-insulating protective layer made of a group V compound semiconductor is formed in this order, and accordingly, (a) the semi-insulating semiconductor layer and the semi-insulating barrier layer are formed on the semi-insulating semiconductor substrate main body. Or (b) a step of obtaining a semiconductor substrate having a configuration in which the semi-insulating semiconductor layer, the semi-insulating barrier layer, and the semi-insulating protective layer are laminated in that order; Forming a first mask layer having a required first pattern, and a side of the semiconductor substrate opposite to the semi-insulating semiconductor substrate main body using the first mask layer as a mask. From the side of the semi-insulating semiconductor layer of the semi-insulating semiconductor layer to the body of the semi-insulating semiconductor substrate by a required depth into the semiconductor substrate. In the area taken, the first Forming an impurity ion implanted region, before or after the step of forming the first n-type impurity ion implanted region, on the semiconductor substrate, the first n
Forming a second mask layer having a required second pattern at a position different from that on the type impurity ion implantation region; and using the second mask layer for the semiconductor substrate as a mask. The second n-type impurity ions are implanted into the semiconductor substrate from the side opposite to the semi-insulating semiconductor substrate main body from the side opposite to the semi-insulating semiconductor layer from the semi-insulating barrier layer side of the semi-insulating semiconductor layer. Forming a second n-type impurity ion-implanted region in a region having a required depth on the conductive semiconductor substrate body side; and forming the first and second n-type impurity ion-implanted regions in the region. The heat treatment of the semiconductor substrate activates the first and second n-type impurity ion-implanted regions, so that the semiconductor substrate is placed in the semiconductor substrate from above the semi-insulating barrier layer side. In the semi-insulating semiconductor substrate body to the area taken by a required depth, the first
Forming a first operating layer n-type semiconductor region from the n-type impurity ion-implanted region, and forming a second operating layer n-type semiconductor region from the second n-type impurity ion-implanted region; First and second Schottky junctions are formed on the semiconductor substrate on the semi-insulating barrier layer or the semi-insulating protective layer and on the first and second n-type semiconductor regions for an operation layer, respectively. First and second connected respectively
A first source electrode, which is connected to each of the first source electrode and the first source electrode in an ohmic manner at both positions sandwiching the first n-type semiconductor region for the operating layer and the first gate electrode. A first source electrode, a second source electrode that is connected to each of the second source electrode and a second source electrode that is in ohmic connection with the second gate electrode at both positions across the second operating layer n-type semiconductor region; Forming a second drain electrode and a semiconductor integrated circuit device having a Schottky junction field effect transistor. 2. A semi-insulating semiconductor substrate made of a first III-V compound semiconductor, comprising: (a) a second III-V compound semiconductor;
A semi-insulating semiconductor layer made of a group III compound semiconductor and a semi-insulating barrier layer made of a third group III-V compound semiconductor having a wider energy band gap than the second group III-V compound semiconductor, Or (b) a second III-V
A semi-insulating semiconductor layer made of a group III compound semiconductor, a semi-insulating barrier layer made of a third group III-V compound semiconductor having a wider energy band gap than the second group III-V compound semiconductor, A fourth III having a narrow energy band gap as compared with the group III-V compound semiconductor
A semi-insulating protective layer made of a group V compound semiconductor is formed in this order, and accordingly, (a) the semi-insulating semiconductor layer and the semi-insulating barrier layer are formed on the semi-insulating semiconductor substrate main body. Or (b) a step of obtaining a semiconductor substrate having a configuration in which the semi-insulating semiconductor layer, the semi-insulating barrier layer, and the semi-insulating protective layer are laminated in that order; Forming a first mask layer having a required first pattern, and a side of the semiconductor substrate opposite to the semi-insulating semiconductor substrate main body using the first mask layer as a mask. From the side of the semi-insulating semiconductor layer of the semi-insulating semiconductor layer to the body of the semi-insulating semiconductor substrate by a required depth into the semiconductor substrate. In the area taken, the first Forming an impurity ion implanted region, before or after the step of forming the first n-type impurity ion implanted region, on the semiconductor substrate, the first n
Forming a second mask layer having a required second pattern which does not mask two regions corresponding to two mutually different regions of the impurity ion implantation region; The semi-insulating semiconductor is implanted into the semiconductor substrate by ion implantation of a second n-type impurity from a side opposite to the semi-insulating semiconductor substrate body using the second mask layer as a mask. The first n-type impurity ion implanted region extending from the semi-insulating barrier layer side of the layer to the semi-insulating semiconductor substrate body side at a required depth. Forming a second and third n-type impurity ion-implanted regions in two different regions, and forming the first and second n-type impurity ion-implanted regions, To Heat treatment activates the first, second, and third n-type impurity ion-implanted regions, so that the semi-insulating semiconductor layer is placed in the semiconductor substrate from the semi-insulating barrier layer side. Forming an n-type semiconductor region for an operating layer from the first n-type impurity ion implanted region in the region having a required depth in the conductive semiconductor substrate main body, and forming the second and third n-type impurity ion implanted regions; Forming an n-type semiconductor region for a source electrode and an n-type semiconductor region for a drain electrode from the respective regions; and forming the semi-insulating semi-insulating barrier layer or the semi-insulating protective layer on the semiconductor substrate. A gate electrode connected to form an Schottky junction on the n-type semiconductor region for the operation layer, the n-type semiconductor region for the source electrode and the n-type semiconductor region for the drain electrode, And o - source are connected respectively to the Mick - preparation of a semiconductor integrated circuit device having a Schottky junction field-effect transistor, characterized by a step of forming a source electrode and a drain electrode.